Inagua: Synchronize AMD/inagua mainboard.

[coreboot.git] / src / mainboard / amd / inagua / devicetree.cb

diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index 32d9a2672ce5a174f7fb29fc83c488bc6f4bb89a..62cf32d1f671fc3e43ccc7bb82167e6c16586663 100644 (file)
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -28,7 +28,7 @@ chip northbridge/amd/agesa/family14/root_complex
 #                       device pci 18.0 on #  northbridge
                                 chip northbridge/amd/agesa/family14 # PCI side of HT root complex
                                         device pci 0.0 on end # Root Complex
-                                        device pci 1.0 on end # Internal Graphics P2P bridge
+                                        device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
                                         device pci 1.1 on end # Internal Multimedia
                                         device pci 4.0 on end # PCIE P2P bridge 0x9604
                                         device pci 5.0 off end # PCIE P2P bridge 0x9605
@@ -65,14 +65,14 @@ chip northbridge/amd/agesa/family14/root_complex
                                                         end
                                                 end # kbc1100
                                        end #LPC
-                                       device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+                                       device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
                                        device pci 14.5 on end # USB 2
                                        device pci 15.0 on end # PCIe PortA
                                        device pci 15.1 on end # PCIe PortB
                                        device pci 15.2 on end # PCIe PortC
                                        device pci 15.3 on end # PCIe PortD
-                                       device pci 16.0 off end # OHCI USB3
-                                       device pci 16.2 off end # EHCI USB3
+                                       device pci 16.0 on end # OHCI USB3
+                                       device pci 16.2 on end # EHCI USB3
                                        register "gpp_configuration" = "4" #1:1:1:1
                                        register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
                                end     #southbridge/amd/cimx/sb800