{
/* do nothing, this should be called by chipset to save TOC in NVRAM */
}
+#else
+
+struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
+{
+ printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n");
+ return NULL;
+}
#endif
return (void *)NULL;
}
-#ifndef __PRE_RAM__
-#if CONFIG_HAVE_ACPI_RESUME
+#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
extern u8 acpi_slp_type;
#endif
-void cbmem_initialize(void)
+#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)
+/* Returns True if it was not intialized before. */
+int cbmem_initialize(void)
{
-#if CONFIG_HAVE_ACPI_RESUME
- if (acpi_slp_type == 3) {
- if (!cbmem_reinit(high_tables_base)) {
- /* Something went wrong, our high memory area got wiped */
+ int rv = 0;
+
+#ifdef __PRE_RAM__
+ extern unsigned long get_top_of_ram(void);
+ uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
+ uint64_t high_tables_size = HIGH_MEMORY_SIZE;
+#endif
+
+ /* We expect the romstage to always initialize it. */
+ if (!cbmem_reinit(high_tables_base)) {
+#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
+ /* Something went wrong, our high memory area got wiped */
+ if (acpi_slp_type == 3 || acpi_slp_type == 2)
acpi_slp_type = 0;
- cbmem_init(high_tables_base, high_tables_size);
- }
- } else {
+#endif
cbmem_init(high_tables_base, high_tables_size);
+ rv = 1;
}
-#else
- cbmem_init(high_tables_base, high_tables_size);
-#endif
+#ifndef __PRE_RAM__
cbmem_arch_init();
+#endif
+ return rv;
}
+#endif
#ifndef __PRE_RAM__
void cbmem_list(void)
case CBMEM_ID_PIRQ: printk(BIOS_DEBUG, "IRQ TABLE "); break;
case CBMEM_ID_MPTABLE: printk(BIOS_DEBUG, "SMP TABLE "); break;
case CBMEM_ID_RESUME: printk(BIOS_DEBUG, "ACPI RESUME"); break;
+ case CBMEM_ID_SMBIOS: printk(BIOS_DEBUG, "SMBIOS "); break;
default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id);
}
printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base);
}
#endif
-#endif