CBMEM CONSOLE: Enable coreboot CBMEM console.

[coreboot.git] / src / lib / Makefile.inc

diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index db640dc0059bae3dfcfcdf8006ac4e930c91ac82..45cb7887a0f23cea6d4f9e1d6491d96556425cf1 100644 (file)
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -11,6 +11,7 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c
 romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
@@ -34,6 +35,7 @@ ramstage-y += clog2.c
 ramstage-y += cbmem.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 ramstage-$(CONFIG_TRACE) += trace.c