Add support for enabling PCIe Common Clock and ASPM

[coreboot.git] / src / include / device / pci_def.h

diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index 6fb7ebd385a8e657123adc893095d22950a80a97..58a73218fe7ecec1b36850d5cc4f5eebe161149c 100644 (file)
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -26,7 +26,7 @@
 #define  PCI_STATUS_FAST_BACK  0x80    /* Accept fast-back to back */
 #define  PCI_STATUS_PARITY     0x100   /* Detected parity error */
 #define  PCI_STATUS_DEVSEL_MASK        0x600   /* DEVSEL timing */
-#define  PCI_STATUS_DEVSEL_FAST        0x000   
+#define  PCI_STATUS_DEVSEL_FAST        0x000
 #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
 #define  PCI_STATUS_DEVSEL_SLOW 0x400
 #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
@@ -55,8 +55,8 @@
 
 /*
  * Base addresses specify locations in memory or I/O space.
- * Decoded size can be determined by writing a value of 
- * 0xffffffff to the register, and reading it back.  Only 
+ * Decoded size can be determined by writing a value of
+ * 0xffffffff to the register, and reading it back.  Only
  * 1 bits are decoded.
  */
 #define PCI_BASE_ADDRESS_0     0x10    /* 32 bits */
@@ -80,7 +80,7 @@
 /* Header type 0 (normal devices) */
 #define PCI_CARDBUS_CIS                0x28
 #define PCI_SUBSYSTEM_VENDOR_ID        0x2c
-#define PCI_SUBSYSTEM_ID       0x2e  
+#define PCI_SUBSYSTEM_ID       0x2e
 #define PCI_ROM_ADDRESS                0x30    /* Bits 31..11 are address, 10..1 reserved */
 #define  PCI_ROM_ADDRESS_ENABLE        0x01
 #define PCI_ROM_ADDRESS_MASK   (~0x7ffUL)
@@ -189,7 +189,7 @@
 
 /* Hypertransport Registers */
 #define PCI_HT_CAP_SIZEOF         4
-#define PCI_HT_CAP_HOST_CTRL       4   /* Host link control */ 
+#define PCI_HT_CAP_HOST_CTRL       4   /* Host link control */
 #define PCI_HT_CAP_HOST_WIDTH     6    /* width value & capability  */
 #define PCI_HT_CAP_HOST_FREQ      0x09 /* Host frequency */
 #define PCI_HT_CAP_HOST_FREQ_CAP   0x0a        /* Host Frequency capability  */
@@ -201,6 +201,7 @@
 #define PCI_HT_CAP_SLAVE_FREQ1    0x011        /* Slave frequency to */
 #define PCI_HT_CAP_SLAVE_FREQ_CAP0 0x0e        /* Frequency capability from */
 #define PCI_HT_CAP_SLAVE_FREQ_CAP1 0x12        /* Frequency capability to */
+#define PCI_HT_CAP_SLAVE_LINK_ENUM   0x14 /* Link Enumeration Scratchpad */
 
 /* Power Management Registers */
 
@@ -347,6 +348,7 @@
 #define  PCI_EXP_DEVCAP_ATN_BUT        0x1000  /* Attention Button Present */
 #define  PCI_EXP_DEVCAP_ATN_IND        0x2000  /* Attention Indicator Present */
 #define  PCI_EXP_DEVCAP_PWR_IND        0x4000  /* Power Indicator Present */
+#define  PCI_EXP_DEVCAP_RBER   0x8000  /* Role-Based Error Reporting */
 #define  PCI_EXP_DEVCAP_PWR_VAL        0x3fc0000 /* Slot Power Limit Value */
 #define  PCI_EXP_DEVCAP_PWR_SCL        0xc000000 /* Slot Power Limit Scale */
 #define PCI_EXP_DEVCTL         8       /* Device Control */
@@ -369,8 +371,15 @@
 #define  PCI_EXP_DEVSTA_AUXPD  0x10    /* AUX Power Detected */
 #define  PCI_EXP_DEVSTA_TRPND  0x20    /* Transactions Pending */
 #define PCI_EXP_LNKCAP         12      /* Link Capabilities */
+#define  PCI_EXP_LNKCAP_ASPMS  0xc00   /* ASPM Support */
+#define  PCI_EXP_LNKCAP_L0SEL  0x7000  /* L0s Exit Latency */
+#define  PCI_EXP_LNKCAP_L1EL   0x38000 /* L1 Exit Latency */
 #define PCI_EXP_LNKCTL         16      /* Link Control */
+#define  PCI_EXP_LNKCTL_RL     0x20    /* Retrain Link */
+#define  PCI_EXP_LNKCTL_CCC    0x40    /* Common Clock COnfiguration */
 #define PCI_EXP_LNKSTA         18      /* Link Status */
+#define  PCI_EXP_LNKSTA_LT     0x800   /* Link Training */
+#define  PCI_EXP_LNKSTA_SLC    0x1000  /* Slot Clock Configuration */
 #define PCI_EXP_SLTCAP         20      /* Slot Capabilities */
 #define PCI_EXP_SLTCTL         24      /* Slot Control */
 #define PCI_EXP_SLTSTA         26      /* Slot Status */