#include <stdint.h>
#include <device/resource.h>
+#include <device/path.h>
+
struct device;
typedef struct device * device_t;
+struct pci_operations;
+struct pci_bus_operations;
+struct smbus_bus_operations;
+
+/* Chip operations */
+struct chip_operations {
+ void (*enable_dev)(struct device *dev);
+ const char *name;
+#if CONFIG_GENERATE_SMBIOS_TABLES
+ int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current);
+#endif
+};
+
+#define CHIP_NAME(X) .name = X,
+
+struct bus;
struct device_operations {
void (*read_resources)(device_t dev);
void (*set_resources)(device_t dev);
+ void (*enable_resources)(device_t dev);
void (*init)(device_t dev);
- unsigned int (*scan_bus)(device_t bus, unsigned int max);
+ unsigned int (*scan_bus)(device_t bus, unsigned int max);
void (*enable)(device_t dev);
+ void (*set_link)(device_t dev, unsigned int link);
+ void (*reset_bus)(struct bus *bus);
+#if CONFIG_GENERATE_SMBIOS_TABLES
+ int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current);
+#endif
+ const struct pci_operations *ops_pci;
+ const struct smbus_bus_operations *ops_smbus_bus;
+ const struct pci_bus_operations *ops_pci_bus;
};
-#define MAX_RESOURCES 6
+struct bus {
+ device_t dev; /* This bridge device */
+ device_t children; /* devices behind this bridge */
+ struct bus *next; /* The next bridge on this device */
+ unsigned bridge_ctrl; /* Bridge control register */
+ unsigned char link_num; /* The index of this link */
+ uint16_t secondary; /* secondary bus number */
+ uint16_t subordinate; /* max subordinate bus number */
+ unsigned char cap; /* PCi capability offset */
+ unsigned reset_needed : 1;
+ unsigned disable_relaxed_ordering : 1;
+};
+
/*
* There is one device structure for each slot-number/function-number
* combination:
*/
struct device {
- device_t bus; /* bus this device is on */
- device_t children; /* devices behind this bridge */
- device_t sibling; /* next device on this bus */
- device_t next; /* chain of all devices */
-
- unsigned int devfn; /* encoded device & function index */
- unsigned short vendor;
- unsigned short device;
- unsigned int class; /* 3 bytes: (base,sub,prog-if) */
+ struct bus * bus; /* bus this device is on, for bridge
+ * devices, it is the up stream bus */
+ device_t sibling; /* next device on this bus */
+ device_t next; /* chain of all devices */
+
+ struct device_path path;
+ unsigned vendor;
+ unsigned device;
+ u16 subsystem_vendor;
+ u16 subsystem_device;
+ unsigned int class; /* 3 bytes: (base, sub, prog-if) */
unsigned int hdr_type; /* PCI header type */
- unsigned int enable : 1; /* set if we should enable the device */
-
- unsigned char secondary; /* secondary bus number */
- unsigned char subordinate; /* max subordinate bus number */
- uint8_t command;
- /*
- * In theory, the irq level can be read from configuration
- * space and all would be fine. However, old PCI chips don't
- * support these registers and return 0 instead. For example,
- * the Vision864-P rev 0 chip can uses INTA, but returns 0 in
- * the interrupt line and pin registers. pci_init()
- * initializes this field with the value at PCI_INTERRUPT_LINE
- * and it is the job of pcibios_fixup() to change it if
- * necessary. The field must not be 0 unless the device
- * cannot generate interrupts at all.
- */
- unsigned int irq; /* irq generated by this device */
+ unsigned int enabled : 1; /* set if we should enable the device */
+ unsigned int initialized : 1; /* set if we have initialized the device */
+ unsigned int on_mainboard : 1;
- /* Base registers for this device, can be adjusted by
- * pcibios_fixup() as necessary.
+ u8 command;
+
+ /* Base registers for this device. I/O, MEM and Expansion ROM */
+ struct resource *resource_list;
+
+ /* links are (downstream) buses attached to the device, usually a leaf
+ * device with no children has 0 buses attached and a bridge has 1 bus
*/
- struct resource resource[MAX_RESOURCES];
- unsigned int resources;
- unsigned long rom_address;
+ struct bus *link_list;
+
struct device_operations *ops;
+ const struct chip_operations *chip_ops;
+ void *chip_info;
};
-extern struct device dev_root; /* root bus */
+/**
+ * This is the root of the device tree. The device tree is defined in the
+ * static.c file and is generated by the config tool at compile time.
+ */
+extern struct device dev_root;
extern struct device *all_devices; /* list of all devices */
+extern struct resource *free_resources;
+extern struct bus *free_links;
/* Generic device interface functions */
-extern void dev_enumerate(void);
-extern void dev_configure(void);
-extern void dev_enable(void);
-extern void dev_initialize(void);
+device_t alloc_dev(struct bus *parent, struct device_path *path);
+void dev_enumerate(void);
+void dev_configure(void);
+void dev_enable(void);
+void dev_initialize(void);
+void dev_optimize(void);
/* Generic device helper functions */
-void append_device(device_t dev);
-void compute_allocate_resource(device_t bus, struct resource *bridge,
- unsigned long type_mask, unsigned long type);
-void assign_resources(device_t bus);
+int reset_bus(struct bus *bus);
+unsigned int scan_bus(struct device *bus, unsigned int max);
+void assign_resources(struct bus *bus);
void enumerate_static_device(void);
+void enumerate_static_devices(void);
+const char *dev_path(device_t dev);
+const char *bus_path(struct bus *bus);
+void dev_set_enabled(device_t dev, int enable);
+void disable_children(struct bus *bus);
+
+/* Option ROM helper functions */
+void run_bios(struct device *dev, unsigned long addr);
/* Helper functions */
-device_t dev_find_device (unsigned int vendor, unsigned int device, device_t from);
+device_t find_dev_path(struct bus *parent, struct device_path *path);
+device_t alloc_find_dev(struct bus *parent, struct device_path *path);
+device_t dev_find_device (u16 vendor, u16 device, device_t from);
device_t dev_find_class (unsigned int class, device_t from);
device_t dev_find_slot (unsigned int bus, unsigned int devfn);
-
-/* Rounding for boundaries.
- * Due to some chip bugs, go ahead and roung IO to 16
+device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr);
+device_t dev_find_lapic(unsigned apic_id);
+int dev_count_cpu(void);
+
+/* Debug functions */
+void print_resource_tree(struct device * root, int debug_level,
+ const char *msg);
+void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum);
+void show_devs_subtree(struct device *root, int debug_level, const char *msg);
+void show_all_devs(int debug_level, const char *msg);
+void show_all_devs_tree(int debug_level, const char *msg);
+void show_one_resource(int debug_level, struct device *dev,
+ struct resource *resource, const char *comment);
+void show_all_devs_resources(int debug_level, const char* msg);
+
+/* Rounding for boundaries.
+ * Due to some chip bugs, go ahead and round IO to 16
*/
-#define DEVICE_IO_ALIGN 16
+#define DEVICE_IO_ALIGN 16
#define DEVICE_MEM_ALIGN 4096
+extern struct device_operations default_dev_ops_root;
+void pci_domain_read_resources(struct device *dev);
+unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max);
+unsigned int scan_static_bus(device_t bus, unsigned int max);
+
+void ram_resource(device_t dev, unsigned long index,
+ unsigned long basek, unsigned long sizek);
+void tolm_test(void *gp, struct device *dev, struct resource *new);
+u32 find_pci_tolm(struct bus *bus);
#endif /* DEVICE_H */
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