#define MTRR_WRITE_MEM (1 << 3)
#define SYSCFG_MSR 0xC0010010
+#define SYSCFG_MSR_TOM2WB (1 << 22)
#define SYSCFG_MSR_TOM2En (1 << 21)
#define SYSCFG_MSR_MtrrVarDramEn (1 << 20)
#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19)
#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
-#define IORR0_BASE 0xC0010016
-#define IORR0_MASK 0xC0010017
-#define IORR1_BASE 0xC0010018
-#define IORR1_MASK 0xC0010019
-#define TOP_MEM 0xC001001A
-#define TOP_MEM2 0xC001001D
+#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg))
+#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1)
+
+#define TOP_MEM_MSR 0xC001001A
+#define TOP_MEM2_MSR 0xC001001D
+#define TOP_MEM TOP_MEM_MSR
+#define TOP_MEM2 TOP_MEM2_MSR
#define TOP_MEM_MASK 0x007fffff
#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
-#ifndef __ROMCC__
+#if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__)
void amd_setup_mtrrs(void);
-#endif /* __ROMCC__ */
+#endif
#endif /* CPU_AMD_MTRR_H */