Detect whether the OXPCIE card is really present while in the ROM stage.

[coreboot.git] / src / drivers / oxford / oxpcie / oxpcie_early.c

diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
index 235c52c6549c10212175294c4a42df3b80653ba0..4f7a3cb105b525135a2690c98c142aadf9334cec 100644 (file)
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -20,6 +20,8 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
+#include <cpu/x86/car.h>
+#include <delay.h>
 #include <uart8250.h>
 #include <device/pci_def.h>
 
@@ -29,11 +31,18 @@
                CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION)
 
 #define OXPCIE_DEVICE \
-       PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0) 
+       PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0)
+
+#define OXPCIE_DEVICE_3 \
+       PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3)
+
+#if defined(__PRE_RAM__)
+int oxford_oxpcie_present CAR_GLOBAL;
 
 void oxford_init(void)
 {
        u16 reg16;
+       oxford_oxpcie_present = 1;
 
        /* First we reset the secondary bus */
        reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
@@ -57,7 +66,7 @@ void oxford_init(void)
 
        /* Memory window for the OXPCIe952 card */
        // XXX is the calculation of base and limit corect?
-       pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE, 
+       pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE,
                        ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) |
                        ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00)));
 
@@ -66,20 +75,44 @@ void oxford_init(void)
        reg16 |= PCI_COMMAND_MEMORY;
        pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
 
-       // FIXME Add a timeout or this will hang forever if 
-       // no device is in the slot.
+       u32 timeout = 20000; // Timeout in 10s of microseconds.
        u32 id = 0;
-       while ((id == 0) || (id == 0xffffffff))
+       for (;;) {
                id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
+               if (!timeout-- || (id != 0 && id != 0xffffffff))
+                       break;
+               udelay(10);
+       }
+
+       u32 device = OXPCIE_DEVICE; /* unknown default */
+       switch (id) {
+       case 0xc1181415: /* e.g. Startech PEX1S1PMINI */
+               /* On this device function 0 is the parallel port, and
+                * function 3 is the serial port. So let's go look for
+                * the UART.
+                */
+               id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID);
+               if (id != 0xc11b1415)
+                       return;
+               device = OXPCIE_DEVICE_3;
+               break;
+       case 0xc1581415: /* e.g. Startech MPEX2S952 */
+               device = OXPCIE_DEVICE;
+               break;
+       default:
+               /* No UART here. */
+               oxford_oxpcie_present = 0;
+               return;
+       }
 
        /* Setup base address on device */
-       pci_write_config32(OXPCIE_DEVICE, PCI_BASE_ADDRESS_0,
+       pci_write_config32(device, PCI_BASE_ADDRESS_0,
                                CONFIG_OXFORD_OXPCIE_BASE_ADDRESS);
 
        /* Enable memory on device */
-       reg16 = pci_read_config16(OXPCIE_DEVICE, PCI_COMMAND);
+       reg16 = pci_read_config16(device, PCI_COMMAND);
        reg16 |= PCI_COMMAND_MEMORY;
-       pci_write_config16(OXPCIE_DEVICE, PCI_COMMAND, reg16);
+       pci_write_config16(device, PCI_COMMAND, reg16);
 
        /* Now the UART initialization */
        u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
@@ -87,3 +120,4 @@ void oxford_init(void)
        uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD));
 }
 
+#endif