* stevel@mvista.com or source@mvista.com
* Copyright (C) 2004 Tyan Computer.
* Auther: Yinghai Lu yhlu@tyan.com
- * move to LinuxBIOS
+ * move to coreboot
* This code is distributed without warranty under the GPL v2 (see COPYING) *
*/
#include <delay.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
+// FIXME BTEXT console within coreboot has been obsoleted
+// and will go away. The BTEXT code in this file should be
+// fixed to export a framebuffer console through the coreboot
+// table (and possibly make it available for bootsplash use)
+// Hence do only remove this if you fix the code.
+#define CONFIG_CONSOLE_BTEXT 0
+
#if CONFIG_CONSOLE_BTEXT==1
#define PLL_CRTC_DECODE 0
#include "fbcon.h"
struct aty_cmap_regs {
- u8 windex;
- u8 lut;
- u8 mask;
- u8 rindex;
- u8 cntl;
+ u8 windex;
+ u8 lut;
+ u8 mask;
+ u8 rindex;
+ u8 cntl;
};
#include <console/btext.h>
0x10, 0x19
}
};
-
+
typedef struct {
u8 lcd_reg;
u32 val;
u32 temp;
union aty_pll pll;
const struct xl_card_cfg_t * card = &card_cfg[xl_card];
-
+
aty_st_8(CONFIG_STAT0, 0x85, info);
mdelay(10);
info->features &= ~M64F_MFB_TIMES_4;
}
#endif
-
+
/*
* Calculate mclk and xclk dividers, etc. The passed
* pixclock and bpp values don't matter yet, the vclk
aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, info);
aty_st_pll(SPLL_CNTL2, 0x03, info);
aty_st_pll(PLL_GEN_CNTL, 0x44, info);
-
+
reset_clocks(info, &pll.ct, 0);
mdelay(10);
aty_st_le32(0xEC, 0x00000000, info);
aty_st_le32(0xFC, 0x00000000, info);
- for (i=0; i<sizeof(lcd_tbl)/sizeof(lcd_tbl_t); i++) {
+ for (i=0; i<ARRAY_SIZE(lcd_tbl); i++) {
aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info);
}
aty_st_8(LCD_INDEX, 0x08, info);
aty_st_8(LCD_DATA, 0x0B, info);
mdelay(2);
-
+
// enable display requests, enable CRTC
aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
// disable display
#endif
struct fb_var_screeninfo default_var = {
- /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
- 640, 480, 640, 480, 0, 0, 8, 0,
- {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
- 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
- 0, FB_VMODE_NONINTERLACED
+ /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
+ 640, 480, 640, 480, 0, 0, 8, 0,
+ {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
+ 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
+ 0, FB_VMODE_NONINTERLACED
};
#endif /*CONFIG_CONSOLE_BTEXT*/
static struct {
- u16 pci_id, chip_type;
- u8 rev_mask, rev_val;
- const char *name;
- int pll, mclk, xclk;
- u32 features;
+ u16 pci_id, chip_type;
+ u8 rev_mask, rev_val;
+ const char *name;
+ int pll, mclk, xclk;
+ u32 features;
} aty_chips[] = {
- /* 3D RAGE XL PCI-66/BGA */
- { 0x474f, 0x474f, 0x00, 0x00, m64n_xl_66, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
- /* 3D RAGE XL PCI-33/BGA */
- { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
+ /* 3D RAGE XL PCI-66/BGA */
+ { 0x474f, 0x474f, 0x00, 0x00, m64n_xl_66, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
+ /* 3D RAGE XL PCI-33/BGA */
+ { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
};
#if CONFIG_CONSOLE_BTEXT==1
-static void aty_calc_mem_refresh(struct fb_info_aty *info,
- u16 id,
- int xclk)
+static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk)
{
int i, size;
#if 0
info->mem_refresh_rate = i;
}
#endif /*CONFIG_CONSOLE_BTEXT */
-static void ati_ragexl_init(device_t dev) {
+static void ati_ragexl_init(device_t dev)
+{
u32 chip_id;
- u32 i;
int j;
u16 type;
u8 rev;
- const char *chipname = NULL, *xtal;
+ const char *chipname = NULL;
+#if CONFIG_CONSOLE_BTEXT
+ u32 i;
+ const char *xtal;
+#endif
int pll, mclk, xclk;
#if CONFIG_CONSOLE_BTEXT==1
#endif /*CONFIG_CONSOLE_BTEXT==1 */
struct fb_info_aty *info;
- struct fb_info_aty info_t;
- struct resource *res;
- info = &info_t;
+ struct fb_info_aty info_t;
+ struct resource *res;
+ info = &info_t;
#define USE_AUX_REG 1
- res = &dev->resource[0];
+ res = dev->resource_list;
if(res->flags & IORESOURCE_IO) {
- res = &dev->resource[1];
+ res = res->next;
}
#if CONFIG_CONSOLE_BTEXT==1
info->frame_buffer = res->base;
#endif /* CONFIG_CONSOLE_BTEXT */
-#if USE_AUX_REG==0
+#if USE_AUX_REG==0
info->ati_regbase = res->base+0x7ff000+0xc00;
-#else
- res = &dev->resource[2];
+#else
+ /* Fix this to look for the correct index. */
+ //if (dev->resource_list && dev->resource_list->next)
+ res = dev->resource_list->next->next;
if(res->flags & IORESOURCE_MEM) {
- info->ati_regbase = res->base+0x400; //using auxiliary register
+ info->ati_regbase = res->base+0x400; //using auxiliary register
}
#endif
#endif
#if 0
- printk_debug("ati_regbase = 0x%08x, frame_buffer = 0x%08x\r\n", info->ati_regbase, info->frame_buffer);
+ printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
#endif
chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
type = chip_id & CFG_CHIP_TYPE;
rev = (chip_id & CFG_CHIP_REV)>>24;
- for (j = 0; j < (sizeof(aty_chips)/sizeof(*aty_chips)); j++)
+ for (j = 0; j < ARRAY_SIZE(aty_chips); j++)
if (type == aty_chips[j].chip_type &&
(rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) {
chipname = aty_chips[j].name;
info->features = aty_chips[j].features;
goto found;
}
- printk_spew("ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
+ printk(BIOS_SPEW, "ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
return ;
found:
- printk_info("ati_ragexl_init: %s [0x%04x rev 0x%02x]\r\n", chipname, type, rev);
+ printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\n", chipname, type, rev);
#if 0
if (M64_HAS(INTEGRATED)) {
/* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
if (mclk == 67 && info->ram_type < SDRAM)
mclk = 63;
- }
+ }
#endif
#if CONFIG_CONSOLE_BTEXT==1
aty_calc_mem_refresh(info, type, xclk);
// info->dac_ops = &aty_dac_ct;
// info->pll_ops = &aty_pll_ct;
info->bus_type = PCI;
-
+
atyfb_xl_init(info);
#if CONFIG_CONSOLE_BTEXT==1
info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07);
-
+
info->ref_clk_per = 1000000000000ULL/14318180;
xtal = "14.31818";
#if 0
}
if (atyfb_decode_var(&var, &info->default_par, info)) {
-#if 0
- printk_debug("atyfb: can't set default video mode\n");
+#if 0
+ printk(BIOS_DEBUG, "atyfb: can't set default video mode\n");
#endif
return ;
}
#if PLL_CRTC_DECODE==1
- printk_spew("framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
+ printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
(((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
info->current_par.crtc.bpp,
info->current_par.crtc.bpp,
info->current_par.crtc.vxres*info->current_par.crtc.bpp/8,info->frame_buffer);
#else
- printk_spew("framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
+ printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
(((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
info->default_par.crtc.bpp,
#endif
btext_clearscreen();
-
+
map_boot_text();
#if 0
#endif
#endif /* CONFIG_CONSOLE_BTEXT */
-
+
}
#if CONFIG_CONSOLE_BTEXT==1
static int aty_var_to_crtc(const struct fb_info_aty *info,
const struct fb_var_screeninfo *var,
struct crtc *crtc)
-{
+{
u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
u32 left, right, upper, lower, hslen, vslen, sync, vmode;
u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
u32 pix_width, dp_pix_width, dp_chain_mask;
-
+
/* input */
xres = var->xres;
yres = var->yres;
lower = var->lower_margin;
hslen = var->hsync_len;
vslen = var->vsync_len;
- sync = var->sync;
+ sync = var->sync;
vmode = var->vmode;
-
+
/* convert (and round up) and validate */
xres = (xres+7) & ~7;
xoffset = (xoffset+7) & ~7;
if (vxres < xres+xoffset)
vxres = xres+xoffset;
h_disp = xres/8-1;
- if (h_disp > 0xff)
+ if (h_disp > 0xff)
FAIL("h_disp too large");
h_sync_strt = h_disp+(right/8);
if (h_sync_strt > 0x1ff)
pix_width = CRTC_PIX_WIDTH_8BPP;
dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
dp_chain_mask = 0x8080;
- }
+ }
#if SUPPORT_8_BPP_ABOVE==1
else if (bpp <= 16) {
bpp = 16;
dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
BYTE_ORDER_LSB_TO_MSB;
dp_chain_mask = 0x8080;
- }
+ }
#endif
else
FAIL("invalid bpp");
fix->smem_start = info->frame_buffer;
fix->smem_len = (u32)info->total_vram;
- /*
+ /*
* Reg Block 0 (CT-compatible block) is at ati_regbase_phys
* Reg Block 1 (multimedia extensions) is at ati_regbase_phys-0x400
*/
#endif
/*
* Set the User Defined Part of the Display
- */
-#if PLL_CRTC_DECODE==1
+ */
+#if PLL_CRTC_DECODE==1
static int atyfb_set_var(struct fb_var_screeninfo *var, int con,
struct fb_info *fb)
-{
+{
struct fb_info_aty *info = (struct fb_info_aty *)fb;
struct atyfb_par par;
#if 0
#endif
int err;
int activate = var->activate;
-
-#if 0
+
+#if 0
if (con >= 0)
display = &fb_display[con];
else
#if 0
display = fb->disp; /* used during initialization */
#endif
-
+
if ((err = atyfb_decode_var(var, &par, info)))
return err;
-
+
atyfb_encode_var(var, &par, (struct fb_info_aty *)info);
-
-#if 0
- printk_info("atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK);
+
+#if 0
+ printk(BIOS_INFO, "atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK);
#endif
if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
#if PLL_CRTC_DECODE==1
info->current_par = *par;
-#endif
+#endif
if (info->blitter_may_be_busy)
wait_for_idle(info);
}
#if 0
-static u16 red2[] = {
+static u16 red2[] = {
0x0000, 0xaaaa
};
static u16 green2[] = {
static u16 red4[] = {
0x0000, 0xaaaa, 0x5555, 0xffff
-};
+};
static u16 green4[] = {
0x0000, 0xaaaa, 0x5555, 0xffff
-};
+};
static u16 blue4[] = {
0x0000, 0xaaaa, 0x5555, 0xffff
-};
-
+};
+
static u16 red8[] = {
0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa
};
static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info_aty *info)
-{
+{
int i, scale;
-
+
if (regno > 255)
return 1;
- red >>= 8;
+ red >>= 8;
green >>= 8;
blue >>= 8;
#if 0
info->palette[regno].red = red;
info->palette[regno].green = green;
info->palette[regno].blue = blue;
-#endif
+#endif
i = aty_ld_8(DAC_CNTL, info) & 0xfc;
if (M64_HAS(EXTRA_BRIGHT))
i |= 0x2; /*DAC_CNTL|0x2 turns off the extra brightness for gt*/
#else
scale = (M64_HAS(INTEGRATED) && info->default_par.crtc.bpp == 16) ? 3 : 0;
#endif
- writeb(regno << scale, &info->aty_cmap_regs->windex);
- writeb(red, &info->aty_cmap_regs->lut);
- writeb(green, &info->aty_cmap_regs->lut);
- writeb(blue, &info->aty_cmap_regs->lut);
+ write8(&info->aty_cmap_regs->windex, regno << scale)
+ write8(&info->aty_cmap_regs->lut, red);
+ write8(&info->aty_cmap_regs->lut, green);
+ write8(&info->aty_cmap_regs->lut, blue);
return 0;
}
int (*setcolreg)(u_int, u_int, u_int, u_int, u_int,
struct fb_info_aty *),
struct fb_info_aty *info)
-{
+{
int i, start;
u16 *red, *green, *blue, *transp;
u_int hred, hgreen, hblue, htransp;
-
+
red = cmap->red;
green = cmap->green;
blue = cmap->blue;
return &default_8_colors;
#endif
return &default_16_colors;
-}
+}
static void do_install_cmap(int con, struct fb_info_aty *info)
{
#if PLL_CRTC_DECODE==1
int size = info->current_par.crtc.bpp == 16 ? 32 : 256;
-#else
+#else
int size = 256;
#endif
fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info);
.scan_bus = 0,
};
-static struct pci_driver ati_ragexl_graph_driver __pci_driver = {
+static const struct pci_driver ati_ragexl_graph_driver __pci_driver = {
.ops = &ati_ragexl_graph_ops,
.vendor = PCI_VENDOR_ID_ATI,
.device = PCI_DEVICE_ID_ATI_215XL,
projects / coreboot.git / blobdiff