* rework tsc based timer code to use inb instead of outb for calibration

[coreboot.git] / src / cpu / x86 / tsc / delay_tsc.c

diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index 946d2cf512c23190c85a8cb348b078f718810477..72b1f7196c0638e5e8edaeafeca1f6b7e9d1b6d4 100644 (file)
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -106,10 +106,10 @@ static unsigned long long calibrate_tsc(void)
        
        printk_spew("Calibrating delay loop...\n");
        start = rdtscll();
-       // no udivdi3, dammit.
+       // no udivdi3 because we don't like libgcc. (only in x86emu)
        // so we count to 1<< 20 and then right shift 20
        for(count = 0; count < (1<<20); count ++)
-               outb(0x80, 0x80);
+               inb(0x80);
        end = rdtscll();
 
 #if 0