1. This patch adds CAR for Intel P6 series processors.

[coreboot.git] / src / cpu / intel / model_6ex / cache_as_ram_disable.c

diff --git a/src/cpu/intel/model_6ex/cache_as_ram_disable.c b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
index 29e726a272e82f8fb419172209c5dfa5f95c7398..f859336adf75af12e6d8bde54a3f5c56180fb468 100644 (file)
--- a/src/cpu/intel/model_6ex/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
@@ -19,7 +19,7 @@
  * MA 02110-1301 USA
  */
 
-
+#include <arch/stages.h>
 
 /* called from assembler code */
 void stage1_main(unsigned long bist);