Intel cpus: apply some good programming practices in new CAR

[coreboot.git] / src / cpu / intel / car / cache_as_ram_ht.inc

diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index ed207db7b17dfeaf20dd2a126fcaff7dd8061bfa..a6cbd6bac5bb0e33efe41d970f3f65d7a950745e 100644 (file)
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -21,6 +21,10 @@
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/post_code.h>
+#include <cpu/x86/lapic_def.h>
+
+/* Macro to access Local APIC registers at default base. */
+#define LAPIC(x)               $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
 
 #define CPU_MAXPHYADDR 36
 #define CPU_PHYSMASK_HI  (1 << (CPU_MAXPHYADDR - 32) - 1)
@@ -38,9 +42,9 @@ cache_as_ram:
        post_code(0x20)
 
        /* Send INIT IPI to all excluding ourself. */
-       movl    $0x000C4500, %eax
-       movl    $0xFEE00300, %esi
-       movl    %eax, (%esi)
+       movl    LAPIC(ICR), %edi
+       movl    $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax
+       movl    %eax, (%edi)
 
        /* Zero out all fixed range and variable range MTRRs. */
        movl    $mtrr_table, %esi
@@ -86,17 +90,16 @@ clear_mtrrs:
        wrmsr
 
        /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
-        movl   %cr0, %eax
+       movl    %cr0, %eax
        andl    $(~((1 << 30) | (1 << 29))), %eax
        invd
        movl    %eax, %cr0
 
        /* Clear the cache memory reagion. */
-       movl    $CACHE_AS_RAM_BASE, %esi
-       movl    %esi, %edi
-       movl    $(CACHE_AS_RAM_SIZE / 4), %ecx
-       // movl $0x23322332, %eax
+       cld
        xorl    %eax, %eax
+       movl    $CACHE_AS_RAM_BASE, %edi
+       movl    $(CACHE_AS_RAM_SIZE / 4), %ecx
        rep     stosl
 
        /* Enable Cache-as-RAM mode by disabling cache. */
@@ -131,11 +134,10 @@ clear_mtrrs:
        /* Set up the stack pointer. */
 #if CONFIG_USBDEBUG
        /* Leave some space for the struct ehci_debug_info. */
-       movl    $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
+       movl    $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp
 #else
-       movl    $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
+       movl    $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp
 #endif
-       movl    %eax, %esp
 
        /* Restore the BIST result. */
        movl    %ebp, %eax
@@ -146,6 +148,7 @@ clear_mtrrs:
 
        /* Call romstage.c main function. */
        call    main
+       addl    $4, %esp
 
        post_code(0x2f)
 
@@ -167,18 +170,6 @@ clear_mtrrs:
        post_code(0x31)
 
        invd
-#if 0
-       xorl    %eax, %eax
-       xorl    %edx, %edx
-       movl    $MTRRphysBase_MSR(0), %ecx
-       wrmsr
-       movl    $MTRRphysMask_MSR(0), %ecx
-       wrmsr
-       movl    $MTRRphysBase_MSR(1), %ecx
-       wrmsr
-       movl    $MTRRphysMask_MSR(1), %ecx
-       wrmsr
-#endif
 
        post_code(0x33)
 
@@ -196,7 +187,7 @@ clear_mtrrs:
 
        post_code(0x38)
 
-       /* Enable Write Back and Speculative Reads for the first 1MB. */
+       /* Enable Write Back and Speculative Reads for low RAM. */
        movl    $MTRRphysBase_MSR(0), %ecx
        movl    $(0x00000000 | MTRR_TYPE_WRBACK), %eax
        xorl    %edx, %edx