projects / coreboot.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
remove trailing whitespace
[coreboot.git] / src / cpu / amd / model_10xxx / defaults.h
diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index 65290089f1c76c1c2bd4be2c720561b50878e025..6df1032d98e78b0880f340b05b0dc3fb0338f770 100644 (file)
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <northbridge/amd/amdmct/amddefs.h>
+#include <cpu/amd/mtrr.h>
 
 /*
  * Default MSR and errata settings.
@@ -66,7 +68,7 @@ static const struct {
          1 << 24, 0x00000000,
          1 << 24, 0x00000000 },        /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */
 
-       { LS_CFG, AMD_FAM10_GT_B0, AMD_PTYPE_ALL,
+       { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL,
          0 << 1, 0x00000000,
          1 << 1, 0x00000000 },         /* IDX_MATCH_ALL=0 */
 
@@ -86,6 +88,26 @@ static const struct {
        { CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC,
          0x00000000, 1 << (33-32),
          0x00000000, 1 << (33-32) },   /* [ExtendedFeatEn]=1 */
+
+       { BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL,
+         0x00000000, 1 << (35-32),
+         0x00000000, 1 << (35-32) },   /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() )  */
+
+       { OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL,
+         0x00000004, 0x00000000,
+         0x00000004, 0x00000000},      /* B0 or Above, OSVW_ID_Length is 0004h */
+
+       { OSVW_Status, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_MC,
+         0x0000000C, 0x00000000,
+         0x0000000C, 0x00000000},      /* Cx and Dx multiple-link processor */
+
+       { BU_CFG2, AMD_DR_Dx, AMD_PTYPE_ALL,
+         0x00000000, 1 << (50-32),
+         0x00000000, 1 << (50-32)},    /* D0 or Above, RdMmExtCfgQwEn*/
+
+       { CPU_ID_EXT_FEATURES_MSR, AMD_DR_Dx, AMD_PTYPE_ALL,
+         0x00000000, 1 << (51 - 32),
+         0x00000000, 1 << (51 - 32)},  /* G34_PKG | C32_PKG | S1G4_PKG | ASB2_PKG */
 };
 
 
@@ -255,8 +277,11 @@ static const struct {
        { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK,
          0x00000080, 0x00000080 },     /* [7] PSIVidEnable */
 
-       { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_ALL,
-         0x00001800, 0x000003800 },    /* [13:11] PllLockTime = 3 */
+       { 3, 0xA0, AMD_DR_Bx, AMD_PTYPE_ALL,
+         0x00002800, 0x000003800 },    /* [13:11] PllLockTime = 5 */
+
+       { 3, 0xA0, (AMD_FAM10_ALL & ~(AMD_DR_Bx)), AMD_PTYPE_ALL,
+         0x00000800, 0x000003800 },    /* [13:11] PllLockTime = 1 */
 
        /* Reported Temp Control Register */
        { 3, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
@@ -288,9 +313,9 @@ static const struct {
                                           [5] DisPciCfgCpuMstAbtRsp = 1,
                                           [1] SyncFloodOnUsPwDataErr = 1 */
 
-       /* errata 346 - Fam10 C2
+       /* errata 346 - Fam10 C2, C3
         *  System software should set F3x188[22] to 1b. */
-       { 3, 0x188, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
+       { 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL,
          0x00400000, 0x00400000 },
 
        /* L3 Control Register */
@@ -315,100 +340,100 @@ static const struct {
        u32 mask;
 } fam10_htphy_default[] = {
 
-       /* Errata 344 - Fam10 C2
+       /* Errata 344 - Fam10 C2/C3, D0/D1
         * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
-       { 0x60, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x60, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x61, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x61, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x62, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x62, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x63, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x63, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x64, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x64, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x65, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x65, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x66, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x66, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x67, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x67, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x68, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x68, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
-       { 0x70, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x70, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x71, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x71, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x72, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x72, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x73, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x73, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x74, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x74, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x75, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x75, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x76, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x76, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x77, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x77, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x78, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x78, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
-       /* Errata 354 - Fam10 C2
+       /* Errata 354 - Fam10 C2, C3
         * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
-       { 0x40, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x40, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x41, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x41, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x42, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x42, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x43, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x43, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x44, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x44, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x45, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x45, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x46, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x46, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x47, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x47, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x48, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x48, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
-       { 0x50, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x50, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x51, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x51, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x52, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x52, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x53, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x53, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x54, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x54, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x55, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x55, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x56, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x56, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x57, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x57, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
-       { 0x58, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x58, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00000040, 0x00000040 },
 
-       /* Errata 327 - Fam10 C2
+       /* Errata 327 - Fam10 C2/C3, D0/D1
         * BIOS should set the Link Phy Impedance Register[RttCtl]
         * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
         * Link Phy Impedance Register[RttIndex]
         * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
-       { 0xC0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0xC0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x40040000, 0xe01F0000 },
-       { 0xD0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0xD0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x40040000, 0xe01F0000 },
 
-       { 0x520A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x520A,AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00004000, 0x00006000 },     /* HT_PHY_DLL_REG */
 
-       { 0x530A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
+       { 0x530A, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
          0x00004000, 0x00006000 },     /* HT_PHY_DLL_REG */
 
        { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
my coreboot WIP stuff (asus m5a99x-evo board)