+if ARCH_X86
+
source src/cpu/amd/Kconfig
-source src/cpu/emulation/Kconfig
source src/cpu/intel/Kconfig
source src/cpu/via/Kconfig
source src/cpu/x86/Kconfig
-config USE_DCACHE_RAM
+config CACHE_AS_RAM
bool
- default n
+ default !ROMCC
config DCACHE_RAM_BASE
hex
- default 0xffdf8000 if CPU_INTEL_CORE
config DCACHE_RAM_SIZE
hex
- default 0x8000 if CPU_INTEL_CORE
config DCACHE_RAM_GLOBAL_VAR_SIZE
hex
This option is used to enable certain functions to make coreboot
work correctly on symmetric multi processor (SMP) systems.
+config AP_SIPI_VECTOR
+ hex
+ default 0xfffff000
+ help
+ This must equal address of ap_sipi_vector from bootblock build.
+
config MMX
bool
help
config SSE2
bool
+ default n
help
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
streaming SIMD instructions. Some parts of coreboot can be built
help
Unset this if you don't want the MTRR code to use
subtractive MTRRs
+
+endif # ARCH_X86