Add support for RAM-less multi-processor init

[coreboot.git] / src / cpu / Kconfig

diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index 74198994bdd9ae417b8f479c779bf9dd38226010..0bdef347f0406fcba28ccb0a8306ec695ea1eda5 100644 (file)
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -1,21 +1,19 @@
+if ARCH_X86
+
 source src/cpu/amd/Kconfig
-source src/cpu/emulation/Kconfig
 source src/cpu/intel/Kconfig
 source src/cpu/via/Kconfig
 source src/cpu/x86/Kconfig
-source src/cpu/ppc/Kconfig
 
-config USE_DCACHE_RAM
+config CACHE_AS_RAM
        bool
-       default n
+       default !ROMCC
 
 config DCACHE_RAM_BASE
        hex
-       default 0xffdf8000 if CPU_INTEL_CORE
 
 config DCACHE_RAM_SIZE
        hex
-       default 0x8000 if CPU_INTEL_CORE
 
 config DCACHE_RAM_GLOBAL_VAR_SIZE
        hex
@@ -29,20 +27,37 @@ config SMP
        bool
        default y if MAX_CPUS != 1
        default n
+       help
+         This option is used to enable certain functions to make coreboot
+         work correctly on symmetric multi processor (SMP) systems.
 
+config AP_SIPI_VECTOR
+       hex
+       default 0xfffff000
+       help
+         This must equal address of ap_sipi_vector from bootblock build.
+                 
 config MMX
        bool
-       default n
        help
-               Set this in socket or model if the CPU has MMX. 
-               If the CPUs for the socket always have MMX, set it there. 
+         Select MMX in your socket or model Kconfig if your CPU has MMX
+         streaming SIMD instructions. ROMCC can build more efficient
+         code if it can spill to MMX registers.
 
 config SSE
+       bool
+       help
+         Select SSE in your socket or model Kconfig if your CPU has SSE
+         streaming SIMD instructions. ROMCC can build more efficient
+         code if it can spill to SSE (aka XMM) registers.
+
+config SSE2
        bool
        default n
        help
-               Set this in socket or model if the CPU has SSE. 
-               If the CPUs for the socket always have MX, set it there. 
+         Select SSE2 in your socket or model Kconfig if your CPU has SSE2
+         streaming SIMD instructions. Some parts of coreboot can be built
+         with more efficient code if SSE2 instructions are available.
 
 config VAR_MTRR_HOLE
        bool
@@ -50,3 +65,5 @@ config VAR_MTRR_HOLE
        help
                Unset this if you don't want the MTRR code to use
                subtractive MTRRs
+
+endif # ARCH_X86