CBMEM CONSOLE: Add config option for CBMEM stored console log.

[coreboot.git] / src / console / Kconfig

diff --git a/src/console/Kconfig b/src/console/Kconfig
index 3b8fb02dca0d5556133b81cd369bd9f0ac40fc05..fefbe2ed847557d7bdaaddf662d407c5ade53405 100644 (file)
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -1,10 +1,17 @@
-menu "Console options"
+menu "Console"
 # TODO: Rename to SERIAL_CONSOLE once Kconfig transition is complete.
 config CONSOLE_SERIAL8250
        bool "Serial port console output"
+       depends on HAVE_UART_IO_MAPPED
        default y
        help
-         Send coreboot debug output to a serial port console.
+         Send coreboot debug output to an I/O mapped serial port console.
+
+config CONSOLE_SERIAL8250MEM
+       bool "Serial port console output (memory mapped)"
+       depends on HAVE_UART_MEMORY_MAPPED
+       help
+         Send coreboot debug output to a memory mapped serial port console.
 
 choice
        prompt "Serial port"
@@ -43,7 +50,7 @@ config TTYS0_BASE
 choice
        prompt "Baud rate"
        default CONSOLE_SERIAL_115200
-       depends on CONSOLE_SERIAL8250
+       depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM
 
 config CONSOLE_SERIAL_115200
        bool "115200"
@@ -82,7 +89,7 @@ config TTYS0_BAUD
 config TTYS0_LCS
        int
        default 3
-       depends on CONSOLE_SERIAL8250
+       depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM
 
 # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code.
 config HAVE_USBDEBUG
@@ -112,13 +119,13 @@ config USBDEBUG
 
          If unsure, say N.
 
-# Note: This option doesn't make sense on Intel ICH southbridges as those
-# hardcode the physical USB port to be used as Debug Port to 1. It cannot
-# be changed by coreboot.
+# Note: This option doesn't make sense on Intel ICH / AMD SB600 southbridges
+# as those hardcode the physical USB port to be used as Debug Port to 1.
+# It cannot be changed by coreboot.
 config USBDEBUG_DEFAULT_PORT
        int "Default USB port to use as Debug Port"
        default 1
-       depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX
+       depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX && !SOUTHBRIDGE_AMD_SB600
        help
          This option selects which physical USB port coreboot will try to
          use as EHCI Debug Port first (valid values are: 1-15).
@@ -133,13 +140,9 @@ config USBDEBUG_DEFAULT_PORT
          on your mainboard) is highly board-specific, and you'll likely
          have to find out by trial-and-error.
 
-config CONSOLE_VGA
-       bool "Use VGA console once initialized"
-       default n
-
 # TODO: Deps?
 # TODO: Improve description.
-config CONSOLE_VGA_ONBOARD_AT_FIRST
+config ONBOARD_VGA_IS_PRIMARY
        bool "Use onboard VGA as primary video device"
        default n
        help
@@ -187,6 +190,33 @@ config CONSOLE_NE2K_IO_PORT
          32 bytes of IO spaces will be used (and align on 32 bytes
          boundary, qemu needs broader align)
 
+config CONSOLE_CBMEM
+       depends on EARLY_CBMEM_INIT
+       bool "Send console output to a CBMEM buffer"
+       default n
+       help
+         Enable this to save the console output in a CBMEM buffer. This would
+         allow to see coreboot console output from Linux space.
+
+config CONSOLE_CBMEM_BUFFER_SIZE
+       depends on CONSOLE_CBMEM
+       hex "Room allocated for console output in CBMEM"
+       default 0xae00
+       help
+         Space allocated for console output storage in CBMEM. The default
+         value (almost 45K or 0xaeoo bytes) is large enough to accommodate
+         even the BIOS_SPEW level.
+
+config CONSOLE_CAR_BUFFER_SIZE
+       depends on CONSOLE_CBMEM
+       hex "Room allocated for console output in cash as RAM"
+       default 0xc00
+       help
+         Console is used before RAM is initialized. This is the room reserved
+         in the DCACHE based RAM to keep console output before it can be
+         saved in a CBMEM buffer. 3K bytes should be enough even for the
+         BIOS_SPEW level.
+
 
 choice
        prompt "Maximum console log level"
@@ -322,14 +352,6 @@ config DEFAULT_CONSOLE_LOGLEVEL
        help
          Map the log level config names to an integer.
 
-config CONSOLE_BTEXT
-       bool
-       default n
-
-config CONSOLE_SROM
-       bool
-       default n
-
 config CONSOLE_LOGBUF
        bool
        default n
@@ -338,14 +360,18 @@ config NO_POST
        bool "Don't show any POST codes"
        default n
 
-config SERIAL_POST
-       bool "Show POST codes on the serial port console"
-       depends on CONSOLE_SERIAL8250 && !NO_POST
+config POST_PORT
+       hex
+       default 0x80
+
+config CONSOLE_POST
+       bool "Show POST codes on the debug console"
+       depends on !NO_POST
        default n
        help
          If enabled, coreboot will additionally print POST codes (which are
          usually displayed using a so-called "POST card" ISA/PCI/PCI-E
-         device) on the serial console.
+         device) on the debug console.
 
 endmenu