CBMEM CONSOLE: Add code using the new console driver.

[coreboot.git] / src / boot / hardwaremain.c

diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 50126261d7e2670f269f5c1a03c8835e2f0a1327..9b293c049a61833899abc886fb0cb7395ead7afe 100644 (file)
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -22,44 +22,53 @@ it with the version available from LANL.
 
 
 /*
- * C Bootstrap code for the LinuxBIOS
+ * C Bootstrap code for the coreboot
  */
 
-
 #include <console/console.h>
 #include <version.h>
-#include <boot/tables.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <delay.h>
 #include <stdlib.h>
-#include <part/hard_reset.h>
-#include <part/init_timer.h>
+#include <reset.h>
+#include <boot/tables.h>
 #include <boot/elf.h>
+#include <cbfs.h>
+#if CONFIG_HAVE_ACPI_RESUME
+#include <arch/acpi.h>
+#endif
+#if CONFIG_WRITE_HIGH_TABLES
+#include <cbmem.h>
+#endif
+
+/**
+ * @brief Main function of the RAM part of coreboot.
+ *
+ * Coreboot is divided into Pre-RAM part and RAM part.
+ *
+ * Device Enumeration:
+ *     In the dev_enumerate() phase,
+ */
+
+void hardwaremain(int boot_complete);
 
 void hardwaremain(int boot_complete)
 {
-       /* the order here is a bit tricky. We don't want to do much of 
-        * anything that uses config registers until after PciAllocateResources
-        * since that function also figures out what kind of config strategy
-        * to use (type 1 or type 2). 
-        * so we turn on cache, then worry about PCI setup, then do other 
-        * things, so that the other work can use the PciRead* and PciWrite*
-        * functions. 
-        */
        struct lb_memory *lb_mem;
 
-       post_code(0x80);
+       post_code(POST_ENTRY_RAMSTAGE);
 
-       /* displayinit MUST PRECEDE ALL PRINTK! */
+       /* console_init() MUST PRECEDE ALL printk()! */
        console_init();
-       
-       post_code(0x39);
-       printk_notice("LinuxBIOS-%s%s %s %s...\n", 
-               linuxbios_version, linuxbios_extra_version, linuxbios_build,
-               (boot_complete)?"rebooting":"booting");
 
-       post_code(0x40);
+       post_code(POST_CONSOLE_READY);
+
+       printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n",
+                     coreboot_version, coreboot_extra_version, coreboot_build,
+                     (boot_complete)?"rebooting":"booting");
+
+       post_code(POST_CONSOLE_BOOT_MSG);
 
        /* If we have already booted attempt a hard reboot */
        if (boot_complete) {
@@ -67,29 +76,36 @@ void hardwaremain(int boot_complete)
        }
 
        /* FIXME: Is there a better way to handle this? */
-       init_timer(); 
+       init_timer();
 
        /* Find the devices we don't have hard coded knowledge about. */
        dev_enumerate();
-       post_code(0x66);
+       post_code(POST_DEVICE_ENUMERATION_COMPLETE);
        /* Now compute and assign the bus resources. */
        dev_configure();
-       post_code(0x88);
+       post_code(POST_DEVICE_CONFIGURATION_COMPLETE);
        /* Now actually enable devices on the bus */
        dev_enable();
        /* And of course initialize devices on the bus */
        dev_initialize();
-       post_code(0x89);
+       post_code(POST_DEVICES_ENABLED);
+
+#if CONFIG_WRITE_HIGH_TABLES == 1
+       cbmem_initialize();
+#if CONFIG_CONSOLE_CBMEM
+       cbmemc_reinit();
+#endif
+#endif
+#if CONFIG_HAVE_ACPI_RESUME == 1
+       suspend_resume();
+       post_code(0x8a);
+#endif
 
        /* Now that we have collected all of our information
         * write our configuration tables.
         */
        lb_mem = write_tables();
-
-#if CONFIG_FS_STREAM == 1
-       filo(lb_mem);
-#else
-       elfboot(lb_mem);
-#endif
+       cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload");
+       printk(BIOS_ERR, "Boot failed.\n");
 }