* C Bootstrap code for the coreboot
*/
-
#include <console/console.h>
#include <version.h>
-#include <boot/tables.h>
#include <device/device.h>
#include <device/pci.h>
#include <delay.h>
#include <stdlib.h>
-#include <part/hard_reset.h>
-#include <part/init_timer.h>
+#include <reset.h>
+#include <boot/tables.h>
#include <boot/elf.h>
#include <cbfs.h>
-#if HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
#include <arch/acpi.h>
#endif
+#if CONFIG_WRITE_HIGH_TABLES
+#include <cbmem.h>
+#endif
+#include <timestamp.h>
/**
- * @brief Main function of the DRAM part of coreboot.
+ * @brief Main function of the RAM part of coreboot.
*
- * Coreboot is divided into Pre-DRAM part and DRAM part.
+ * Coreboot is divided into Pre-RAM part and RAM part.
*
- *
* Device Enumeration:
- * In the dev_enumerate() phase,
+ * In the dev_enumerate() phase,
*/
+void hardwaremain(int boot_complete);
+
void hardwaremain(int boot_complete)
{
struct lb_memory *lb_mem;
-#if HAVE_ACPI_RESUME == 1
- void *wake_vec;
-#endif
+ tsc_t timestamps[6];
- post_code(0x80);
+ timestamps[0] = rdtsc();
+ post_code(POST_ENTRY_RAMSTAGE);
- /* displayinit MUST PRECEDE ALL PRINTK! */
+ /* console_init() MUST PRECEDE ALL printk()! */
console_init();
-
- post_code(0x39);
- printk_notice("coreboot-%s%s %s %s...\n",
+ post_code(POST_CONSOLE_READY);
+
+ printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n",
coreboot_version, coreboot_extra_version, coreboot_build,
(boot_complete)?"rebooting":"booting");
- post_code(0x40);
+ post_code(POST_CONSOLE_BOOT_MSG);
/* If we have already booted attempt a hard reboot */
if (boot_complete) {
}
/* FIXME: Is there a better way to handle this? */
- init_timer();
+ init_timer();
+ timestamps[1] = rdtsc();
/* Find the devices we don't have hard coded knowledge about. */
dev_enumerate();
- post_code(0x66);
+ post_code(POST_DEVICE_ENUMERATION_COMPLETE);
+
+ timestamps[2] = rdtsc();
/* Now compute and assign the bus resources. */
dev_configure();
- post_code(0x88);
+ post_code(POST_DEVICE_CONFIGURATION_COMPLETE);
+
+ timestamps[3] = rdtsc();
/* Now actually enable devices on the bus */
dev_enable();
+
+ timestamps[4] = rdtsc();
/* And of course initialize devices on the bus */
dev_initialize();
- post_code(0x89);
+ post_code(POST_DEVICES_ENABLED);
-#if HAVE_ACPI_RESUME == 1
-
-#if MEM_TRAIN_SEQ != 0
- #error "So far it works on AMD and MEM_TRAIN_SEQ == 0"
+ timestamps[5] = rdtsc();
+#if CONFIG_WRITE_HIGH_TABLES == 1
+ cbmem_initialize();
+#if CONFIG_CONSOLE_CBMEM
+ cbmemc_reinit();
#endif
-
-#if _RAMBASE < 0x1F00000
- #error "For ACPI RESUME you need to have _RAMBASE at least 31MB"
- #error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)"
- #error "And coreboot memory reserved in mainboard.c"
#endif
- /* if we happen to be resuming find wakeup vector and jump to OS */
- wake_vec = acpi_find_wakeup_vector();
- if (wake_vec)
- acpi_jump_to_wakeup(wake_vec);
+#if CONFIG_HAVE_ACPI_RESUME == 1
+ suspend_resume();
+ post_code(0x8a);
#endif
+ timestamp_add(TS_START_RAMSTAGE, timestamps[0]);
+ timestamp_add(TS_DEVICE_ENUMERATE, timestamps[1]);
+ timestamp_add(TS_DEVICE_CONFIGURE, timestamps[2]);
+ timestamp_add(TS_DEVICE_ENABLE, timestamps[3]);
+ timestamp_add(TS_DEVICE_INITIALIZE, timestamps[4]);
+ timestamp_add(TS_DEVICE_DONE, timestamps[5]);
+ timestamp_add_now(TS_WRITE_TABLES);
+
/* Now that we have collected all of our information
* write our configuration tables.
*/
lb_mem = write_tables();
-#if CONFIG_CBFS == 1
-# if USE_FALLBACK_IMAGE == 1
- void (*pl)(void) = cbfs_load_payload(lb_mem, "fallback/payload");
-# else
- void (*pl)(void) = cbfs_load_payload(lb_mem, "normal/payload");
-# endif
-#endif
-#if CONFIG_FS_PAYLOAD == 1
-#warning "CONFIG_FS_PAYLOAD is deprecated."
- filo(lb_mem);
-#else
-#warning "elfboot will soon be deprecated."
- elfboot(lb_mem);
-#endif
- printk_err("Boot failed.\n");
+ timestamp_add_now(TS_LOAD_PAYLOAD);
+ cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload");
+ printk(BIOS_ERR, "Boot failed.\n");
}