endmenu
source src/mainboard/Kconfig
-source src/arch/i386/Kconfig
+
+# This option is used to set the architecture of a mainboard to X86.
+# It is usually set in mainboard/*/Kconfig.
+config ARCH_X86
+ bool
+ default n
+
+if ARCH_X86
+source src/arch/x86/Kconfig
+endif
menu "Chipset"
source src/superio/Kconfig
comment "Devices"
source src/devices/Kconfig
+comment "Embedded Controllers"
+source src/ec/Kconfig
endmenu
int
default 0
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
- hex
- default 0x0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
- hex
- default 0x0
-
-config CPU_ADDR_BITS
- int
- default 36
-
-config LOGICAL_CPUS
- bool
- default y
-
config PCI_ROM_RUN
bool
default n
bool
default n
-config ATI_RAGE_XL
- bool
-
source src/console/Kconfig
config HAVE_ACPI_RESUME
choice
prompt "Add a payload"
- default PAYLOAD_NONE
+ default PAYLOAD_NONE if !ARCH_X86
+ default PAYLOAD_SEABIOS if ARCH_X86
config PAYLOAD_NONE
bool "None"
You will be able to specify the location and file name of the
payload image later.
+config PAYLOAD_SEABIOS
+ bool "SeaBIOS"
+ depends on ARCH_X86
+ help
+ Select this option if you want to build a coreboot image
+ with a SeaBIOS payload. If you don't know what this is
+ about, just leave it enabled.
+
+ See http://coreboot.org/Payloads for more information.
+
+config PAYLOAD_FILO
+ bool "FILO"
+ help
+ Select this option if you want to build a coreboot image
+ with a FILO payload. If you don't know what this is
+ about, just leave it enabled.
+
+ See http://coreboot.org/Payloads for more information.
+
+endchoice
+
+choice
+ prompt "SeaBIOS version"
+ default SEABIOS_STABLE
+ depends on PAYLOAD_SEABIOS
+
+config SEABIOS_STABLE
+ bool "stable"
+ help
+ Stable SeaBIOS version
+config SEABIOS_MASTER
+ bool "master"
+ help
+ Newest SeaBIOS version
endchoice
-config FALLBACK_PAYLOAD_FILE
+choice
+ prompt "FILO version"
+ default FILO_STABLE
+ depends on PAYLOAD_FILO
+
+config FILO_STABLE
+ bool "0.6.0"
+ help
+ Stable FILO version
+config FILO_MASTER
+ bool "HEAD"
+ help
+ Newest FILO version
+endchoice
+
+config PAYLOAD_FILE
string "Payload path and filename"
depends on PAYLOAD_ELF
default "payload.elf"
help
The path and filename of the ELF executable file to use as payload.
+config PAYLOAD_FILE
+ depends on PAYLOAD_SEABIOS
+ default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+
+config PAYLOAD_FILE
+ depends on PAYLOAD_FILO
+ default "payloads/external/FILO/filo/build/filo.elf"
+
# TODO: Defined if no payload? Breaks build?
config COMPRESSED_PAYLOAD_LZMA
bool "Use LZMA compression for payloads"
default y
- depends on PAYLOAD_ELF
+ depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
help
In order to reduce the size payloads take up in the ROM chip
coreboot can compress them using the LZMA algorithm.
You will be able to specify the location and file name of the
image later.
-config FALLBACK_VGA_BIOS_FILE
+config VGA_BIOS_FILE
string "VGA BIOS path and filename"
depends on VGA_BIOS
default "vgabios.bin"
help
The path and filename of the file to use as VGA BIOS.
-config FALLBACK_VGA_BIOS_ID
+config VGA_BIOS_ID
string "VGA device PCI IDs"
depends on VGA_BIOS
default "1106,3230"
You will be able to specify the location and file name of the
image later.
-config FALLBACK_MBI_FILE
+config MBI_FILE
string "Intel MBI path and filename"
depends on INTEL_MBI
default "mbi.bin"
This option shows a graphical bootsplash screen. The grapics are
loaded from the CBFS file bootsplash.jpg.
-config FALLBACK_BOOTSPLASH_FILE
+config BOOTSPLASH_FILE
string "Bootsplash path and filename"
depends on BOOTSPLASH
default "bootsplash.jpg"
default y
help
If enabled, you will be able to set breakpoints for gdb debugging.
- See src/arch/i386/lib/c_start.S for details.
+ See src/arch/x86/lib/c_start.S for details.
config HAVE_DEBUG_RAM_SETUP
def_bool n
config HAVE_DEBUG_CAR
def_bool n
+config DEBUG_CAR
+ def_bool n
+ depends on HAVE_DEBUG_CAR
+
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
config DEBUG_CAR
bool "Output verbose Cache-as-RAM debug messages"
default n
depends on HAVE_DEBUG_CAR
help
This option enables additional CAR related debug messages.
+endif
config DEBUG_PIRQ
bool "Check PIRQ table consistency"
If unsure, say N.
+config DEBUG_MALLOC
+ def_bool n
+
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+config DEBUG_MALLOC
+ bool "Output verbose malloc debug messages"
+ default n
+ help
+ This option enables additional malloc related debug messages.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+endif
+
+config REALMODE_DEBUG
+ def_bool n
+ depends on PCI_OPTION_ROM_RUN_REALMODE
+
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
config REALMODE_DEBUG
bool "Enable debug messages for option ROM execution"
default n
Note: This option will increase the time to emulate a ROM.
If unsure, say N.
+endif
config X86EMU_DEBUG
bool "Output verbose x86emu debug messages"
help
If enabled, you will have a low level shell to examine your machine.
Put llshell() in your (romstage) code to start the shell.
- See src/arch/i386/llshell/llshell.inc for details.
+ See src/arch/x86/llshell/llshell.inc for details.
endmenu
projects / coreboot.git / blobdiff