endmenu
source src/mainboard/Kconfig
-source src/arch/i386/Kconfig
+source src/arch/x86/Kconfig
menu "Chipset"
#
# endmenu
-#TODO Remove this option or make it useful.
-config HAVE_LOW_TABLES
- bool
- default y
- help
- This Option is unused in the code. Since two boards try to set it to
- 'n', they may be broken. We either need to make the option useful or
- get rid of it. The broken boards are:
- asus/m2v-mx_se
- supermicro/h8dme
-
-config HAVE_HIGH_TABLES
- bool
- default y
- help
- This variable specifies whether a given northbridge has high table
- support.
- It is set in northbridge/*/Kconfig.
- Whether or not the high tables are actually written by coreboot is
- configurable by the user via WRITE_HIGH_TABLES.
-
config HAVE_ACPI_TABLES
bool
help
bool
default HAVE_PIRQ_TABLE
-config WRITE_HIGH_TABLES
- bool
- default HAVE_HIGH_TABLES
-
menu "System tables"
config WRITE_HIGH_TABLES
bool "Write 'high' tables to avoid being overwritten in F segment"
- depends on HAVE_HIGH_TABLES
default y
config MULTIBOOT
default y
help
If enabled, you will be able to set breakpoints for gdb debugging.
- See src/arch/i386/lib/c_start.S for details.
+ See src/arch/x86/lib/c_start.S for details.
+
+config HAVE_DEBUG_RAM_SETUP
+ def_bool n
config DEBUG_RAM_SETUP
bool "Output verbose RAM init debug messages"
default n
- depends on (NORTHBRIDGE_AMD_AMDFAM10 \
- || NORTHBRIDGE_AMD_AMDK8 \
- || NORTHBRIDGE_VIA_CN700 \
- || NORTHBRIDGE_VIA_CX700 \
- || NORTHBRIDGE_VIA_VX800 \
- || NORTHBRIDGE_INTEL_E7501 \
- || NORTHBRIDGE_INTEL_I440BX \
- || NORTHBRIDGE_INTEL_I82810 \
- || NORTHBRIDGE_INTEL_I82830 \
- || NORTHBRIDGE_INTEL_I945)
+ depends on HAVE_DEBUG_RAM_SETUP
help
This option enables additional RAM init related debug messages.
It is recommended to enable this when debugging issues on your
If unsure, say N.
+config HAVE_DEBUG_CAR
+ def_bool n
+
+config DEBUG_CAR
+ def_bool n
+ depends on HAVE_DEBUG_CAR
+
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
+config DEBUG_CAR
+ bool "Output verbose Cache-as-RAM debug messages"
+ default n
+ depends on HAVE_DEBUG_CAR
+ help
+ This option enables additional CAR related debug messages.
+endif
+
config DEBUG_PIRQ
bool "Check PIRQ table consistency"
default n
help
If unsure, say N.
+config HAVE_DEBUG_SMBUS
+ def_bool n
+
config DEBUG_SMBUS
bool "Output verbose SMBus debug messages"
default n
- depends on (SOUTHBRIDGE_VIA_VT8237R \
- || NORTHBRIDGE_VIA_VX800 \
- || NORTHBRIDGE_VIA_CX700 \
- || NORTHBRIDGE_AMD_AMDK8 \
- || NORTHBRIDGE_AMD_AMDFAM10 \
- || BOARD_LIPPERT_SPACERUNNER_LX \
- || SOUTHBRIDGE_VIA_VT8231)
+ depends on HAVE_DEBUG_SMBUS
help
This option enables additional SMBus (and SPD) debug messages.
If unsure, say N.
+config DEBUG_MALLOC
+ def_bool n
+
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+config DEBUG_MALLOC
+ bool "Output verbose malloc debug messages"
+ default n
+ help
+ This option enables additional malloc related debug messages.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+endif
+
+config REALMODE_DEBUG
+ def_bool n
+ depends on PCI_OPTION_ROM_RUN_REALMODE
+
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
+config REALMODE_DEBUG
+ bool "Enable debug messages for option ROM execution"
+ default n
+ depends on PCI_OPTION_ROM_RUN_REALMODE
+ help
+ This option enables additional x86emu related debug messages.
+
+ Note: This option will increase the time to emulate a ROM.
+
+ If unsure, say N.
+endif
+
config X86EMU_DEBUG
bool "Output verbose x86emu debug messages"
default n
help
If enabled, you will have a low level shell to examine your machine.
Put llshell() in your (romstage) code to start the shell.
- See src/arch/i386/llshell/llshell.inc for details.
+ See src/arch/x86/llshell/llshell.inc for details.
endmenu
bool
default n
+config RAMINIT_SYSINFO
+ bool
+ default n
+
config ENABLE_APIC_EXT_ID
bool
default n
hex
default 0x10
+# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
+# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
+# mutually exclusive. One of these options must be selected in the
+# mainboard Kconfig if the chipset supports enabling and disabling of
+# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
+# in mainboard/Kconfig to know if the button should be enabled or not.
+
+config POWER_BUTTON_DEFAULT_ENABLE
+ def_bool n
+ help
+ Select when the board has a power button which can optionally be
+ disabled by the user.
+
+config POWER_BUTTON_DEFAULT_DISABLE
+ def_bool n
+ help
+ Select when the board has a power button which can optionally be
+ enabled by the user, e.g. when the board ships with a jumper over
+ the power switch contacts.
+
+config POWER_BUTTON_FORCE_ENABLE
+ def_bool n
+ help
+ Select when the board requires that the power button is always
+ enabled.
+
+config POWER_BUTTON_FORCE_DISABLE
+ def_bool n
+ help
+ Select when the board requires that the power button is always
+ disabled, e.g. when it has been hardwired to ground.
+
+config POWER_BUTTON_IS_OPTIONAL
+ bool
+ default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
+ default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
+ help
+ Internal option that controls ENABLE_POWER_BUTTON visibility.
+
source src/Kconfig.deprecated_options
projects / coreboot.git / blobdiff