## ## This file is part of the coreboot project. ## ## Copyright (C) 2009-2010 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## mainmenu "Coreboot Configuration" menu "General setup" config EXPERT bool "Expert mode" help This allows you to select certain advanced configuration options. Warning: Only enable this option if you really know what you are doing! You have been warned! config LOCALVERSION string "Local version string" help Append an extra string to the end of the coreboot version. This can be useful if, for instance, you want to append the respective board's hostname or some other identifying string to the coreboot version number, so that you can easily distinguish boot logs of different boards from each other. config CBFS_PREFIX string "CBFS prefix to use" default "fallback" help Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. choice prompt "Compiler" default COMPILER_GCC help This option allows you to select the compiler used for building coreboot. config COMPILER_GCC bool "GCC" config COMPILER_LLVM_CLANG bool "LLVM/clang" endchoice config SCANBUILD_ENABLE bool "Build with scan-build for static analysis" default n help Changes the build process to scan-build is used. Requires scan-build in path. config SCANBUILD_REPORT_LOCATION string "Directory to put scan-build report in" default "" depends on SCANBUILD_ENABLE help Where the scan-build report should be stored config CCACHE bool "ccache" default n help Enables the use of ccache for faster builds. Requires ccache in path. config SCONFIG_GENPARSER bool "Generate SCONFIG parser using flex and bison" default n depends on EXPERT help Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l and sconfig.y. Otherwise, say N. config USE_OPTION_TABLE bool "Use CMOS for configuration values" default n depends on HAVE_OPTION_TABLE help Enable this option if coreboot shall read options from the "CMOS" NVRAM instead of using hard coded values. config COMPRESS_RAMSTAGE bool "Compress ramstage with LZMA" default y help Compress ramstage to save memory in the flash image. Note that decompression might slow down booting if the boot flash is connected through a slow Link (i.e. SPI) config INCLUDE_CONFIG_FILE bool "Include the coreboot config file into the ROM image" default y help Include in CBFS the coreboot config file that was used to compile the ROM image config EARLY_CBMEM_INIT bool "Initialize CBMEM while in ROM stage" default n help Make coreboot initialize the cbmem structures while running in rom stage. This could be useful when the rom stage wants to communicate some, for instance, execution timestamps. config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" depends on EARLY_CBMEM_INIT help Make coreboot create a table of timer id/timer value pairs to allow measuring time spent at different phases of the boot process. endmenu source src/mainboard/Kconfig # This option is used to set the architecture of a mainboard to X86. # It is usually set in mainboard/*/Kconfig. config ARCH_X86 bool default n if ARCH_X86 source src/arch/x86/Kconfig endif menu "Chipset" comment "CPU" source src/cpu/Kconfig comment "Northbridge" source src/northbridge/Kconfig comment "Southbridge" source src/southbridge/Kconfig comment "Super I/O" source src/superio/Kconfig comment "Devices" source src/devices/Kconfig comment "Embedded Controllers" source src/ec/Kconfig endmenu menu "Generic Drivers" source src/drivers/Kconfig endmenu config PCI_BUS_SEGN_BITS int default 0 config PCI_ROM_RUN bool default n config HEAP_SIZE hex default 0x4000 config MAX_CPUS int default 1 config MMCONF_SUPPORT_DEFAULT bool default n config MMCONF_SUPPORT bool default n source src/console/Kconfig # This should default to N and be set by SuperI/O drivers that have an UART config HAVE_UART_IO_MAPPED bool default y config HAVE_UART_MEMORY_MAPPED bool default n config HAVE_ACPI_RESUME bool default n config HAVE_ACPI_SLIC bool default n config ACPI_SSDTX_NUM int default 0 config HAVE_HARD_RESET bool default y if BOARD_HAS_HARD_RESET default n help This variable specifies whether a given board has a hard_reset function, no matter if it's provided by board code or chipset code. config HAVE_INIT_TIMER bool default n if UDELAY_IO default y config HAVE_MAINBOARD_RESOURCES bool default n config USE_OPTION_TABLE bool default n config HAVE_OPTION_TABLE bool default n help This variable specifies whether a given board has a cmos.layout file containing NVRAM/CMOS bit definitions. It defaults to 'n' but can be selected in mainboard/*/Kconfig. config PIRQ_ROUTE bool default n config HAVE_SMI_HANDLER bool default n config PCI_IO_CFG_EXT bool default n config IOAPIC bool default n config TPM bool default n # TODO: Can probably be removed once all chipsets have kconfig options for it. config VIDEO_MB int default 0 config USE_WATCHDOG_ON_BOOT bool default n config VGA bool default n help Build board-specific VGA code. config GFXUMA bool default n help Enable Unified Memory Architecture for graphics. # TODO # menu "Drivers" # # endmenu config HAVE_ACPI_TABLES bool help This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. Whether or not the ACPI tables are actually generated by coreboot is configurable by the user via GENERATE_ACPI_TABLES. config HAVE_MP_TABLE bool help This variable specifies whether a given board has MP table support. It is usually set in mainboard/*/Kconfig. Whether or not the MP table is actually generated by coreboot is configurable by the user via GENERATE_MP_TABLE. config HAVE_PIRQ_TABLE bool help This variable specifies whether a given board has PIRQ table support. It is usually set in mainboard/*/Kconfig. Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE. #These Options are here to avoid "undefined" warnings. #The actual selection and help texts are in the following menu. config GENERATE_ACPI_TABLES bool default HAVE_ACPI_TABLES config GENERATE_MP_TABLE bool default HAVE_MP_TABLE config GENERATE_PIRQ_TABLE bool default HAVE_PIRQ_TABLE config GENERATE_SMBIOS_TABLES bool default y menu "System tables" config WRITE_HIGH_TABLES bool "Write 'high' tables to avoid being overwritten in F segment" default y config MULTIBOOT bool "Generate Multiboot tables (for GRUB2)" default y config GENERATE_ACPI_TABLES depends on HAVE_ACPI_TABLES bool "Generate ACPI tables" default y help Generate ACPI tables for this board. If unsure, say Y. config GENERATE_MP_TABLE depends on HAVE_MP_TABLE bool "Generate an MP table" default y help Generate an MP table (conforming to the Intel MultiProcessor specification 1.4) for this board. If unsure, say Y. config GENERATE_PIRQ_TABLE depends on HAVE_PIRQ_TABLE bool "Generate a PIRQ table" default y help Generate a PIRQ table for this board. If unsure, say Y. config GENERATE_SMBIOS_TABLES depends on ARCH_X86 bool "Generate SMBIOS tables" default y help Generate SMBIOS tables for this board. If unsure, say Y. endmenu menu "Payload" choice prompt "Add a payload" default PAYLOAD_NONE if !ARCH_X86 default PAYLOAD_SEABIOS if ARCH_X86 config PAYLOAD_NONE bool "None" help Select this option if you want to create an "empty" coreboot ROM image for a certain mainboard, i.e. a coreboot ROM image which does not yet contain a payload. For such an image to be useful, you have to use 'cbfstool' to add a payload to the ROM image later. config PAYLOAD_ELF bool "An ELF executable payload" help Select this option if you have a payload image (an ELF file) which coreboot should run as soon as the basic hardware initialization is completed. You will be able to specify the location and file name of the payload image later. config PAYLOAD_SEABIOS bool "SeaBIOS" depends on ARCH_X86 help Select this option if you want to build a coreboot image with a SeaBIOS payload. If you don't know what this is about, just leave it enabled. See http://coreboot.org/Payloads for more information. config PAYLOAD_FILO bool "FILO" help Select this option if you want to build a coreboot image with a FILO payload. If you don't know what this is about, just leave it enabled. See http://coreboot.org/Payloads for more information. endchoice choice prompt "SeaBIOS version" default SEABIOS_STABLE depends on PAYLOAD_SEABIOS config SEABIOS_STABLE bool "stable" help Stable SeaBIOS version config SEABIOS_MASTER bool "master" help Newest SeaBIOS version endchoice choice prompt "FILO version" default FILO_STABLE depends on PAYLOAD_FILO config FILO_STABLE bool "0.6.0" help Stable FILO version config FILO_MASTER bool "HEAD" help Newest FILO version endchoice config PAYLOAD_FILE string "Payload path and filename" depends on PAYLOAD_ELF default "payload.elf" help The path and filename of the ELF executable file to use as payload. config PAYLOAD_FILE depends on PAYLOAD_SEABIOS default "$(obj)/seabios/out/bios.bin.elf" config PAYLOAD_FILE depends on PAYLOAD_FILO default "payloads/external/FILO/filo/build/filo.elf" # TODO: Defined if no payload? Breaks build? config COMPRESSED_PAYLOAD_LZMA bool "Use LZMA compression for payloads" default y depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO help In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm. config COMPRESSED_PAYLOAD_NRV2B bool default n endmenu menu "VGA BIOS" config VGA_BIOS bool "Add a VGA BIOS image" help Select this option if you have a VGA BIOS image that you would like to add to your ROM. You will be able to specify the location and file name of the image later. config VGA_BIOS_FILE string "VGA BIOS path and filename" depends on VGA_BIOS default "vgabios.bin" help The path and filename of the file to use as VGA BIOS. config VGA_BIOS_ID string "VGA device PCI IDs" depends on VGA_BIOS default "1106,3230" help The comma-separated PCI vendor and device ID that would associate your VGA BIOS to your video card. Example: 1106,3230 In the above example 1106 is the PCI vendor ID (in hex, but without the "0x" prefix) and 3230 specifies the PCI device ID of the video card (also in hex, without "0x" prefix). config INTEL_MBI bool "Add an MBI image" depends on NORTHBRIDGE_INTEL_I82830 help Select this option if you have an Intel MBI image that you would like to add to your ROM. You will be able to specify the location and file name of the image later. config MBI_FILE string "Intel MBI path and filename" depends on INTEL_MBI default "mbi.bin" help The path and filename of the file to use as VGA BIOS. endmenu menu "Display" depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE config FRAMEBUFFER_SET_VESA_MODE prompt "Set VESA framebuffer mode" bool depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE help Set VESA framebuffer mode (needed for bootsplash) # TODO: Turn this into a "choice". config FRAMEBUFFER_VESA_MODE prompt "VESA framebuffer video mode" hex default 0x117 depends on FRAMEBUFFER_SET_VESA_MODE help This option sets the resolution used for the coreboot framebuffer (and bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will some day make this a "choice". config FRAMEBUFFER_KEEP_VESA_MODE prompt "Keep VESA framebuffer" bool depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE help This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a framebuffer entry in its coreboot table and the payload will need a framebuffer driver. If this option is disabled, coreboot will switch back to text mode before handing control to a payload. config BOOTSPLASH prompt "Show graphical bootsplash" bool depends on FRAMEBUFFER_SET_VESA_MODE help This option shows a graphical bootsplash screen. The grapics are loaded from the CBFS file bootsplash.jpg. config BOOTSPLASH_FILE string "Bootsplash path and filename" depends on BOOTSPLASH default "bootsplash.jpg" help The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg. endmenu menu "Debugging" # TODO: Better help text and detailed instructions. config GDB_STUB bool "GDB debugging support" default n help If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/x86/lib/c_start.S for details. config HAVE_DEBUG_RAM_SETUP def_bool n config DEBUG_RAM_SETUP bool "Output verbose RAM init debug messages" default n depends on HAVE_DEBUG_RAM_SETUP help This option enables additional RAM init related debug messages. It is recommended to enable this when debugging issues on your board which might be RAM init related. Note: This option will increase the size of the coreboot image. If unsure, say N. config HAVE_DEBUG_CAR def_bool n config DEBUG_CAR def_bool n depends on HAVE_DEBUG_CAR if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional # printk(BIOS_DEBUG, ...) calls. config DEBUG_CAR bool "Output verbose Cache-as-RAM debug messages" default n depends on HAVE_DEBUG_CAR help This option enables additional CAR related debug messages. endif config DEBUG_PIRQ bool "Check PIRQ table consistency" default n depends on GENERATE_PIRQ_TABLE help If unsure, say N. config HAVE_DEBUG_SMBUS def_bool n config DEBUG_SMBUS bool "Output verbose SMBus debug messages" default n depends on HAVE_DEBUG_SMBUS help This option enables additional SMBus (and SPD) debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N. config DEBUG_SMI bool "Output verbose SMI debug messages" default n depends on HAVE_SMI_HANDLER help This option enables additional SMI related debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N. config DEBUG_SMM_RELOCATION bool "Debug SMM relocation code" default n depends on HAVE_SMI_HANDLER help This option enables additional SMM handler relocation related debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N. config DEBUG_MALLOC def_bool n # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional # printk(BIOS_DEBUG, ...) calls. if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 config DEBUG_MALLOC bool "Output verbose malloc debug messages" default n help This option enables additional malloc related debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N. endif config DEBUG_ACPI def_bool n # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional # printk(BIOS_DEBUG, ...) calls. if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 config DEBUG_ACPI bool "Output verbose ACPI debug messages" default n help This option enables additional ACPI related debug messages. Note: This option will slightly increase the size of the coreboot image. If unsure, say N. endif config REALMODE_DEBUG def_bool n depends on PCI_OPTION_ROM_RUN_REALMODE if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional # printk(BIOS_DEBUG, ...) calls. config REALMODE_DEBUG bool "Enable debug messages for option ROM execution" default n depends on PCI_OPTION_ROM_RUN_REALMODE help This option enables additional x86emu related debug messages. Note: This option will increase the time to emulate a ROM. If unsure, say N. endif config X86EMU_DEBUG bool "Output verbose x86emu debug messages" default n depends on PCI_OPTION_ROM_RUN_YABEL help This option enables additional x86emu related debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N. config X86EMU_DEBUG_JMP bool "Trace JMP/RETF" default n depends on X86EMU_DEBUG help Print information about JMP and RETF opcodes from x86emu. Note: This option will increase the size of the coreboot image. If unsure, say N. config X86EMU_DEBUG_TRACE bool "Trace all opcodes" default n depends on X86EMU_DEBUG help Print _all_ opcodes that are executed by x86emu. WARNING: This will produce a LOT of output and take a long time. Note: This option will increase the size of the coreboot image. If unsure, say N. config X86EMU_DEBUG_PNP bool "Log Plug&Play accesses" default n depends on X86EMU_DEBUG help Print Plug And Play accesses made by option ROMs. Note: This option will increase the size of the coreboot image. If unsure, say N. config X86EMU_DEBUG_DISK bool "Log Disk I/O" default n depends on X86EMU_DEBUG help Print Disk I/O related messages. Note: This option will increase the size of the coreboot image. If unsure, say N. config X86EMU_DEBUG_PMM bool "Log PMM" default n depends on X86EMU_DEBUG help Print messages related to POST Memory Manager (PMM). Note: This option will increase the size of the coreboot image. If unsure, say N. config X86EMU_DEBUG_VBE bool "Debug VESA BIOS Extensions" default n depends on X86EMU_DEBUG help Print messages related to VESA BIOS Extension (VBE) functions. Note: This option will increase the size of the coreboot image. If unsure, say N. config X86EMU_DEBUG_INT10 bool "Redirect INT10 output to console" default n depends on X86EMU_DEBUG help Let INT10 (i.e. character output) calls print messages to debug output. Note: This option will increase the size of the coreboot image. If unsure, say N. config X86EMU_DEBUG_INTERRUPTS bool "Log intXX calls" default n depends on X86EMU_DEBUG help Print messages related to interrupt handling. Note: This option will increase the size of the coreboot image. If unsure, say N. config X86EMU_DEBUG_CHECK_VMEM_ACCESS bool "Log special memory accesses" default n depends on X86EMU_DEBUG help Print messages related to accesses to certain areas of the virtual memory (e.g. BDA (BIOS Data Area) or interrupt vectors) Note: This option will increase the size of the coreboot image. If unsure, say N. config X86EMU_DEBUG_MEM bool "Log all memory accesses" default n depends on X86EMU_DEBUG help Print memory accesses made by option ROM. Note: This also includes accesses to fetch instructions. Note: This option will increase the size of the coreboot image. If unsure, say N. config X86EMU_DEBUG_IO bool "Log IO accesses" default n depends on X86EMU_DEBUG help Print I/O accesses made by option ROM. Note: This option will increase the size of the coreboot image. If unsure, say N. config DEBUG_TPM bool "Output verbose TPM debug messages" default n depends on TPM help This option enables additional TPM related debug messages. if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8 # Only visible with the right southbridge and loglevel. config DEBUG_INTEL_ME bool "Verbose logging for Intel Management Engine" default n help Enable verbose logging for Intel Management Engine driver that is present on Intel 6-series chipsets. endif config LLSHELL bool "Built-in low-level shell" default n help If enabled, you will have a low level shell to examine your machine. Put llshell() in your (romstage) code to start the shell. See src/arch/x86/llshell/llshell.inc for details. config TRACE bool "Trace function calls" default n help If enabled, every function will print information to console once the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd) the 0xaaaabbbb is the actual function and 0xccccdddd is EIP of calling function. Please note some printk releated functions are omitted from trace to have good looking console dumps. endmenu config LIFT_BSP_APIC_ID bool default n # These probably belong somewhere else, but they are needed somewhere. config AP_CODE_IN_CAR bool default n config RAMINIT_SYSINFO bool default n config ENABLE_APIC_EXT_ID bool default n config WARNINGS_ARE_ERRORS bool default y # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are # mutually exclusive. One of these options must be selected in the # mainboard Kconfig if the chipset supports enabling and disabling of # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set # in mainboard/Kconfig to know if the button should be enabled or not. config POWER_BUTTON_DEFAULT_ENABLE def_bool n help Select when the board has a power button which can optionally be disabled by the user. config POWER_BUTTON_DEFAULT_DISABLE def_bool n help Select when the board has a power button which can optionally be enabled by the user, e.g. when the board ships with a jumper over the power switch contacts. config POWER_BUTTON_FORCE_ENABLE def_bool n help Select when the board requires that the power button is always enabled. config POWER_BUTTON_FORCE_DISABLE def_bool n help Select when the board requires that the power button is always disabled, e.g. when it has been hardwired to ground. config POWER_BUTTON_IS_OPTIONAL bool default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE) help Internal option that controls ENABLE_POWER_BUTTON visibility. source src/Kconfig.deprecated_options source src/vendorcode/Kconfig