X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=cbimages.git;a=blobdiff_plain;f=2012-04-06_14%3A14.log;fp=2012-04-06_14%3A14.log;h=c6e9cb3edee47564a9d8981abb0db5c575224a8e;hp=0000000000000000000000000000000000000000;hb=08a7bbf033494ca4b6fd1361f7f7ad63827f47f4;hpb=43694cb43cd670fc51e07700e05f53c9342878eb diff --git a/2012-04-06_14:14.log b/2012-04-06_14:14.log new file mode 100644 index 0000000..c6e9cb3 --- /dev/null +++ b/2012-04-06_14:14.log @@ -0,0 +1,3120 @@ + + +coreboot-4.0-2271-g0d4a5be-dirty Fri Apr 6 14:13:20 CEST 2012 starting... + +BSP Family_Model: 00100fa0 +*sysinfo range: [000cc000,000cf360] +bsp_apicid = 00 +cpu_init_detectedx = 00000000 +microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000 +microcode: patch id to apply = 0x010000bf +microcode: updated to patch id = 0x010000bf success + +POST: 0x33 +cpuSetAMDMSR done +POST: 0x34 +Enter amd_ht_init() +Exit amd_ht_init() +POST: 0x35 +SB900 - Early.c - get_sbdn - Start. +SB900 - Early.c - get_sbdn - End. +cpuSetAMDPCI 00 done +Prep FID/VID Node:00 +P-state info in MSRC001_0064 is invalid !!! +P-state info in MSRc0010064 is invalid !!! + F3x80: e600e681 + F3x84: 80e641e6 + F3xD4: c3310f26 + F3xD8: 03001016 + F3xDC: 0000611a +POST: 0x36 +core0 started: +start_other_cores() +init node: 00 cores: 05 +Start other core - nodeid: 00 cores: 05 +POST: 0x37 +started ap apicid: PPPPPOOOSSOOTSSSTTT::T ::: 000xx00xxx3333300000 + + + + +* mmmiiimmAciiPcc rrrccoorr0oo1cccocooocddoodddeee:::ee :: eee qeeqqquuuqiiuuiiivvvaavvaaallleeellneennntttn tt rrr eerreeevvv vv iiidddii dd = === =00 000xxx111xx11000aaa000aa000,,,0 ,, cccuuccuuurrrrrrrrerreennneetnnttt tpp ppaaapttaatttccchhhcchh iii diiddd d== == = 0000xxx00xx00000000000000000000000000000000000000 0 + + + + +startemdimmmmi ciiicccc +rrorrroooocccoccdooooddedd:eeee::: : p ppppaaataattttccchcc hhhh i diiiid dddt ttott oooo a apaaapppppplpppllllyyy yy= === =0 000x0x0xxx000011011100000000000000000b00fbbbbfff f + + + + +mmmmm*ii iiicccccArrPrrr oooooccc0cc2ooooodddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss + + + + + + + + + +scctcccpppappruuuuuSSStSSeeeeeettttdtA AAAAMMMMM +DDDDDMMMMMSSSSSRRRRR * AP 0dddddoo3ooonnnnneeeee + + + + +siiiiinntnnnaiiiiitttrttt_____ffffefidiiiidddd dvv +vvviiiiiddddd_____aaaaappppp(((((ssssstttttaaaaagggggeeeee11111))))) aaaaapppppiiiiiccccciiiiiddddd::::: 0000054123 + + + + +FFFFF*II IIIDDDDDAVVVPVV IIIIIDDD0DD 4 ooooonnnnn AAAAAPPPPP::::: 0000023541 + + + + +started +* AP 05started + +POST: 0x38 +cimx/rd890 early.c nb_Poweron_Init() Start +cimx/rd890 early.c nb_Poweron_Init() End. return status=0 + +Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 +POST: 0x39 +FIDVID on BSP, APIC_id: 00 +BSP fid = 0 +Wait for AP stage 1: ap_apicid = 1 + readback = 1000001 + common_fid(packed) = 0 +Wait for AP stage 1: ap_apicid = 2 + readback = 2000001 + common_fid(packed) = 0 +Wait for AP stage 1: ap_apicid = 3 + readback = 3000001 + common_fid(packed) = 0 +Wait for AP stage 1: ap_apicid = 4 + readback = 4000001 + common_fid(packed) = 0 +Wait for AP stage 1: ap_apicid = 5 + readback = 5000001 + common_fid(packed) = 0 +common_fid = 0 +POST: 0x3a +End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 +AmdHtInit status: 0 +...WARM RESET... + + + + +coreboot-4.0-2271-g0d4a5be-dirty Fri Apr 6 14:13:20 CEST 2012 starting... + +BSP Family_Model: 00100fa0 +*sysinfo range: [000cc000,000cf360] +bsp_apicid = 00 +cpu_init_detectedx = 00000000 +microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000 +microcode: patch id to apply = 0x010000bf +microcode: updated to patch id = 0x010000bf success + +POST: 0x33 +cpuSetAMDMSR done +POST: 0x34 +Enter amd_ht_init() +Exit amd_ht_init() +POST: 0x35 +SB900 - Early.c - get_sbdn - Start. +SB900 - Early.c - get_sbdn - End. +cpuSetAMDPCI 00 done +Prep FID/VID Node:00 +P-state info in MSRC001_0064 is invalid !!! +P-state info in MSRc0010064 is invalid !!! + F3x80: e600e681 + F3x84: 80e641e6 + F3xD4: c3310f26 + F3xD8: 03001016 + F3xDC: 0000611a +POST: 0x36 +core0 started: +start_other_cores() +init node: 00 cores: 05 +Start other core - nodeid: 00 cores: 05 +POST: 0x37 +started ap apicid: PPPPPOSOOOOSSSTST:TTT::: : 0 x0000xxxx3333300000 + + + + +* mAmmmimiPiiicccrc cor0rrroooco1occccdoooodddedeee:e:: :: e eqeeeuqqqquuuuiiiiivvvvavaaalalellleneeetnnnn tttt r rrrereeveevv vv i idiiidddd = == == 0 0x0001xxxx011110000aaaa0a000,0,, ,, c uccccruuuurrrrrrrrereeenenntnntt ttp appppaaaattttctccchchh hh i idiii dddd= === = 0 00x00xx0xx00000000000000000000000000000000000 0000 + + + + +startemmiimmmdii ccirrccc +rrrooooccoccoocoddooeeddd::eee ::: pppppaaaattattccthhccc hhhi idiiidd dd tt ttoot oooaa paaapppppppppllllyyly yy == ===0 0x000xxxx000011011001000000000000000b000bfbbbfff f + + + + +mmmmm*i iiiiccccAcrPrrrroooo occ0cccooooo2dddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss + + + + + + + + + +scctcccppppapuruuuuSSSStSeeeeeetttttdAA AAAMMMMM +DDDDDMMMMMSSSSSRRRRR * AP dd d0oodd3nnoooennneeee + + + + +siiitniiinnnnaiirtiit_tttt___ef_diffffiiii dd +vdddvvvviiiiidddd_d__s__sstsstatttgaaaaeggggeeee22222 a aapaappippciiiiicccciiiiddddd:::: : 0 005001 423 + + + + +* AP 04started +* AP 05started + +POST: 0x38 +cimx/rd890 early.c nb_Poweron_Init() Start +cimx/rd890 early.c nb_Poweron_Init() End. return status=0 + +Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 +POST: 0x39 +POST: 0x3a +End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 +AmdHtInit status: 0 +POST: 0x3b +fill_mem_ctrl() +POST: 0x40 +raminit_amdmct() +raminit_amdmct begin: +SB900 - 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Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SPDGetTCL_D: DIMMCASL 4 +SPDGetTCL_D: DIMMAutoSpeed 4 +SPDGetTCL_D: Status 1000 +SPDGetTCL_D: ErrStatus 0 +SPDGetTCL_D: ErrCode 0 +SPDGetTCL_D: Done + +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +AutoCycTiming: Status 1000 +AutoCycTiming: ErrStatus 0 +AutoCycTiming: ErrCode 0 +AutoCycTiming: Done + + DCTInit_D: AutoCycTiming_D Done +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SPDSetBanks: CSPresent c +SPDSetBanks: Status 1000 +SPDSetBanks: ErrStatus 0 +SPDSetBanks: ErrCode 0 +SPDSetBanks: Done + +AfterStitch pDCTstat->NodeSysBase = 0 +mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff +StitchMemory: Status 1000 +StitchMemory: ErrStatus 0 +StitchMemory: ErrCode 0 +StitchMemory: Done + +InterleaveBanks_D: Status 1000 +InterleaveBanks_D: ErrStatus 0 +InterleaveBanks_D: ErrCode 0 +InterleaveBanks_D: Done + +AutoConfig_D: DramControl: 2a06 +AutoConfig_D: DramTimingLo: 90092 +AutoConfig_D: DramConfigMisc: 0 +AutoConfig_D: DramConfigMisc2: 0 +AutoConfig_D: DramConfigLo: 10000 +AutoConfig_D: DramConfigHi: f40000b +AutoConfig: Status 1000 +AutoConfig: ErrStatus 0 +AutoConfig: ErrCode 0 +AutoConfig: Done + + DCTInit_D: AutoConfig_D Done + DCTInit_D: PlatformSpec_D Done + DCTInit_D: StartupDCT_D + DCTInit_D: mct_DIMMPresence Done +SPDCalcWidth: Status 1000 +SPDCalcWidth: ErrStatus 0 +SPDCalcWidth: ErrCode 0 +SPDCalcWidth: Done + DCTInit_D: mct_SPDCalcWidth Done +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +AutoCycTiming: Status 1000 +AutoCycTiming: ErrStatus 0 +AutoCycTiming: ErrCode 0 +AutoCycTiming: Done + + DCTInit_D: AutoCycTiming_D Done +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SPDSetBanks: CSPresent c +SPDSetBanks: Status 1000 +SPDSetBanks: ErrStatus 0 +SPDSetBanks: ErrCode 0 +SPDSetBanks: Done + +AfterStitch pDCTstat->NodeSysBase = 0 +mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe +StitchMemory: Status 1000 +StitchMemory: ErrStatus 0 +StitchMemory: ErrCode 0 +StitchMemory: Done + +InterleaveBanks_D: Status 1000 +InterleaveBanks_D: ErrStatus 0 +InterleaveBanks_D: ErrCode 0 +InterleaveBanks_D: Done + +AutoConfig_D: DramControl: 2a06 +AutoConfig_D: DramTimingLo: 90092 +AutoConfig_D: DramConfigMisc: 0 +AutoConfig_D: DramConfigMisc2: 0 +AutoConfig_D: DramConfigLo: 10000 +AutoConfig_D: DramConfigHi: f40000b +AutoConfig: Status 1000 +AutoConfig: ErrStatus 0 +AutoConfig: ErrCode 0 +AutoConfig: Done + + DCTInit_D: AutoConfig_D Done + DCTInit_D: PlatformSpec_D Done + DCTInit_D: StartupDCT_D +mctAutoInitMCT_D: SyncDCTsReady_D +mctAutoInitMCT_D: HTMemMapInit_D + Node: 00 base: 00 limit: 1ffffff BottomIO: e00000 + Node: 00 base: 03 limit: 21fffff + Node: 01 base: 00 limit: 00 + Node: 02 base: 00 limit: 00 + Node: 03 base: 00 limit: 00 + Node: 04 base: 00 limit: 00 + Node: 05 base: 00 limit: 00 + Node: 06 base: 00 limit: 00 + Node: 07 base: 00 limit: 00 +mctAutoInitMCT_D: CPUMemTyping_D + CPUMemTyping: Cache32bTOP:e00000 + CPUMemTyping: Bottom32bIO:e00000 + CPUMemTyping: Bottom40bIO:2200000 +mctAutoInitMCT_D: DQSTiming_D +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +SB900 - Smbus.c - do_smbus_read_byte - Start. +SB900 - Smbus.c - do_smbus_read_byte - End. +TrainRcvrEn: Status 1100 +TrainRcvrEn: ErrStatus 0 +TrainRcvrEn: ErrCode 0 +TrainRcvrEn: Done + +TrainDQSRdWrPos: Status 1100 +TrainDQSRdWrPos: TrainErrors 0 +TrainDQSRdWrPos: ErrStatus 0 +TrainDQSRdWrPos: ErrCode 0 +TrainDQSRdWrPos: Done + +TrainDQSRdWrPos: Status 1100 +TrainDQSRdWrPos: TrainErrors 0 +TrainDQSRdWrPos: ErrStatus 0 +TrainDQSRdWrPos: ErrCode 0 +TrainDQSRdWrPos: Done + +TrainDQSRdWrPos: Status 1100 +TrainDQSRdWrPos: TrainErrors 0 +TrainDQSRdWrPos: ErrStatus 0 +TrainDQSRdWrPos: ErrCode 0 +TrainDQSRdWrPos: Done + +TrainDQSRdWrPos: Status 1100 +TrainDQSRdWrPos: TrainErrors 0 +TrainDQSRdWrPos: ErrStatus 0 +TrainDQSRdWrPos: ErrCode 0 +TrainDQSRdWrPos: Done + +mctAutoInitMCT_D: UMAMemTyping_D +mctAutoInitMCT_D: :OtherTiming +InterleaveNodes_D: Status 1100 +InterleaveNodes_D: ErrStatus 0 +InterleaveNodes_D: ErrCode 0 +InterleaveNodes_D: Done + +InterleaveChannels_D: Node 0 +InterleaveChannels_D: Status 1100 +InterleaveChannels_D: ErrStatus 0 +InterleaveChannels_D: ErrCode 0 +InterleaveChannels_D: Node 1 +InterleaveChannels_D: Status 1000 +InterleaveChannels_D: ErrStatus 0 +InterleaveChannels_D: ErrCode 0 +InterleaveChannels_D: Node 2 +InterleaveChannels_D: Status 1000 +InterleaveChannels_D: ErrStatus 0 +InterleaveChannels_D: ErrCode 0 +InterleaveChannels_D: Node 3 +InterleaveChannels_D: Status 1000 +InterleaveChannels_D: ErrStatus 0 +InterleaveChannels_D: ErrCode 0 +InterleaveChannels_D: Node 4 +InterleaveChannels_D: Status 1000 +InterleaveChannels_D: ErrStatus 0 +InterleaveChannels_D: ErrCode 0 +InterleaveChannels_D: Node 5 +InterleaveChannels_D: Status 1000 +InterleaveChannels_D: ErrStatus 0 +InterleaveChannels_D: ErrCode 0 +InterleaveChannels_D: Node 6 +InterleaveChannels_D: Status 1000 +InterleaveChannels_D: ErrStatus 0 +InterleaveChannels_D: ErrCode 0 +InterleaveChannels_D: Node 7 +InterleaveChannels_D: Status 1000 +InterleaveChannels_D: ErrStatus 0 +InterleaveChannels_D: ErrCode 0 +InterleaveChannels_D: Done + +mctAutoInitMCT_D: ECCInit_D +ECCInit: Node 00 +ECCInit: Status 1100 +ECCInit: ErrStatus 0 +ECCInit: ErrCode 0 +ECCInit: Done +mctAutoInitMCT_D Done: Global Status: 10 +raminit_amdmct end: +POST: 0x41 +POST: 0x42 +v_esp=000cbef8 +testx = 5a5a5a5a +Copying data from cache to RAM -- switching to use RAM as stack... Done +testx = 5a5a5a5a +Disabling cache as ram now +Clearing initial memory region: Done +Loading image. +Searching for fallback/coreboot_ram +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Stage: loading fallback/coreboot_ram @ 0x200000 (1310720 bytes), entry @ 0x200000 +Stage: done loading. +Jumping to image. +POST: 0x80 +POST: 0x39 +coreboot-4.0-2271-g0d4a5be-dirty Fri Apr 6 14:13:20 CEST 2012 booting... +POST: 0x40 +Enumerating buses... +Show all devs...Before device enumeration. +Root Device: enabled 1 +APIC_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +PCI_DOMAIN: 0000: enabled 1 +PCI: 00:18.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:00.1: enabled 0 +PCI: 00:02.0: enabled 1 +PCI: 00:03.0: enabled 0 +PCI: 00:04.0: enabled 0 +PCI: 00:05.0: enabled 0 +PCI: 00:06.0: enabled 0 +PCI: 00:07.0: enabled 0 +PCI: 00:08.0: enabled 0 +PCI: 00:09.0: enabled 0 +PCI: 00:0a.0: enabled 0 +PCI: 00:0b.0: enabled 0 +PCI: 00:0c.0: enabled 0 +PCI: 00:0d.0: enabled 1 +PCI: 00:11.0: enabled 1 +PCI: 00:12.0: enabled 1 +PCI: 00:12.2: enabled 1 +PCI: 00:13.0: enabled 1 +PCI: 00:13.2: enabled 1 +PCI: 00:14.0: enabled 1 +I2C: 00:50: enabled 1 +I2C: 00:51: enabled 1 +I2C: 00:52: enabled 1 +I2C: 00:53: enabled 1 +PCI: 00:14.1: enabled 1 +PCI: 00:14.2: enabled 1 +PCI: 00:14.3: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 0 +PNP: 002e.2: enabled 1 +PNP: 002e.3: enabled 1 +PNP: 002e.5: enabled 1 +PNP: 002e.6: enabled 0 +PNP: 002e.7: enabled 0 +PNP: 002e.8: enabled 0 +PNP: 002e.9: enabled 0 +PNP: 002e.a: enabled 0 +PNP: 002e.b: enabled 1 +PCI: 00:14.4: enabled 0 +PCI: 00:14.5: enabled 1 +PCI: 00:14.6: enabled 0 +PCI: 00:15.0: enabled 1 +PCI: 00:15.1: enabled 1 +PCI: 00:15.2: enabled 1 +PCI: 00:15.3: enabled 1 +PCI: 00:16.0: enabled 1 +PCI: 00:16.2: enabled 1 +PCI: 00:18.1: enabled 1 +PCI: 00:18.2: enabled 1 +PCI: 00:18.3: enabled 1 +PCI: 00:18.4: enabled 1 +Compare with tree... +Root Device: enabled 1 + APIC_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + PCI_DOMAIN: 0000: enabled 1 + PCI: 00:18.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:00.1: enabled 0 + PCI: 00:02.0: enabled 1 + PCI: 00:03.0: enabled 0 + PCI: 00:04.0: enabled 0 + PCI: 00:05.0: enabled 0 + PCI: 00:06.0: enabled 0 + PCI: 00:07.0: enabled 0 + PCI: 00:08.0: enabled 0 + PCI: 00:09.0: enabled 0 + PCI: 00:0a.0: enabled 0 + PCI: 00:0b.0: enabled 0 + PCI: 00:0c.0: enabled 0 + PCI: 00:0d.0: enabled 1 + PCI: 00:11.0: enabled 1 + PCI: 00:12.0: enabled 1 + PCI: 00:12.2: enabled 1 + PCI: 00:13.0: enabled 1 + PCI: 00:13.2: enabled 1 + PCI: 00:14.0: enabled 1 + I2C: 00:50: enabled 1 + I2C: 00:51: enabled 1 + I2C: 00:52: enabled 1 + I2C: 00:53: enabled 1 + PCI: 00:14.1: enabled 1 + PCI: 00:14.2: enabled 1 + PCI: 00:14.3: enabled 1 + PNP: 002e.0: enabled 0 + PNP: 002e.1: enabled 0 + PNP: 002e.2: enabled 1 + PNP: 002e.3: enabled 1 + PNP: 002e.5: enabled 1 + PNP: 002e.6: enabled 0 + PNP: 002e.7: enabled 0 + PNP: 002e.8: enabled 0 + PNP: 002e.9: enabled 0 + PNP: 002e.a: enabled 0 + PNP: 002e.b: enabled 1 + PCI: 00:14.4: enabled 0 + PCI: 00:14.5: enabled 1 + PCI: 00:14.6: enabled 0 + PCI: 00:15.0: enabled 1 + PCI: 00:15.1: enabled 1 + PCI: 00:15.2: enabled 1 + PCI: 00:15.3: enabled 1 + PCI: 00:16.0: enabled 1 + PCI: 00:16.2: enabled 1 + PCI: 00:18.1: enabled 1 + PCI: 00:18.2: enabled 1 + PCI: 00:18.3: enabled 1 + PCI: 00:18.4: enabled 1 +Mainboard ASUS M5A99X-EVO Enable. dev=0x0023a964 +m5a99x_evo_enable, TOP MEM: msr.lo = 0xe0000000, msr.hi = 0x00000000 +m5a99x_evo_enable, TOP MEM2: msr2.lo = 0x20000000, msr2.hi = 0x00000002 +scan_static_bus for Root Device +APIC_CLUSTER: 0 enabled +PCI_DOMAIN: 0000 enabled +APIC_CLUSTER: 0 scanning... + PCI: 00:18.3 siblings=5 +CPU: APIC: 00 enabled +CPU: APIC: 01 enabled +CPU: APIC: 02 enabled +CPU: APIC: 03 enabled +CPU: APIC: 04 enabled +CPU: APIC: 05 enabled +PCI_DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +POST: 0x24 +PCI: 00:18.0 [1022/1200] bus ops +PCI: 00:18.0 [1022/1200] enabled +PCI: 00:18.1 [1022/1201] enabled +PCI: 00:18.2 [1022/1202] enabled +PCI: 00:18.3 [1022/1203] ops +PCI: 00:18.3 [1022/1203] enabled +PCI: 00:18.4 [1022/1204] enabled +POST: 0x25 +PCI: 00:00.0 [1002/5a14] ops +PCI: 00:00.0 [1002/5a14] enabled +Capability: type 0x08 @ 0xf0 +flags: 0xa803 +Capability: type 0x08 @ 0xf0 +Capability: type 0x08 @ 0xc4 +flags: 0x0281 +PCI: pci_scan_bus for bus 00 +PCI: pci_scan_bus limits devfn 0 - devfn ffffffff +PCI: pci_scan_bus upper limit too big. Using 0xff. +POST: 0x24 +PCI: 00:00.0 [1002/5a14] enabled +PCI: 00:11.0 [1002/4393] enabled +PCI: 00:12.0 [1002/4397] enabled +PCI: 00:12.2 [1002/4396] enabled +PCI: 00:13.0 [1002/4397] enabled +PCI: 00:13.2 [1002/4396] enabled +PCI: 00:14.0 [1002/4385] enabled +PCI: 00:14.1 [1002/439c] enabled +PCI: 00:14.2 [1002/4383] enabled +PCI: 00:14.3 [1002/439d] enabled +PCI: 00:14.4 [1002/4384] enabled +PCI: 00:14.5 [1002/4399] enabled +PCI: 00:16.0 [1002/4397] enabled +PCI: 00:16.2 [1002/4396] enabled +PCI: 00:18.0 [1022/1200] bus ops +PCI: 00:18.0 [1022/1200] enabled +PCI: 00:18.1 [1022/1201] enabled +PCI: 00:18.2 [1022/1202] enabled +PCI: 00:18.3 [1022/1203] ops +PCI: 00:18.3 [1022/1203] enabled +PCI: 00:18.4 [1022/1204] enabled +POST: 0x25 +do_pci_scan_bridge for PCI: 00:14.4 +PCI: pci_scan_bus for bus 01 +POST: 0x24 +POST: 0x25 +PCI: pci_scan_bus returning with max=001 +POST: 0x55 +do_pci_scan_bridge returns max 1 +PCI: pci_scan_bus returning with max=001 +POST: 0x55 +PCI: pci_scan_bus returning with max=001 +POST: 0x55 +PCI_DOMAIN: 0000 passpw: enabled +scan_static_bus for Root Device done +done +POST: 0x66 +===============Enumeration done!======== +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +APIC_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +APIC: 01 missing read_resources +APIC: 02 missing read_resources +APIC: 03 missing read_resources +APIC: 04 missing read_resources +APIC: 05 missing read_resources +APIC_CLUSTER: 0 read_resources bus 0 link: 0 done +PCI_DOMAIN: 0000 read_resources bus 0 link: 0 +PCI: 00:18.0 read_resources bus 0 link: 0 +PCI: 00:14.4 read_resources bus 1 link: 0 +PCI: 00:14.4 read_resources bus 1 link: 0 done +PCI: 00:18.0 read_resources bus 0 link: 0 done +PCI: 00:18.0 read_resources bus 0 link: 1 +PCI: 00:00.0 missing read_resources +PCI: 00:02.0 missing read_resources +PCI: 00:0d.0 missing read_resources +PCI: 00:11.0 missing read_resources +PCI: 00:12.0 missing read_resources +PCI: 00:12.2 missing read_resources +PCI: 00:13.0 missing read_resources +PCI: 00:13.2 missing read_resources +PCI: 00:14.0 missing read_resources +PCI: 00:14.1 missing read_resources +PCI: 00:14.2 missing read_resources +PCI: 00:14.3 missing read_resources +PCI: 00:14.5 missing read_resources +PCI: 00:15.0 missing read_resources +PCI: 00:15.1 missing read_resources +PCI: 00:15.2 missing read_resources +PCI: 00:15.3 missing read_resources +PCI: 00:16.0 missing read_resources +PCI: 00:16.2 missing read_resources +PCI: 00:18.0 read_resources bus 0 link: 1 done +PCI: 00:18.0 read_resources bus 0 link: 2 +PCI: 00:18.0 read_resources bus 0 link: 2 done +PCI: 00:18.0 read_resources bus 0 link: 3 +PCI: 00:18.0 read_resources bus 0 link: 3 done +PCI: 00:18.0 read_resources bus 0 link: 4 +PCI: 00:18.0 read_resources bus 0 link: 4 done +PCI: 00:18.0 read_resources bus 0 link: 5 +PCI: 00:18.0 read_resources bus 0 link: 5 done +PCI: 00:18.0 read_resources bus 0 link: 6 +PCI: 00:18.0 read_resources bus 0 link: 6 done +PCI: 00:18.0 read_resources bus 0 link: 7 +PCI: 00:18.0 read_resources bus 0 link: 7 done +PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 APIC_CLUSTER: 0 + APIC_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: 01 + APIC: 02 + APIC: 03 + APIC: 04 + APIC: 05 + PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 + PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 + PCI: 00:18.0 child on link 0 PCI: 00:00.0 + PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8 + PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b8 + PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b0 + PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d0 + PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110a8 + PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110a0 + PCI: 00:00.0 + PCI: 00:00.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 1200 index fc + PCI: 00:11.0 + PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 + PCI: 00:12.0 + PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 00:12.2 + PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:13.0 + PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 00:13.2 + PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:14.0 + PCI: 00:14.1 + PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:14.2 + PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:14.3 + PCI: 00:14.4 + PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 + PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:14.5 + PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 00:16.0 + PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 00:16.2 + PCI: 00:16.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:18.0 + PCI: 00:18.1 + PCI: 00:18.2 + PCI: 00:18.3 + PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 + PCI: 00:18.4 + PCI: 00:00.0 + PCI: 00:00.1 + PCI: 00:02.0 + PCI: 00:03.0 + PCI: 00:04.0 + PCI: 00:05.0 + PCI: 00:06.0 + PCI: 00:07.0 + PCI: 00:08.0 + PCI: 00:09.0 + PCI: 00:0a.0 + PCI: 00:0b.0 + PCI: 00:0c.0 + PCI: 00:0d.0 + PCI: 00:11.0 + PCI: 00:12.0 + PCI: 00:12.2 + PCI: 00:13.0 + PCI: 00:13.2 + PCI: 00:14.0 child on link 0 I2C: 00:50 + I2C: 00:50 + I2C: 00:51 + I2C: 00:52 + I2C: 00:53 + PCI: 00:14.1 + PCI: 00:14.2 + PCI: 00:14.3 child on link 0 PNP: 002e.0 + PNP: 002e.0 + PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 + PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.3 + PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.5 + PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 72 + PNP: 002e.6 + PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 002e.7 + PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.8 + PNP: 002e.9 + PNP: 002e.a + PNP: 002e.b + PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PCI: 00:14.4 + PCI: 00:14.5 + PCI: 00:14.6 + PCI: 00:15.0 + PCI: 00:15.1 + PCI: 00:15.2 + PCI: 00:15.3 + PCI: 00:16.0 + PCI: 00:16.2 + PCI: 00:18.1 + PCI: 00:18.2 + PCI: 00:18.3 + PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 + PCI: 00:18.4 +PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:11.0 20 * [0x0 - 0xf] io +PCI: 00:14.1 20 * [0x10 - 0x1f] io +PCI: 00:11.0 10 * [0x20 - 0x27] io +PCI: 00:11.0 18 * [0x28 - 0x2f] io +PCI: 00:14.1 10 * [0x30 - 0x37] io +PCI: 00:14.1 18 * [0x38 - 0x3f] io +PCI: 00:11.0 14 * [0x40 - 0x43] io +PCI: 00:11.0 1c * [0x44 - 0x47] io +PCI: 00:14.1 14 * [0x48 - 0x4b] io +PCI: 00:14.1 1c * [0x4c - 0x4f] io +PCI: 00:18.0 compute_resources_io: base: 50 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:18.0 10d8 * [0x0 - 0xfff] io +PCI_DOMAIN: 0000 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 0 limit: ffff done +PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff +PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:00.0 fc * [0x0 - 0xff] prefmem +PCI: 00:18.0 compute_resources_prefmem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff +PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem +PCI: 00:14.2 10 * [0x4000000 - 0x4003fff] mem +PCI: 00:12.0 10 * [0x4004000 - 0x4004fff] mem +PCI: 00:13.0 10 * [0x4005000 - 0x4005fff] mem +PCI: 00:14.5 10 * [0x4006000 - 0x4006fff] mem +PCI: 00:16.0 10 * [0x4007000 - 0x4007fff] mem +PCI: 00:11.0 24 * [0x4008000 - 0x40083ff] mem +PCI: 00:12.2 10 * [0x4008400 - 0x40084ff] mem +PCI: 00:13.2 10 * [0x4008500 - 0x40085ff] mem +PCI: 00:16.2 10 * [0x4008600 - 0x40086ff] mem +PCI: 00:18.0 compute_resources_mem: base: 4008700 size: 4100000 align: 26 gran: 20 limit: ffffffff done +PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff +PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done +PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff +PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done +PCI: 00:18.0 10b0 * [0x0 - 0x40fffff] mem +PCI: 00:18.3 94 * [0x8000000 - 0xbffffff] mem +PCI: 00:18.0 10b8 * [0xc000000 - 0xc0fffff] prefmem +PCI_DOMAIN: 0000 compute_resources_mem: base: c100000 size: c100000 align: 26 gran: 0 limit: ffffffff done +avoid_fixed_resources: PCI_DOMAIN: 0000 +avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: PCI_DOMAIN: 0000 +constrain_resources: PCI: 00:18.0 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:11.0 +constrain_resources: PCI: 00:12.0 +constrain_resources: PCI: 00:12.2 +constrain_resources: PCI: 00:13.0 +constrain_resources: PCI: 00:13.2 +constrain_resources: PCI: 00:14.0 +constrain_resources: PCI: 00:14.1 +constrain_resources: PCI: 00:14.2 +constrain_resources: PCI: 00:14.3 +constrain_resources: PCI: 00:14.4 +constrain_resources: PCI: 00:14.5 +constrain_resources: PCI: 00:16.0 +constrain_resources: PCI: 00:16.2 +constrain_resources: PCI: 00:18.0 +constrain_resources: PCI: 00:18.1 +constrain_resources: PCI: 00:18.2 +constrain_resources: PCI: 00:18.3 +constrain_resources: PCI: 00:18.4 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:02.0 +constrain_resources: PCI: 00:0d.0 +constrain_resources: PCI: 00:11.0 +constrain_resources: PCI: 00:12.0 +constrain_resources: PCI: 00:12.2 +constrain_resources: PCI: 00:13.0 +constrain_resources: PCI: 00:13.2 +constrain_resources: PCI: 00:14.0 +constrain_resources: I2C: 00:50 +constrain_resources: I2C: 00:51 +constrain_resources: I2C: 00:52 +constrain_resources: I2C: 00:53 +constrain_resources: PCI: 00:14.1 +constrain_resources: PCI: 00:14.2 +constrain_resources: PCI: 00:14.3 +constrain_resources: PNP: 002e.2 +skipping PNP: 002e.2@60 fixed resource, size=0! +skipping PNP: 002e.2@70 fixed resource, size=0! +constrain_resources: PNP: 002e.3 +skipping PNP: 002e.3@60 fixed resource, size=0! +skipping PNP: 002e.3@70 fixed resource, size=0! +constrain_resources: PNP: 002e.5 +skipping PNP: 002e.5@60 fixed resource, size=0! +skipping PNP: 002e.5@62 fixed resource, size=0! +skipping PNP: 002e.5@70 fixed resource, size=0! +skipping PNP: 002e.5@72 fixed resource, size=0! +constrain_resources: PNP: 002e.b +skipping PNP: 002e.b@60 fixed resource, size=0! +skipping PNP: 002e.b@70 fixed resource, size=0! +constrain_resources: PCI: 00:14.5 +constrain_resources: PCI: 00:15.0 +constrain_resources: PCI: 00:15.1 +constrain_resources: PCI: 00:15.2 +constrain_resources: PCI: 00:15.3 +constrain_resources: PCI: 00:16.0 +constrain_resources: PCI: 00:16.2 +constrain_resources: PCI: 00:18.1 +constrain_resources: PCI: 00:18.2 +constrain_resources: PCI: 00:18.3 +constrain_resources: PCI: 00:18.4 +avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff + lim->base 00000000 lim->limit 0000ffff +avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff + lim->base 00000000 lim->limit dfffffff +Setting resources... +PCI_DOMAIN: 0000 allocate_resources_io: base:0 size:1000 align:12 gran:0 limit:ffff +Assigned: PCI: 00:18.0 10d8 * [0x0 - 0xfff] io +PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1000 size: 1000 align: 12 gran: 0 done +PCI: 00:18.0 allocate_resources_io: base:0 size:1000 align:12 gran:12 limit:ffff +Assigned: PCI: 00:11.0 20 * [0x0 - 0xf] io +Assigned: PCI: 00:14.1 20 * [0x10 - 0x1f] io +Assigned: PCI: 00:11.0 10 * [0x20 - 0x27] io +Assigned: PCI: 00:11.0 18 * [0x28 - 0x2f] io +Assigned: PCI: 00:14.1 10 * [0x30 - 0x37] io +Assigned: PCI: 00:14.1 18 * [0x38 - 0x3f] io +Assigned: PCI: 00:11.0 14 * [0x40 - 0x43] io +Assigned: PCI: 00:11.0 1c * [0x44 - 0x47] io +Assigned: PCI: 00:14.1 14 * [0x48 - 0x4b] io +Assigned: PCI: 00:14.1 1c * [0x4c - 0x4f] io +PCI: 00:18.0 allocate_resources_io: next_base: 50 size: 1000 align: 12 gran: 12 done +PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:18.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:18.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI_DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:c100000 align:26 gran:0 limit:dfffffff +Assigned: PCI: 00:18.0 10b0 * [0xd0000000 - 0xd40fffff] mem +Assigned: PCI: 00:18.3 94 * [0xd8000000 - 0xdbffffff] mem +Assigned: PCI: 00:18.0 10b8 * [0xdc000000 - 0xdc0fffff] prefmem +PCI_DOMAIN: 0000 allocate_resources_mem: next_base: dc100000 size: c100000 align: 26 gran: 0 done +PCI: 00:18.0 allocate_resources_prefmem: base:dc000000 size:100000 align:20 gran:20 limit:dfffffff +Assigned: PCI: 00:00.0 fc * [0xdc000000 - 0xdc0000ff] prefmem +PCI: 00:18.0 allocate_resources_prefmem: next_base: dc000100 size: 100000 align: 20 gran: 20 done +PCI: 00:14.4 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff +PCI: 00:14.4 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done +PCI: 00:18.0 allocate_resources_mem: base:d0000000 size:4100000 align:26 gran:20 limit:dfffffff +Assigned: PCI: 00:18.3 94 * [0xd0000000 - 0xd3ffffff] mem +Assigned: PCI: 00:14.2 10 * [0xd4000000 - 0xd4003fff] mem +Assigned: PCI: 00:12.0 10 * [0xd4004000 - 0xd4004fff] mem +Assigned: PCI: 00:13.0 10 * [0xd4005000 - 0xd4005fff] mem +Assigned: PCI: 00:14.5 10 * [0xd4006000 - 0xd4006fff] mem +Assigned: PCI: 00:16.0 10 * [0xd4007000 - 0xd4007fff] mem +Assigned: PCI: 00:11.0 24 * [0xd4008000 - 0xd40083ff] mem +Assigned: PCI: 00:12.2 10 * [0xd4008400 - 0xd40084ff] mem +Assigned: PCI: 00:13.2 10 * [0xd4008500 - 0xd40085ff] mem +Assigned: PCI: 00:16.2 10 * [0xd4008600 - 0xd40086ff] mem +PCI: 00:18.0 allocate_resources_mem: next_base: d4008700 size: 4100000 align: 26 gran: 20 done +PCI: 00:14.4 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff +PCI: 00:14.4 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done +PCI: 00:18.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff +PCI: 00:18.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done +PCI: 00:18.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff +PCI: 00:18.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 + split: 128K table at =cffe0000 +0: mmio_basek=00340000, basek=00400000, limitk=00880000 +PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:18.0 10d8 <- [0x0000000000 - 0x0000000fff] size 0x00001000 gran 0x0c io +PCI: 00:18.0 10b8 <- [0x00dc000000 - 0x00dc0fffff] size 0x00100000 gran 0x14 prefmem +PCI: 00:18.0 10b0 <- [0x00d0000000 - 0x00d40fffff] size 0x04100000 gran 0x14 mem +PCI: 00:18.0 110d0 <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c io +PCI: 00:18.0 110a8 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 prefmem +PCI: 00:18.0 110a0 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 mem +PCI: 00:18.0 assign_resources, bus 0 link: 0 +PCI: 00:00.0 fc <- [0x00dc000000 - 0x00dc0000ff] size 0x00000100 gran 0x08 prefmem +PCI: 00:11.0 10 <- [0x0000000020 - 0x0000000027] size 0x00000008 gran 0x03 io +PCI: 00:11.0 14 <- [0x0000000040 - 0x0000000043] size 0x00000004 gran 0x02 io +PCI: 00:11.0 18 <- [0x0000000028 - 0x000000002f] size 0x00000008 gran 0x03 io +PCI: 00:11.0 1c <- [0x0000000044 - 0x0000000047] size 0x00000004 gran 0x02 io +PCI: 00:11.0 20 <- [0x0000000000 - 0x000000000f] size 0x00000010 gran 0x04 io +PCI: 00:11.0 24 <- [0x00d4008000 - 0x00d40083ff] size 0x00000400 gran 0x0a mem +PCI: 00:12.0 10 <- [0x00d4004000 - 0x00d4004fff] size 0x00001000 gran 0x0c mem +PCI: 00:12.2 10 <- [0x00d4008400 - 0x00d40084ff] size 0x00000100 gran 0x08 mem +PCI: 00:13.0 10 <- [0x00d4005000 - 0x00d4005fff] size 0x00001000 gran 0x0c mem +PCI: 00:13.2 10 <- [0x00d4008500 - 0x00d40085ff] size 0x00000100 gran 0x08 mem +PCI: 00:14.1 10 <- [0x0000000030 - 0x0000000037] size 0x00000008 gran 0x03 io +PCI: 00:14.1 14 <- [0x0000000048 - 0x000000004b] size 0x00000004 gran 0x02 io +PCI: 00:14.1 18 <- [0x0000000038 - 0x000000003f] size 0x00000008 gran 0x03 io +PCI: 00:14.1 1c <- [0x000000004c - 0x000000004f] size 0x00000004 gran 0x02 io +PCI: 00:14.1 20 <- [0x0000000010 - 0x000000001f] size 0x00000010 gran 0x04 io +PCI: 00:14.2 10 <- [0x00d4000000 - 0x00d4003fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io +PCI: 00:14.4 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem +PCI: 00:14.4 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem +PCI: 00:14.5 10 <- [0x00d4006000 - 0x00d4006fff] size 0x00001000 gran 0x0c mem +PCI: 00:16.0 10 <- [0x00d4007000 - 0x00d4007fff] size 0x00001000 gran 0x0c mem +PCI: 00:16.2 10 <- [0x00d4008600 - 0x00d40086ff] size 0x00000100 gran 0x08 mem +PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem +PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem +PCI: 00:18.0 assign_resources, bus 0 link: 0 +PCI: 00:18.0 assign_resources, bus 0 link: 1 +PCI: 00:18.0 assign_resources, bus 0 link: 1 +PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem +PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem +PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 APIC_CLUSTER: 0 + APIC_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: 01 + APIC: 02 + APIC: 03 + APIC: 04 + APIC: 05 + PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 + PCI_DOMAIN: 0000 resource base 0 size 1000 align 12 gran 0 limit ffff flags 40040100 index 10000000 + PCI_DOMAIN: 0000 resource base d0000000 size c100000 align 26 gran 0 limit dfffffff flags 40040200 index 10000100 + PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 + PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 + PCI_DOMAIN: 0000 resource base c0000 size cff40000 align 0 gran 0 limit 0 flags e0004200 index 20 + PCI_DOMAIN: 0000 resource base 100000000 size 120000000 align 0 gran 0 limit 0 flags e0004200 index 30 + PCI: 00:18.0 child on link 0 PCI: 00:00.0 + PCI: 00:18.0 resource base 0 size 1000 align 12 gran 12 limit ffff flags 60080100 index 10d8 + PCI: 00:18.0 resource base dc000000 size 100000 align 20 gran 20 limit dfffffff flags 60081200 index 10b8 + PCI: 00:18.0 resource base d0000000 size 4100000 align 26 gran 20 limit dfffffff flags 60080200 index 10b0 + PCI: 00:18.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080100 index 110d0 + PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081200 index 110a8 + PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080200 index 110a0 + PCI: 00:00.0 + PCI: 00:00.0 resource base dc000000 size 100 align 8 gran 8 limit dfffffff flags 60001200 index fc + PCI: 00:11.0 + PCI: 00:11.0 resource base 20 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:11.0 resource base 40 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:11.0 resource base 28 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:11.0 resource base 44 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:11.0 resource base d4008000 size 400 align 10 gran 10 limit dfffffff flags 60000200 index 24 + PCI: 00:12.0 + PCI: 00:12.0 resource base d4004000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 + PCI: 00:12.2 + PCI: 00:12.2 resource base d4008400 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 + PCI: 00:13.0 + PCI: 00:13.0 resource base d4005000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 + PCI: 00:13.2 + PCI: 00:13.2 resource base d4008500 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 + PCI: 00:14.0 + PCI: 00:14.1 + PCI: 00:14.1 resource base 30 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:14.1 resource base 48 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:14.1 resource base 38 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:14.1 resource base 4c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:14.1 resource base 10 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:14.2 + PCI: 00:14.2 resource base d4000000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 10 + PCI: 00:14.3 + PCI: 00:14.4 + PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 + PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 + PCI: 00:14.5 + PCI: 00:14.5 resource base d4006000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 + PCI: 00:16.0 + PCI: 00:16.0 resource base d4007000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 + PCI: 00:16.2 + PCI: 00:16.2 resource base d4008600 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 + PCI: 00:18.0 + PCI: 00:18.1 + PCI: 00:18.2 + PCI: 00:18.3 + PCI: 00:18.3 resource base d0000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 + PCI: 00:18.4 + PCI: 00:00.0 + PCI: 00:00.1 + PCI: 00:02.0 + PCI: 00:03.0 + PCI: 00:04.0 + PCI: 00:05.0 + PCI: 00:06.0 + PCI: 00:07.0 + PCI: 00:08.0 + PCI: 00:09.0 + PCI: 00:0a.0 + PCI: 00:0b.0 + PCI: 00:0c.0 + PCI: 00:0d.0 + PCI: 00:11.0 + PCI: 00:12.0 + PCI: 00:12.2 + PCI: 00:13.0 + PCI: 00:13.2 + PCI: 00:14.0 child on link 0 I2C: 00:50 + I2C: 00:50 + I2C: 00:51 + I2C: 00:52 + I2C: 00:53 + PCI: 00:14.1 + PCI: 00:14.2 + PCI: 00:14.3 child on link 0 PNP: 002e.0 + PNP: 002e.0 + PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 + PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.3 + PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.5 + PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 72 + PNP: 002e.6 + PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 002e.7 + PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.8 + PNP: 002e.9 + PNP: 002e.a + PNP: 002e.b + PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 + PCI: 00:14.4 + PCI: 00:14.5 + PCI: 00:14.6 + PCI: 00:15.0 + PCI: 00:15.1 + PCI: 00:15.2 + PCI: 00:15.3 + PCI: 00:16.0 + PCI: 00:16.2 + PCI: 00:18.1 + PCI: 00:18.2 + PCI: 00:18.3 + PCI: 00:18.3 resource base d8000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 + PCI: 00:18.4 +Done allocating resources. +POST: 0x88 +Enabling resources... +PCI: 00:18.0 cmd <- 00 +PCI: 00:18.1 subsystem <- 1043/843e +PCI: 00:18.1 cmd <- 00 +PCI: 00:18.2 subsystem <- 1043/843e +PCI: 00:18.2 cmd <- 00 +PCI: 00:18.3 cmd <- 00 +PCI: 00:18.4 subsystem <- 1043/843e +PCI: 00:18.4 cmd <- 00 +PCI: 00:00.0 cmd <- 02 +PCI: 00:11.0 cmd <- 03 +PCI: 00:12.0 cmd <- 02 +PCI: 00:12.2 cmd <- 02 +PCI: 00:13.0 cmd <- 02 +PCI: 00:13.2 cmd <- 02 +PCI: 00:14.0 cmd <- 403 +PCI: 00:14.1 cmd <- 01 +PCI: 00:14.2 cmd <- 02 +PCI: 00:14.3 cmd <- 0f +PCI: 00:14.4 bridge ctrl <- 0003 +PCI: 00:14.4 cmd <- 00 +PCI: 00:14.5 cmd <- 02 +PCI: 00:16.0 cmd <- 02 +PCI: 00:16.2 cmd <- 02 +PCI: 00:18.0 cmd <- 00 +PCI: 00:18.1 cmd <- 00 +PCI: 00:18.2 cmd <- 00 +PCI: 00:18.3 cmd <- 00 +PCI: 00:18.4 cmd <- 00 +done. +Initializing devices... +Root Device init +APIC_CLUSTER: 0 init +start_eip=0x00005000, offset=0x00200000, code_size=0x0000005b +Initializing CPU #0 +CPU: vendor AMD device 100fa0 +CPU: family 10, model 0a, stepping 00 +nodeid = 00, coreid = 00 +POST: 0x60 +Enabling cache +CPU ID 0x80000001: 100fa0 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB + +Setting fixed MTRRs(0-88) type: UC +Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM +Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM +DONE fixed MTRRs +Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB +ADDRESS_MASK_HIGH=0xffff +Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB +Setting variable MTRR 1, base: 3328MB, range: 256MB, type UC +ADDRESS_MASK_HIGH=0xffff +Setting variable MTRR 2, base: 3584MB, range: 512MB, type UC +ADDRESS_MASK_HIGH=0xffff +DONE variable MTRRs +Clear out the extra MTRR's +call enable_var_mtrr() +Leave x86_setup_var_mtrrs +POST: 0x6a + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +POST: 0x93 +Setting up local apic... apic_id: 0x00 done. +POST: 0x9b +CPU model: AMD Processor model unknown +siblings = 05, CPU #0 initialized +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 1. +Sending STARTUP #1 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #1 +CPU: vendor AMD device 100fa0 +CPU: family 10, model 0a, stepping 00 +nodeid = 00, coreid = 00 +POST: 0x60 +Enabling cache +CPU ID 0x80000001: 100fa0 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB + +Setting fixed MTRRs(0-88) type: UC +Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM +Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM +DONE fixed MTRRs +Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB +ADDRESS_MASK_HIGH=0xffff +Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB +Setting variable MTRR 1, base: 3328MB, range: 256MB, type UC +ADDRESS_MASK_HIGH=0xffff +Setting variable MTRR 2, base: 3584MB, range: 512MB, type UC +ADDRESS_MASK_HIGH=0xffff +DONE variable MTRRs +Clear out the extra MTRR's +call enable_var_mtrr() +Leave x86_setup_var_mtrrs +POST: 0x6a + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +POST: 0x93 +Setting up local apic... apic_id: 0x01 done. +POST: 0x9b +CPU model: AMD Processor model unknown +siblings = 05, CPU #1 initialized +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 1. +Sending STARTUP #1 to 2. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #2 +CPU: vendor AMD device 100fa0 +CPU: family 10, model 0a, stepping 00 +nodeid = 00, coreid = 00 +POST: 0x60 +Enabling cache +CPU ID 0x80000001: 100fa0 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB + +Setting fixed MTRRs(0-88) type: UC +Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM +Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM +DONE fixed MTRRs +Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB +ADDRESS_MASK_HIGH=0xffff +Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB +Setting variable MTRR 1, base: 3328MB, range: 256MB, type UC +ADDRESS_MASK_HIGH=0xffff +Setting variable MTRR 2, base: 3584MB, range: 512MB, type UC +ADDRESS_MASK_HIGH=0xffff +DONE variable MTRRs +Clear out the extra MTRR's +call enable_var_mtrr() +Leave x86_setup_var_mtrrs +POST: 0x6a + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +POST: 0x93 +Setting up local apic... apic_id: 0x02 done. +POST: 0x9b +CPU model: AMD Processor model unknown +siblings = 05, CPU #2 initialized +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 1. +Sending STARTUP #1 to 3. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #3 +CPU: vendor AMD device 100fa0 +CPU: family 10, model 0a, stepping 00 +nodeid = 00, coreid = 00 +POST: 0x60 +Enabling cache +CPU ID 0x80000001: 100fa0 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB + +Setting fixed MTRRs(0-88) type: UC +Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM +Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM +DONE fixed MTRRs +Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB +ADDRESS_MASK_HIGH=0xffff +Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB +Setting variable MTRR 1, base: 3328MB, range: 256MB, type UC +ADDRESS_MASK_HIGH=0xffff +Setting variable MTRR 2, base: 3584MB, range: 512MB, type UC +ADDRESS_MASK_HIGH=0xffff +DONE variable MTRRs +Clear out the extra MTRR's +call enable_var_mtrr() +Leave x86_setup_var_mtrrs +POST: 0x6a + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +POST: 0x93 +Setting up local apic... apic_id: 0x03 done. +POST: 0x9b +CPU model: AMD Processor model unknown +siblings = 05, CPU #3 initialized +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 1. +Sending STARTUP #1 to 4. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #4 +CPU: vendor AMD device 100fa0 +CPU: family 10, model 0a, stepping 00 +nodeid = 00, coreid = 00 +POST: 0x60 +Enabling cache +CPU ID 0x80000001: 100fa0 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB + +Setting fixed MTRRs(0-88) type: UC +Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM +Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM +DONE fixed MTRRs +Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB +ADDRESS_MASK_HIGH=0xffff +Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB +Setting variable MTRR 1, base: 3328MB, range: 256MB, type UC +ADDRESS_MASK_HIGH=0xffff +Setting variable MTRR 2, base: 3584MB, range: 512MB, type UC +ADDRESS_MASK_HIGH=0xffff +DONE variable MTRRs +Clear out the extra MTRR's +call enable_var_mtrr() +Leave x86_setup_var_mtrrs +POST: 0x6a + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +POST: 0x93 +Setting up local apic... apic_id: 0x04 done. +POST: 0x9b +CPU model: AMD Processor model unknown +siblings = 05, CPU #4 initialized +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 1. +Sending STARTUP #1 to 5. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #5 +Waiting for 1 CPUS to stop +CPU: vendor AMD device 100fa0 +CPU: family 10, model 0a, stepping 00 +nodeid = 00, coreid = 00 +POST: 0x60 +Enabling cache +CPU ID 0x80000001: 100fa0 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB + +Setting fixed MTRRs(0-88) type: UC +Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM +Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM +DONE fixed MTRRs +Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB +ADDRESS_MASK_HIGH=0xffff +Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB +Setting variable MTRR 1, base: 3328MB, range: 256MB, type UC +ADDRESS_MASK_HIGH=0xffff +Setting variable MTRR 2, base: 3584MB, range: 512MB, type UC +ADDRESS_MASK_HIGH=0xffff +DONE variable MTRRs +Clear out the extra MTRR's +call enable_var_mtrr() +Leave x86_setup_var_mtrrs +POST: 0x6a + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +POST: 0x93 +Setting up local apic... apic_id: 0x05 done. +POST: 0x9b +CPU model: AMD Processor model unknown +siblings = 05, CPU #5 initialized +All AP CPUs stopped +SB900 - Early.c - sb_After_Pci_Init - Start. +SB900 - Cfg.c - sb900_cimx_config - Start. +SB900 - Cfg.c - sb900_cimx_config - End. +SB900 - Early.c - sb_After_Pci_Init - End. +SB900 - Early.c - sb_Mid_Post_Init - Start. +SB900 - Cfg.c - sb900_cimx_config - Start. +SB900 - Cfg.c - sb900_cimx_config - End. +SB900 - Early.c - sb_Mid_Post_Init - End. +PCI: 00:18.0 init +PCI: 00:18.1 init +Searching for pci1022,1201.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1022,1201.rom'. +PCI: 00:18.2 init +Searching for pci1022,1202.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1022,1202.rom'. +PCI: 00:18.3 init +NB: Function 3 Misc Control.. done. +PCI: 00:18.4 init +Searching for pci1022,1204.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1022,1204.rom'. +PCI: 00:00.0 init +IOAPIC: Initializing IOAPIC at 0xdc000000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x01 +IOAPIC: 24 interrupts +IOAPIC: Enabling interrupts on FSB +IOAPIC: Enabling interrupts on APIC serial bus +IOAPIC not responding. +PCI: 00:11.0 init +Searching for pci1002,4393.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1002,4393.rom'. +PCI: 00:12.0 init +Searching for pci1002,4397.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1002,4397.rom'. +PCI: 00:12.2 init +Searching for pci1002,4396.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1002,4396.rom'. +PCI: 00:13.0 init +Searching for pci1002,4397.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1002,4397.rom'. +PCI: 00:13.2 init +Searching for pci1002,4396.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1002,4396.rom'. +PCI: 00:14.0 init +Searching for pci1002,4385.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1002,4385.rom'. +PCI: 00:14.1 init +Searching for pci1002,439c.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1002,439c.rom'. +PCI: 00:14.2 init +Searching for pci1002,4383.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1002,4383.rom'. +PCI: 00:14.3 init +Searching for pci1002,439d.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1002,439d.rom'. +PCI: 00:14.5 init +Searching for pci1002,4399.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1002,4399.rom'. +PCI: 00:16.0 init +Searching for pci1002,4397.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1002,4397.rom'. +PCI: 00:16.2 init +Searching for pci1002,4396.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1002,4396.rom'. +PCI: 00:18.0 init +PCI: 00:18.1 init +Searching for pci1022,1201.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1022,1201.rom'. +PCI: 00:18.2 init +Searching for pci1022,1202.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1022,1202.rom'. +PCI: 00:18.3 init +NB: Function 3 Misc Control.. done. +PCI: 00:18.4 init +Searching for pci1022,1204.rom +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Check config +Check +Could not find file 'pci1022,1204.rom'. +Devices initialized +Show all devs...After init. +Root Device: enabled 1 +APIC_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +PCI_DOMAIN: 0000: enabled 1 +PCI: 00:18.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:00.1: enabled 0 +PCI: 00:02.0: enabled 1 +PCI: 00:03.0: enabled 0 +PCI: 00:04.0: enabled 0 +PCI: 00:05.0: enabled 0 +PCI: 00:06.0: enabled 0 +PCI: 00:07.0: enabled 0 +PCI: 00:08.0: enabled 0 +PCI: 00:09.0: enabled 0 +PCI: 00:0a.0: enabled 0 +PCI: 00:0b.0: enabled 0 +PCI: 00:0c.0: enabled 0 +PCI: 00:0d.0: enabled 1 +PCI: 00:11.0: enabled 1 +PCI: 00:12.0: enabled 1 +PCI: 00:12.2: enabled 1 +PCI: 00:13.0: enabled 1 +PCI: 00:13.2: enabled 1 +PCI: 00:14.0: enabled 1 +I2C: 00:50: enabled 1 +I2C: 00:51: enabled 1 +I2C: 00:52: enabled 1 +I2C: 00:53: enabled 1 +PCI: 00:14.1: enabled 1 +PCI: 00:14.2: enabled 1 +PCI: 00:14.3: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 0 +PNP: 002e.2: enabled 1 +PNP: 002e.3: enabled 1 +PNP: 002e.5: enabled 1 +PNP: 002e.6: enabled 0 +PNP: 002e.7: enabled 0 +PNP: 002e.8: enabled 0 +PNP: 002e.9: enabled 0 +PNP: 002e.a: enabled 0 +PNP: 002e.b: enabled 1 +PCI: 00:14.4: enabled 0 +PCI: 00:14.5: enabled 1 +PCI: 00:14.6: enabled 0 +PCI: 00:15.0: enabled 1 +PCI: 00:15.1: enabled 1 +PCI: 00:15.2: enabled 1 +PCI: 00:15.3: enabled 1 +PCI: 00:16.0: enabled 1 +PCI: 00:16.2: enabled 1 +PCI: 00:18.1: enabled 1 +PCI: 00:18.2: enabled 1 +PCI: 00:18.3: enabled 1 +PCI: 00:18.4: enabled 1 +APIC: 01: enabled 1 +APIC: 02: enabled 1 +APIC: 03: enabled 1 +APIC: 04: enabled 1 +APIC: 05: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:11.0: enabled 1 +PCI: 00:12.0: enabled 1 +PCI: 00:12.2: enabled 1 +PCI: 00:13.0: enabled 1 +PCI: 00:13.2: enabled 1 +PCI: 00:14.0: enabled 1 +PCI: 00:14.1: enabled 1 +PCI: 00:14.2: enabled 1 +PCI: 00:14.3: enabled 1 +PCI: 00:14.4: enabled 1 +PCI: 00:14.5: enabled 1 +PCI: 00:16.0: enabled 1 +PCI: 00:16.2: enabled 1 +PCI: 00:18.0: enabled 1 +PCI: 00:18.1: enabled 1 +PCI: 00:18.2: enabled 1 +PCI: 00:18.3: enabled 1 +PCI: 00:18.4: enabled 1 +POST: 0x89 +Re-Initializing CBMEM area to 0xcffe0000 +Initializing CBMEM area to 0xcffe0000 (131072 bytes) +Adding CBMEM entry as no. 1 +Moving GDT to cffe0200...ok +High Tables Base is cffe0000. +POST: 0x9a +SB900 - Early.c - sb_Late_Post - Start. +SB900 - Cfg.c - sb900_cimx_config - Start. +SB900 - Cfg.c - sb900_cimx_config - End. +SB900 - Early.c - sb_Late_Post - End. +Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done. +Adding CBMEM entry as no. 2 +Writing IRQ routing tables to 0xcffe0400...write_pirq_routing_table done. +PIRQ table: 48 bytes. +POST: 0x9b +Wrote the mp table end at: 000f0410 - 000f055c +Adding CBMEM entry as no. 3 +Wrote the mp table end at: cffe1410 - cffe155c +MP table: 348 bytes. +POST: 0x9c +Adding CBMEM entry as no. 4 +ACPI: Writing ACPI tables at cffe2400... +ACPI: * HPET at cffe24c8 +ACPI: added table 1/32, length now 40 +ACPI: * MADT at cffe2500 +ACPI: added table 2/32, length now 44 +ACPI: * SRAT at cffe2580 +SRAT: lapic cpu_index=00, node_id=00, apic_id=00 +SRAT: lapic cpu_index=01, node_id=00, apic_id=01 +SRAT: lapic cpu_index=02, node_id=00, apic_id=02 +SRAT: lapic cpu_index=03, node_id=00, apic_id=03 +SRAT: lapic cpu_index=04, node_id=00, apic_id=04 +SRAT: lapic cpu_index=05, node_id=00, apic_id=05 +set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 +set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=0033fd00 +set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00480000 +ACPI: added table 3/32, length now 48 +ACPI: * SLIT at cffe2688 +ACPI: added table 4/32, length now 52 +ACPI: * SSDT at cffe26c0 +ACPI: added table 5/32, length now 56 +ACPI: * SSDT for PState at cffe2cf5 +ACPI: * DSDT at cffe2cf8 +ACPI: * DSDT @ cffe2cf8 Length 2969 +ACPI: * FACS at cffe5668 +ACPI: * FADT at cffe56a8 +ACPI_BLK_BASE: 0x0800 +ACPI: added table 6/32, length now 60 +ACPI: done. +ACPI tables: 13212 bytes. +Adding CBMEM entry as no. 5 +smbios_write_tables: cffed800 +Root Device (ASUS M5A99X-EVO Mainboard) +APIC_CLUSTER: 0 (AMD FAM10 Root Complex) +APIC: 00 (socket AM3) +PCI_DOMAIN: 0000 (AMD FAM10 Root Complex) +PCI: 00:18.0 (AMD FAM10 Northbridge) +PCI: 00:00.0 (ATI rd890) +PCI: 00:00.1 (ATI rd890) +PCI: 00:02.0 (ATI rd890) +PCI: 00:03.0 (ATI rd890) +PCI: 00:04.0 (ATI rd890) +PCI: 00:05.0 (ATI rd890) +PCI: 00:06.0 (ATI rd890) +PCI: 00:07.0 (ATI rd890) +PCI: 00:08.0 (ATI rd890) +PCI: 00:09.0 (ATI rd890) +PCI: 00:0a.0 (ATI rd890) +PCI: 00:0b.0 (ATI rd890) +PCI: 00:0c.0 (ATI rd890) +PCI: 00:0d.0 (ATI rd890) +PCI: 00:11.0 (ATI SB900) +PCI: 00:12.0 (ATI SB900) +PCI: 00:12.2 (ATI SB900) +PCI: 00:13.0 (ATI SB900) +PCI: 00:13.2 (ATI SB900) +PCI: 00:14.0 (ATI SB900) +I2C: 00:50 () +I2C: 00:51 () +I2C: 00:52 () +I2C: 00:53 () +PCI: 00:14.1 (ATI SB900) +PCI: 00:14.2 (ATI SB900) +PCI: 00:14.3 (ATI SB900) +PNP: 002e.0 (ITE IT8721F Super I/O) +PNP: 002e.1 (ITE IT8721F Super I/O) +PNP: 002e.2 (ITE IT8721F Super I/O) +PNP: 002e.3 (ITE IT8721F Super I/O) +PNP: 002e.5 (ITE IT8721F Super I/O) +PNP: 002e.6 (ITE IT8721F Super I/O) +PNP: 002e.7 (ITE IT8721F Super I/O) +PNP: 002e.8 (ITE IT8721F Super I/O) +PNP: 002e.9 (ITE IT8721F Super I/O) +PNP: 002e.a (ITE IT8721F Super I/O) +PNP: 002e.b (ITE IT8721F Super I/O) +PCI: 00:14.4 (ATI SB900) +PCI: 00:14.5 (ATI SB900) +PCI: 00:14.6 (ATI SB900) +PCI: 00:15.0 (ATI SB900) +PCI: 00:15.1 (ATI SB900) +PCI: 00:15.2 (ATI SB900) +PCI: 00:15.3 (ATI SB900) +PCI: 00:16.0 (ATI SB900) +PCI: 00:16.2 (ATI SB900) +PCI: 00:18.1 (AMD FAM10 Northbridge) +PCI: 00:18.2 (AMD FAM10 Northbridge) +PCI: 00:18.3 (AMD FAM10 Northbridge) +PCI: 00:18.4 (AMD FAM10 Northbridge) +APIC: 01 () +APIC: 02 () +APIC: 03 () +APIC: 04 () +APIC: 05 () +PCI: 00:00.0 () +PCI: 00:11.0 () +PCI: 00:12.0 () +PCI: 00:12.2 () +PCI: 00:13.0 () +PCI: 00:13.2 () +PCI: 00:14.0 () +PCI: 00:14.1 () +PCI: 00:14.2 () +PCI: 00:14.3 () +PCI: 00:14.4 () +PCI: 00:14.5 () +PCI: 00:16.0 () +PCI: 00:16.2 () +PCI: 00:18.0 () +PCI: 00:18.1 () +PCI: 00:18.2 () +PCI: 00:18.3 () +PCI: 00:18.4 () +SMBIOS tables: 289 bytes. +POST: 0x9d +Adding CBMEM entry as no. 6 +Writing high table forward entry at 0x00000500 +Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4fdf +New low_table_end: 0x00000528 +Now going to write high coreboot table at 0xcffee000 +rom_table_end = 0xcffee000 +Adjust low_table_end from 0x00000528 to 0x00001000 +Adjust rom_table_end from 0xcffee000 to 0xcfff0000 +Adding high table area +coreboot memory table: + 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES + 1. 0000000000001000-000000000009ffff: RAM + 2. 00000000000c0000-00000000cffdffff: RAM + 3. 00000000cffe0000-00000000cfffffff: CONFIGURATION TABLES + 4. 00000000e0000000-00000000efffffff: RESERVED + 5. 0000000100000000-000000021fffffff: RAM +Wrote coreboot table at: cffee000, 0x1f8 bytes, checksum d132 +coreboot table: 528 bytes. +POST: 0x9e +POST: 0x9d +Multiboot Information structure has been written. + 0. FREE SPACE cfff6000 0000a000 + 1. GDT cffe0200 00000200 + 2. IRQ TABLE cffe0400 00001000 + 3. SMP TABLE cffe1400 00001000 + 4. ACPI cffe2400 0000b400 + 5. SMBIOS cffed800 00000800 + 6. COREBOOT cffee000 00008000 +Searching for fallback/payload +Check cmos_layout.bin +Check fallback/romstage +Check fallback/coreboot_ram +Check fallback/payload +Got a payload +Loading segment from rom address 0xffc44bb8 + code (compression=1) + New segment dstaddr 0xe5370 memsize 0x1ac90 srcaddr 0xffc44bf0 filesize 0xce24 + (cleaned up) New segment addr 0xe5370 size 0x1ac90 offset 0xffc44bf0 filesize 0xce24 +Loading segment from rom address 0xffc44bd4 + Entry Point 0x00000000 +Loading Segment: addr: 0x00000000000e5370 memsz: 0x000000000001ac90 filesz: 0x000000000000ce24 +lb: [0x0000000000200000, 0x0000000000340000) +Post relocation: addr: 0x00000000000e5370 memsz: 0x000000000001ac90 filesz: 0x000000000000ce24 +using LZMA +[ 0x000e5370, 00100000, 0x00100000) <- ffc44bf0 +dest 000e5370, end 00100000, bouncebuffer cfd60000 +Loaded segments +Jumping to boot code at fbfbb +POST: 0xf8 +entry = 0x000fbfbb +lb_start = 0x00200000 +lb_size = 0x00140000 +adjust = 0xcfca0000 +buffer = 0xcfd60000 + elf_boot_notes = 0x0023bcfc +adjusted_boot_notes = 0xcfedbcfc +Start bios (version 1.6.3-20120406_134746-oldx86) +Find memory size +Attempting to find coreboot table +Found coreboot table forwarder. +Now attempting to find coreboot memory map +Add to e820 map: 00000000 00001000 2 +Add to e820 map: 00001000 0009f000 1 +Add to e820 map: 000c0000 cff20000 1 +Add to e820 map: cffe0000 00020000 2 +Add to e820 map: e0000000 10000000 2 +Add to e820 map: 00000000 20000000 1 +Add to e820 map: 00000000 00004000 1 +Found mainboard ASUS M5A99X-EVO +Found CBFS header at 0xffffefe0 +Add to e820 map: 000a0000 00050000 -1 +Add to e820 map: 000f0000 00010000 2 +Ram Size=0xcffe0000 (0x0000000120000000 high) +malloc setup +Add to e820 map: cffd0000 00010000 2 +init ivt +init bda +Add to e820 map: 0009fc00 00000400 2 +init pic +init timer +CPU Mhz=800 +init timer: 01 +init timer: 02 +init timer: 03 +init timer: 04 +init timer: 05 +init timer: 06 +init timer: 07 +init timer: 08 +init timer: 09 +init timer: 10 +init timer: 11 +init timer: 12 +math cp init +PCI probe +Searching CBFS for prefix etc/extra-pci-roots +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcfe70 (detail=0xcffcfee0) +PCI device 00:00.0 (vd=1002:5a14 c=0600) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcfdd0 (detail=0xcffcfe40) +PCI device 00:11.0 (vd=1002:4393 c=0101) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcfd30 (detail=0xcffcfda0) +PCI device 00:12.0 (vd=1002:4397 c=0c03) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcfc90 (detail=0xcffcfd00) +PCI device 00:12.2 (vd=1002:4396 c=0c03) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcfbf0 (detail=0xcffcfc60) +PCI device 00:13.0 (vd=1002:4397 c=0c03) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcfb50 (detail=0xcffcfbc0) +PCI device 00:13.2 (vd=1002:4396 c=0c03) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcfab0 (detail=0xcffcfb20) +PCI device 00:14.0 (vd=1002:4385 c=0c05) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcfa10 (detail=0xcffcfa80) +PCI device 00:14.1 (vd=1002:439c c=0101) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcf970 (detail=0xcffcf9e0) +PCI device 00:14.2 (vd=1002:4383 c=0403) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcf8d0 (detail=0xcffcf940) +PCI device 00:14.3 (vd=1002:439d c=0601) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcf830 (detail=0xcffcf8a0) +PCI device 00:14.4 (vd=1002:4384 c=0604) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcf790 (detail=0xcffcf800) +PCI device 00:14.5 (vd=1002:4399 c=0c03) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcf6f0 (detail=0xcffcf760) +PCI device 00:16.0 (vd=1002:4397 c=0c03) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcf650 (detail=0xcffcf6c0) +PCI device 00:16.2 (vd=1002:4396 c=0c03) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcf5b0 (detail=0xcffcf620) +PCI device 00:18.0 (vd=1022:1200 c=0600) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcf510 (detail=0xcffcf580) +PCI device 00:18.1 (vd=1022:1201 c=0600) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcf470 (detail=0xcffcf4e0) +PCI device 00:18.2 (vd=1022:1202 c=0600) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcf3d0 (detail=0xcffcf440) +PCI device 00:18.3 (vd=1022:1203 c=0600) +pmm_malloc zone=0x000f0204 handle=ffffffff size=112 align=10 ret=0xcffcf330 (detail=0xcffcf3a0) +PCI device 00:18.4 (vd=1022:1204 c=0600) +Found 19 PCI devices (max PCI bus is 01) +Searching CBFS for prefix bootorder +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Found 6 cpu(s) max supported 6 cpu(s) +init bios32 +[wurm] pmm_setup +init PMM +[wurm] pnp_setup +init PNPBIOS table +[wurm] kbd_setup +init keyboard +[wurm] mouse_setup +init mouse +[wurm] init_bios_tables +Relocating coreboot bios tables +pmm_malloc zone=0x000f0200 handle=ffffffff size=48 align=10 ret=0x000fdbc0 (detail=0xcffcf300) +Copying PIR from 0xcffe0400 to 0x000fdbc0 +pmm_malloc zone=0x000f0200 handle=ffffffff size=348 align=10 ret=0x000fda60 (detail=0xcffcf2d0) +Copying MPTABLE from 0xcffe1400/cffe1410 to 0x000fda60 +pmm_malloc zone=0x000f0200 handle=ffffffff size=20 align=10 ret=0x000fda40 (detail=0xcffcf2a0) +Copying ACPI RSDP from 0xcffe2400 to 0x000fda40 +pmm_malloc zone=0x000f0200 handle=ffffffff size=31 align=10 ret=0x000fda20 (detail=0xcffcf270) +Copying SMBIOS entry point from 0xcffed800 to 0x000fda20 +[wurm] vga_setup +Scan for VGA option rom +Searching CBFS for prefix etc/optionroms-checksum +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Searching CBFS for prefix etc/s3-resume-vga-init +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Searching CBFS for prefix etc/screen-and-debug +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Searching CBFS for prefix vgaroms/ +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +init usb +pmm_malloc zone=0x000f0204 handle=ffffffff size=72 align=10 ret=0xcffcf1f0 (detail=0xcffcf240) +EHCI init on dev 00:12.2 (regs=0xd4008420) +pmm_malloc zone=0x000f0208 handle=ffffffff size=4096 align=1000 ret=0xcffdf000 (detail=0xcffcf1c0) +pmm_malloc zone=0x000f0208 handle=ffffffff size=48 align=40 ret=0xcffdefc0 (detail=0xcffcf190) +pmm_malloc zone=0x000f0208 handle=ffffffff size=48 align=40 ret=0xcffdef80 (detail=0xcffcf160) +pmm_free 0xcffdf000 (detail=0xcffcf1c0) +pmm_free 0xcffdefc0 (detail=0xcffcf190) +pmm_free 0xcffdef80 (detail=0xcffcf160) +pmm_free 0xcffcf1f0 (detail=0xcffcf240) +pmm_malloc zone=0x000f0204 handle=ffffffff size=72 align=10 ret=0xcffcf1f0 (detail=0xcffcf240) +EHCI init on dev 00:13.2 (regs=0xd4008520) +pmm_malloc zone=0x000f0208 handle=ffffffff size=4096 align=1000 ret=0xcffdf000 (detail=0xcffcf1c0) +pmm_malloc zone=0x000f0208 handle=ffffffff size=48 align=40 ret=0xcffdefc0 (detail=0xcffcf190) +pmm_malloc zone=0x000f0208 handle=ffffffff size=48 align=40 ret=0xcffdef80 (detail=0xcffcf160) +pmm_free 0xcffdf000 (detail=0xcffcf1c0) +pmm_free 0xcffdefc0 (detail=0xcffcf190) +pmm_free 0xcffdef80 (detail=0xcffcf160) +pmm_free 0xcffcf1f0 (detail=0xcffcf240) +pmm_malloc zone=0x000f0204 handle=ffffffff size=24 align=10 ret=0xcffcf220 (detail=0xcffcf240) +OHCI init on dev 00:14.5 (regs=0xd4006000) +pmm_malloc zone=0x000f0208 handle=ffffffff size=256 align=100 ret=0xcffdff00 (detail=0xcffcf1f0) +pmm_malloc zone=0x000f0208 handle=ffffffff size=16 align=10 ret=0xcffdfef0 (detail=0xcffcf1c0) +pmm_free 0xcffdff00 (detail=0xcffcf1f0) +pmm_free 0xcffdfef0 (detail=0xcffcf1c0) +pmm_malloc zone=0x000f0204 handle=ffffffff size=72 align=10 ret=0xcffcf1a0 (detail=0xcffcf1f0) +EHCI init on dev 00:16.2 (regs=0xd4008620) +pmm_malloc zone=0x000f0208 handle=ffffffff size=4096 align=1000 ret=0xcffdf000 (detail=0xcffcf170) +pmm_malloc zone=0x000f0208 handle=ffffffff size=48 align=40 ret=0xcffdefc0 (detail=0xcffcf140) +pmm_malloc zone=0x000f0208 handle=ffffffff size=48 align=40 ret=0xcffdef80 (detail=0xcffcf110) +pmm_free 0xcffdf000 (detail=0xcffcf170) +pmm_free 0xcffdefc0 (detail=0xcffcf140) +pmm_free 0xcffdef80 (detail=0xcffcf110) +pmm_free 0xcffcf1a0 (detail=0xcffcf1f0) +init ps2port +i8042_flush +i8042_command cmd=1aa +i8042_wait_write +i8042_wait_read +i8042 param=55 +i8042_command cmd=1ab +i8042_wait_write +i8042_wait_read +i8042 param=0 +Searching CBFS for prefix etc/ps2-keyboard-spinup +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +ps2_command aux=0 cmd=2ff +i8042 ctr old=30 new=30 +i8042_command cmd=1060 +i8042_wait_write +i8042_wait_write +i8042_command cmd=1060 +i8042_wait_write +i8042_wait_write +ps2_sendbyte aux=0 cmd=ff +i8042_kbd_write c=255 +i8042_wait_write +ps2 read fe +Got ps2 nak (status=51) +i8042_command cmd=1060 +i8042_wait_write +i8042_wait_write +ps2 command 2ff failed (aux=0) +init serial +Found 2 serial ports +init floppy drives +init hard drives +pmm_malloc zone=0x000f0200 handle=ffffffff size=16 align=10 ret=0x000fda10 (detail=0xcffcf1f0) +ATA controller 1 at 20/40/0 (irq 0 dev 88) +powerup iobase=20 st=50 +powerup iobase=20 st=7f +ata_detect ata0-0: sc=55 sn=0 dh=ff +powerup iobase=20 st=7f +powerup iobase=20 st=50 +ata_detect ata0-1: sc=55 sn=0 dh=b0 +pmm_malloc zone=0x000f0200 handle=ffffffff size=16 align=10 ret=0x000fda00 (detail=0xcffcf1c0) +ATA controller 2 at 28/44/0 (irq 0 dev 88) +powerup iobase=28 st=7f +powerup iobase=28 st=7f +ata_detect ata1-0: sc=ff sn=ff dh=ff +powerup iobase=28 st=7f +powerup iobase=28 st=7f +ata_detect ata1-1: sc=ff sn=ff dh=ff +pmm_malloc zone=0x000f0200 handle=ffffffff size=16 align=10 ret=0x000fd9f0 (detail=0xcffcf190) +ATA controller 3 at 1f0/3f4/10 (irq 14 dev a1) +powerup iobase=1f0 st=7f +powerup iobase=1f0 st=7f +ata_detect ata2-0: sc=ff sn=ff dh=ff +powerup iobase=1f0 st=7f +powerup iobase=1f0 st=7f +ata_detect ata2-1: sc=ff sn=ff dh=ff +pmm_malloc zone=0x000f0200 handle=ffffffff size=16 align=10 ret=0x000fd9e0 (detail=0xcffcf160) +ATA controller 4 at 170/374/18 (irq 15 dev a1) +powerup iobase=170 st=7f +powerup iobase=170 st=7f +ata_detect ata3-0: sc=ff sn=ff dh=ff +powerup iobase=170 st=7f +powerup iobase=170 st=7f +ata_detect ata3-1: sc=ff sn=ff dh=ff +init ahci +Searching CBFS for prefix img/ +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +[wurm] optionrom_setup +Scan for option roms +Attempting to init PCI bdf 00:00.0 (vd 1002:5a14) +Searching CBFS for prefix pci1002,5a14.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:00.0 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:12.0 (vd 1002:4397) +Searching CBFS for prefix pci1002,4397.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:12.0 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:12.2 (vd 1002:4396) +Searching CBFS for prefix pci1002,4396.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:12.2 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:13.0 (vd 1002:4397) +Searching CBFS for prefix pci1002,4397.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:13.0 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:13.2 (vd 1002:4396) +Searching CBFS for prefix pci1002,4396.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:13.2 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:14.0 (vd 1002:4385) +Searching CBFS for prefix pci1002,4385.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:14.0 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:14.2 (vd 1002:4383) +Searching CBFS for prefix pci1002,4383.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:14.2 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:14.3 (vd 1002:439d) +Searching CBFS for prefix pci1002,439d.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:14.3 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:14.4 (vd 1002:4384) +Searching CBFS for prefix pci1002,4384.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:14.4 +Skipping non-normal pci device (type=81) +Attempting to init PCI bdf 00:14.5 (vd 1002:4399) +Searching CBFS for prefix pci1002,4399.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:14.5 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:16.0 (vd 1002:4397) +Searching CBFS for prefix pci1002,4397.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:16.0 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:16.2 (vd 1002:4396) +Searching CBFS for prefix pci1002,4396.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:16.2 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:18.0 (vd 1022:1200) +Searching CBFS for prefix pci1022,1200.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:18.0 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:18.1 (vd 1022:1201) +Searching CBFS for prefix pci1022,1201.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:18.1 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:18.2 (vd 1022:1202) +Searching CBFS for prefix pci1022,1202.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:18.2 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:18.3 (vd 1022:1203) +Searching CBFS for prefix pci1022,1203.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:18.3 +Option rom sizing returned 0 0 +Attempting to init PCI bdf 00:18.4 (vd 1022:1204) +Searching CBFS for prefix pci1022,1204.rom +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Attempting to map option rom on dev 00:18.4 +Option rom sizing returned 0 0 +Searching CBFS for prefix genroms/ +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +[wurm] boot_prep +[wurm] bp1 +enter handle_16: + a=00000100 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 + si=00000000 di=00000000 bp=00000000 sp=00006d44 cs=f000 ip=e984 f=0202 +Press F12 for boot menu. + +Searching CBFS for prefix etc/boot-menu-wait +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Checking for bootsplash +Searching CBFS for prefix bootsplash.jpg +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +Searching CBFS for prefix bootsplash.bmp +Found CBFS file cmos_layout.bin +Found CBFS file fallback/romstage +Found CBFS file fallback/coreboot_ram +Found CBFS file fallback/payload +Found CBFS file config +Found CBFS file +[wurm] bp2 +[wurm] bp3 +[wurm] bp4 +[wurm] bp5 +[wurm] cdemu_setup +[wurm] pmm_finalize +finalize PMM +[wurm] malloc_finalize +malloc finalize +Add to e820 map: 0009fc00 00000400 2 +Add to e820 map: cffd0000 00010000 1 +Returned 65536 bytes of ZoneHigh +[wurm] memmap_finalize +e820 map has 7 items: + 0: 0000000000000000 - 000000000009fc00 = 1 RAM + 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED + 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED + 3: 0000000000100000 - 00000000cffe0000 = 1 RAM + 4: 00000000cffe0000 - 00000000d0000000 = 2 RESERVED + 5: 00000000e0000000 - 00000000f0000000 = 2 RESERVED + 6: 0000000100000000 - 0000000220000000 = 1 RAM +[wurm] make_bios_readonly +[wurm] startBoot +Jump to int19 +enter handle_19: + NULL +Booting from Floppy... +enter handle_13: + a=00000201 b=00000000 c=00000001 d=00000000 ds=0000 es=07c0 ss=0000 + si=00000000 di=00000000 bp=00000000 sp=00006f20 cs=f000 ip=be62 f=0202 +invalid handle_legacy_disk:841: + a=00000201 b=00000000 c=00000001 d=00000000 ds=0000 es=07c0 ss=0000 + si=00000000 di=00000000 bp=00000000 sp=00006f20 cs=f000 ip=be62 f=0202 +Boot failed: could not read the boot disk + +enter handle_18: + NULL +Booting from Hard Disk... +enter handle_13: + a=00000201 b=00000000 c=00000001 d=00000080 ds=0000 es=07c0 ss=0000 + si=00000000 di=00000000 bp=00000000 sp=00006f20 cs=f000 ip=be62 f=0202 +invalid handle_legacy_disk:841: + a=00000201 b=00000000 c=00000001 d=00000080 ds=0000 es=07c0 ss=0000 + si=00000000 di=00000000 bp=00000000 sp=00006f20 cs=f000 ip=be62 f=0202 +Boot failed: could not read the boot disk + +enter handle_18: + NULL +No bootable device.