coreboot-4.0-2039-gd16b170-dirty Wed Feb 8 18:05:44 CET 2012 starting... BSP Family_Model: 00100fa0 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000 microcode: patch id to apply = 0x010000bf microcode: updated to patch id = 0x010000bf success POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 SB900 - Early.c - get_sbdn - Start. SB900 - Early.c - get_sbdn - End. cpuSetAMDPCI 00 done Prep FID/VID Node:00 P-state info in MSRC001_0064 is invalid !!! P-state info in MSRc0010064 is invalid !!! F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001016 F3xDC: 0000611a POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 POST: 0x37 started ap apicid: PPPPPOSOOOOSSTSSTTT:T:: ::0 00x00xxxx3333300000 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000024513 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000053142}}}}} --------------- * AmmiimmmPi cciiccc0rroorrr1occoocccooddooodeeddeee:: ::: ee qeeequuqqquuiiuviiivvaavvaallaellleenneennntt ttt rr rrreevveeevv v iiddiiidd d == == =0 00xx00xxx11001110aa00aaa00,,000,,, ccucccuurruurrrrrerrreenneennntt ttt pp pppaattaaattccthccch hhh ii diiidd dd == === 00 000xx00xxx00000000000000000000000000000000000 000 startmmemmmiiidiiccccc r rrrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff mmm*mmiiiii cAccccrrrPrrooooo cc0cccoooo2odddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss sccctccapppppuuruuuSSSStSeeeeeettdtttAAAA AM MMMMDDDDDMMMMMSSSSSRRRRR * AP dd0dddoooo3onnnnneeeee stiiiiinnnnnairiiiitttttte_____ffdfffiiii i dddddvvvvviiiiiddddd_____aaaaappppp(((((ssssstttttaaaaagggggeeeee11111))))) aaaaapppppiiiiiccccciiiiiddddd::::: 0000054123 FFFF*F IIIIIDDADDDVVVVVPI IIIIDDD0DD 4ooooonnnnn AAAAAPPPPP::::: 0000023541 started * AP 05started POST: 0x38 cimx/rd890 early.c nb_Poweron_Init() Start cimx/rd890 early.c nb_Poweron_Init() End. return status=0 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 POST: 0x39 FIDVID on BSP, APIC_id: 00 BSP fid = 0 Wait for AP stage 1: ap_apicid = 1 readback = 1000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2 readback = 2000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 3 readback = 3000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 4 readback = 4000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 5 readback = 5000001 common_fid(packed) = 0 common_fid = 0 POST: 0x3a End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 AmdHtInit status: 0 ...WARM RESET... coreboot-4.0-2039-gd16b170-dirty Wed Feb 8 18:05:44 CET 2012 starting... BSP Family_Model: 00100fa0 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000 microcode: patch id to apply = 0x010000bf microcode: updated to patch id = 0x010000bf success POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 SB900 - Early.c - get_sbdn - Start. SB900 - Early.c - get_sbdn - End. cpuSetAMDPCI 00 done Prep FID/VID Node:00 P-state info in MSRC001_0064 is invalid !!! P-state info in MSRc0010064 is invalid !!! F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001016 F3xDC: 0000611a POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 POST: 0x37 started ap apicid: PPPPPOOOOOSSSSSTTTTT::::: 00000xxxxx3333300000 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000025341 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000024315}}}}} --------------- * AmmmPmmiii ii0cccccrrrr1rooooocccccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000 startmmmmmediiiiicccc cr rrrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff mmmm*m iiiiiccccAcrPrrrrooooo cc0cccooooo2dddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss scctcccpppappruuuuuSSStSSeeeeeettttdtAA AAAMMMMM DDDDDMMMMMSSSSSRRRRR * AP dd0ddd3ooooonnnnneeeee siiiitniainnnniiiirttt_tttf____effdiffdiiii ddd vdivvvvdiiiiddd_d___s_stssstatttagaaaggggeeeee2222 2 a aapaappippciiiiicccciiiidddd:d::: : 0 003002 514 * AP 04started * AP 05started POST: 0x38 cimx/rd890 early.c nb_Poweron_Init() Start cimx/rd890 early.c nb_Poweron_Init() End. return status=0 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 POST: 0x39 POST: 0x3a End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 AmdHtInit status: 0 POST: 0x3b fill_mem_ctrl() POST: 0x40 raminit_amdmct() raminit_amdmct begin: SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=c DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=10 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=10 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 1000 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDGetTCL_D: DIMMCASL 4 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 1000 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: e00000 Node: 00 base: 03 limit: 21fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:e00000 CPUMemTyping: Bottom32bIO:e00000 CPUMemTyping: Bottom40bIO:2200000 mctAutoInitMCT_D: DQSTiming_D SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. TrainRcvrEn: Status 1100 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 1100 InterleaveNodes_D: ErrStatus 0 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 1100 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D All Done raminit_amdmct end: POST: 0x41 POST: 0x42 v_esp=000cbef8 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1310720 bytes), entry @ 0x200000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-4.0-2039-gd16b170-dirty Wed Feb 8 18:05:44 CET 2012 booting... POST: 0x40 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Mainboard ASUS M5A99X-EVO Enable. dev=0x00239e38 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=5 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled CPU: APIC: 04 enabled CPU: APIC: 05 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled POST: 0x25 PCI: Using configuration type 1 PCI: 00:00.0 [1002/5a14] ops PCI: 00:00.0 [1002/5a14] enabled Capability: type 0x08 @ 0xf0 flags: 0xa803 Capability: type 0x08 @ 0xf0 Capability: type 0x08 @ 0xc4 flags: 0x0281 PCI: pci_scan_bus for bus 00 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff PCI: pci_scan_bus upper limit too big. Using 0xff. POST: 0x24 PCI: 00:00.0 [1002/5a14] enabled PCI: 00:11.0 [1002/4393] enabled PCI: 00:12.0 [1002/4397] enabled PCI: 00:12.2 [1002/4396] enabled PCI: 00:13.0 [1002/4397] enabled PCI: 00:13.2 [1002/4396] enabled PCI: 00:14.0 [1002/4385] enabled PCI: 00:14.1 [1002/439c] enabled PCI: 00:14.2 [1002/4383] enabled PCI: 00:14.3 [1002/439d] enabled PCI: 00:14.4 [1002/4384] enabled PCI: 00:14.5 [1002/4399] enabled PCI: 00:16.0 [1002/4397] enabled PCI: 00:16.2 [1002/4396] enabled PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:14.4 PCI: pci_scan_bus for bus 01 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 do_pci_scan_bridge returns max 1 PCI: pci_scan_bus returning with max=001 POST: 0x55 PCI: pci_scan_bus returning with max=001 POST: 0x55 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done POST: 0x66 Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources APIC: 02 missing read_resources APIC: 03 missing read_resources APIC: 04 missing read_resources APIC: 05 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:14.4 read_resources bus 1 link: 0 PCI: 00:14.4 read_resources bus 1 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 PCI: 00:00.0 missing read_resources PCI: 00:02.0 missing read_resources PCI: 00:0d.0 missing read_resources PCI: 00:11.0 missing read_resources PCI: 00:12.0 missing read_resources PCI: 00:12.2 missing read_resources PCI: 00:13.0 missing read_resources PCI: 00:13.2 missing read_resources PCI: 00:14.0 missing read_resources PCI: 00:14.1 missing read_resources PCI: 00:14.2 missing read_resources PCI: 00:14.3 missing read_resources PCI: 00:14.5 missing read_resources PCI: 00:15.0 missing read_resources PCI: 00:15.1 missing read_resources PCI: 00:15.2 missing read_resources PCI: 00:15.3 missing read_resources PCI: 00:16.0 missing read_resources PCI: 00:16.2 missing read_resources PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI: 00:18.0 read_resources bus 0 link: 3 PCI: 00:18.0 read_resources bus 0 link: 3 done PCI: 00:18.0 read_resources bus 0 link: 4 PCI: 00:18.0 read_resources bus 0 link: 4 done PCI: 00:18.0 read_resources bus 0 link: 5 PCI: 00:18.0 read_resources bus 0 link: 5 done PCI: 00:18.0 read_resources bus 0 link: 6 PCI: 00:18.0 read_resources bus 0 link: 6 done PCI: 00:18.0 read_resources bus 0 link: 7 PCI: 00:18.0 read_resources bus 0 link: 7 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110a8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110a0 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 1200 index fc PCI: 00:11.0 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.3 PCI: 00:14.4 PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:02.0 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0d.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.2 PCI: 00:13.0 PCI: 00:13.2 PCI: 00:14.0 child on link 0 I2C: 00:50 I2C: 00:50 I2C: 00:51 I2C: 00:52 I2C: 00:53 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 child on link 0 PNP: 002e.0 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:14.4 PCI: 00:14.5 PCI: 00:14.6 PCI: 00:15.0 PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: 00:16.0 PCI: 00:16.2 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:11.0 20 * [0x0 - 0xf] io PCI: 00:14.1 20 * [0x10 - 0x1f] io PCI: 00:11.0 10 * [0x20 - 0x27] io PCI: 00:11.0 18 * [0x28 - 0x2f] io PCI: 00:14.1 10 * [0x30 - 0x37] io PCI: 00:14.1 18 * [0x38 - 0x3f] io PCI: 00:11.0 14 * [0x40 - 0x43] io PCI: 00:11.0 1c * [0x44 - 0x47] io PCI: 00:14.1 14 * [0x48 - 0x4b] io PCI: 00:14.1 1c * [0x4c - 0x4f] io PCI: 00:18.0 compute_resources_io: base: 50 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 10d8 * [0x0 - 0xfff] io PCI_DOMAIN: 0000 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.0 fc * [0x0 - 0xff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI: 00:14.2 10 * [0x4000000 - 0x4003fff] mem PCI: 00:12.0 10 * [0x4004000 - 0x4004fff] mem PCI: 00:13.0 10 * [0x4005000 - 0x4005fff] mem PCI: 00:14.5 10 * [0x4006000 - 0x4006fff] mem PCI: 00:16.0 10 * [0x4007000 - 0x4007fff] mem PCI: 00:11.0 24 * [0x4008000 - 0x40083ff] mem PCI: 00:12.2 10 * [0x4008400 - 0x40084ff] mem PCI: 00:13.2 10 * [0x4008500 - 0x40085ff] mem PCI: 00:16.2 10 * [0x4008600 - 0x40086ff] mem PCI: 00:18.0 compute_resources_mem: base: 4008700 size: 4100000 align: 26 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done PCI: 00:18.0 10b0 * [0x0 - 0x40fffff] mem PCI: 00:18.3 94 * [0x8000000 - 0xbffffff] mem PCI: 00:18.0 10b8 * [0xc000000 - 0xc0fffff] prefmem PCI_DOMAIN: 0000 compute_resources_mem: base: c100000 size: c100000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:11.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:12.2 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:13.2 constrain_resources: PCI: 00:14.0 constrain_resources: PCI: 00:14.1 constrain_resources: PCI: 00:14.2 constrain_resources: PCI: 00:14.3 constrain_resources: PCI: 00:14.4 constrain_resources: PCI: 00:14.5 constrain_resources: PCI: 00:16.0 constrain_resources: PCI: 00:16.2 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:0d.0 constrain_resources: PCI: 00:11.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:12.2 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:13.2 constrain_resources: PCI: 00:14.0 constrain_resources: I2C: 00:50 constrain_resources: I2C: 00:51 constrain_resources: I2C: 00:52 constrain_resources: I2C: 00:53 constrain_resources: PCI: 00:14.1 constrain_resources: PCI: 00:14.2 constrain_resources: PCI: 00:14.3 constrain_resources: PNP: 002e.2 skipping PNP: 002e.2@60 fixed resource, size=0! skipping PNP: 002e.2@70 fixed resource, size=0! constrain_resources: PNP: 002e.3 skipping PNP: 002e.3@60 fixed resource, size=0! skipping PNP: 002e.3@70 fixed resource, size=0! constrain_resources: PNP: 002e.5 skipping PNP: 002e.5@60 fixed resource, size=0! skipping PNP: 002e.5@62 fixed resource, size=0! skipping PNP: 002e.5@70 fixed resource, size=0! skipping PNP: 002e.5@72 fixed resource, size=0! constrain_resources: PNP: 002e.b skipping PNP: 002e.b@60 fixed resource, size=0! skipping PNP: 002e.b@70 fixed resource, size=0! constrain_resources: PCI: 00:14.5 constrain_resources: PCI: 00:15.0 constrain_resources: PCI: 00:15.1 constrain_resources: PCI: 00:15.2 constrain_resources: PCI: 00:15.3 constrain_resources: PCI: 00:16.0 constrain_resources: PCI: 00:16.2 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00000000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit dfffffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:0 size:1000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 10d8 * [0x0 - 0xfff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1000 size: 1000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:0 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 00:11.0 20 * [0x0 - 0xf] io Assigned: PCI: 00:14.1 20 * [0x10 - 0x1f] io Assigned: PCI: 00:11.0 10 * [0x20 - 0x27] io Assigned: PCI: 00:11.0 18 * [0x28 - 0x2f] io Assigned: PCI: 00:14.1 10 * [0x30 - 0x37] io Assigned: PCI: 00:14.1 18 * [0x38 - 0x3f] io Assigned: PCI: 00:11.0 14 * [0x40 - 0x43] io Assigned: PCI: 00:11.0 1c * [0x44 - 0x47] io Assigned: PCI: 00:14.1 14 * [0x48 - 0x4b] io Assigned: PCI: 00:14.1 1c * [0x4c - 0x4f] io PCI: 00:18.0 allocate_resources_io: next_base: 50 size: 1000 align: 12 gran: 12 done PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:18.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:18.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:c100000 align:26 gran:0 limit:dfffffff Assigned: PCI: 00:18.0 10b0 * [0xd0000000 - 0xd40fffff] mem Assigned: PCI: 00:18.3 94 * [0xd8000000 - 0xdbffffff] mem Assigned: PCI: 00:18.0 10b8 * [0xdc000000 - 0xdc0fffff] prefmem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: dc100000 size: c100000 align: 26 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:dc000000 size:100000 align:20 gran:20 limit:dfffffff Assigned: PCI: 00:00.0 fc * [0xdc000000 - 0xdc0000ff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: dc000100 size: 100000 align: 20 gran: 20 done PCI: 00:14.4 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:14.4 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:d0000000 size:4100000 align:26 gran:20 limit:dfffffff Assigned: PCI: 00:18.3 94 * [0xd0000000 - 0xd3ffffff] mem Assigned: PCI: 00:14.2 10 * [0xd4000000 - 0xd4003fff] mem Assigned: PCI: 00:12.0 10 * [0xd4004000 - 0xd4004fff] mem Assigned: PCI: 00:13.0 10 * [0xd4005000 - 0xd4005fff] mem Assigned: PCI: 00:14.5 10 * [0xd4006000 - 0xd4006fff] mem Assigned: PCI: 00:16.0 10 * [0xd4007000 - 0xd4007fff] mem Assigned: PCI: 00:11.0 24 * [0xd4008000 - 0xd40083ff] mem Assigned: PCI: 00:12.2 10 * [0xd4008400 - 0xd40084ff] mem Assigned: PCI: 00:13.2 10 * [0xd4008500 - 0xd40085ff] mem Assigned: PCI: 00:16.2 10 * [0xd4008600 - 0xd40086ff] mem PCI: 00:18.0 allocate_resources_mem: next_base: d4008700 size: 4100000 align: 26 gran: 20 done PCI: 00:14.4 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:14.4 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:18.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:18.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 split: 64K table at =cfff0000 0: mmio_basek=00340000, basek=00400000, limitk=00880000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:18.0 10d8 <- [0x0000000000 - 0x0000000fff] size 0x00001000 gran 0x0c io PCI: 00:18.0 10b8 <- [0x00dc000000 - 0x00dc0fffff] size 0x00100000 gran 0x14 prefmem PCI: 00:18.0 10b0 <- [0x00d0000000 - 0x00d40fffff] size 0x04100000 gran 0x14 mem PCI: 00:18.0 110d0 <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c io PCI: 00:18.0 110a8 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 prefmem PCI: 00:18.0 110a0 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:00.0 fc <- [0x00dc000000 - 0x00dc0000ff] size 0x00000100 gran 0x08 prefmem PCI: 00:11.0 10 <- [0x0000000020 - 0x0000000027] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000000040 - 0x0000000043] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000000028 - 0x000000002f] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000000044 - 0x0000000047] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000000000 - 0x000000000f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00d4008000 - 0x00d40083ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00d4004000 - 0x00d4004fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00d4008400 - 0x00d40084ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00d4005000 - 0x00d4005fff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00d4008500 - 0x00d40085ff] size 0x00000100 gran 0x08 mem PCI: 00:14.1 10 <- [0x0000000030 - 0x0000000037] size 0x00000008 gran 0x03 io PCI: 00:14.1 14 <- [0x0000000048 - 0x000000004b] size 0x00000004 gran 0x02 io PCI: 00:14.1 18 <- [0x0000000038 - 0x000000003f] size 0x00000008 gran 0x03 io PCI: 00:14.1 1c <- [0x000000004c - 0x000000004f] size 0x00000004 gran 0x02 io PCI: 00:14.1 20 <- [0x0000000010 - 0x000000001f] size 0x00000010 gran 0x04 io PCI: 00:14.2 10 <- [0x00d4000000 - 0x00d4003fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:14.4 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:14.4 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:14.5 10 <- [0x00d4006000 - 0x00d4006fff] size 0x00001000 gran 0x0c mem PCI: 00:16.0 10 <- [0x00d4007000 - 0x00d4007fff] size 0x00001000 gran 0x0c mem PCI: 00:16.2 10 <- [0x00d4008600 - 0x00d40086ff] size 0x00000100 gran 0x08 mem PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 1000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base d0000000 size c100000 align 26 gran 0 limit dfffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size cff40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base 100000000 size 120000000 align 0 gran 0 limit 0 flags e0004200 index 30 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 1000 align 12 gran 12 limit ffff flags 60080100 index 10d8 PCI: 00:18.0 resource base dc000000 size 100000 align 20 gran 20 limit dfffffff flags 60081200 index 10b8 PCI: 00:18.0 resource base d0000000 size 4100000 align 26 gran 20 limit dfffffff flags 60080200 index 10b0 PCI: 00:18.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080100 index 110d0 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081200 index 110a8 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080200 index 110a0 PCI: 00:00.0 PCI: 00:00.0 resource base dc000000 size 100 align 8 gran 8 limit dfffffff flags 60001200 index fc PCI: 00:11.0 PCI: 00:11.0 resource base 20 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:11.0 resource base 40 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:11.0 resource base 28 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:11.0 resource base 44 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:11.0 resource base d4008000 size 400 align 10 gran 10 limit dfffffff flags 60000200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base d4004000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base d4008400 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base d4005000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base d4008500 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.1 resource base 30 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:14.1 resource base 48 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:14.1 resource base 38 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:14.1 resource base 4c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:14.1 resource base 10 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base d4000000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 10 PCI: 00:14.3 PCI: 00:14.4 PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base d4006000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base d4007000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base d4008600 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base d0000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 PCI: 00:18.4 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:02.0 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0d.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.2 PCI: 00:13.0 PCI: 00:13.2 PCI: 00:14.0 child on link 0 I2C: 00:50 I2C: 00:50 I2C: 00:51 I2C: 00:52 I2C: 00:53 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 child on link 0 PNP: 002e.0 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:14.4 PCI: 00:14.5 PCI: 00:14.6 PCI: 00:15.0 PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: 00:16.0 PCI: 00:16.2 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base d8000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 PCI: 00:18.4 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/843e PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/843e PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1043/843e PCI: 00:18.4 cmd <- 00 PCI: 00:00.0 cmd <- 02 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 cmd <- 02 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 cmd <- 02 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 cmd <- 0f PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 cmd <- 02 PCI: 00:16.0 cmd <- 02 PCI: 00:16.2 cmd <- 02 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00006000, offset=0x00200000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 00 POST: 0x60 Enabling cache POST: 0x30 INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- Issuing SOFT_RESET... coreboot-4.0-2039-gd16b170-dirty Wed Feb 8 18:05:44 CET 2012 starting... BSP Family_Model: 00100fa0 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000 microcode: patch id to apply = 0x010000bf microcode: updated to patch id = 0x010000bf success POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 SB900 - Early.c - get_sbdn - Start. SB900 - Early.c - get_sbdn - End. cpuSetAMDPCI 00 done Prep FID/VID Node:00 P-state info in MSRC001_0064 is invalid !!! P-state info in MSRc0010064 is invalid !!! F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001016 F3xDC: 0000611a POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 POST: 0x37 started ap apicid: PPPPPOOOOOSSSSSTTTTT::::: 00000xxxxx3333300000 c cc oooccrororereerxxxee:xx:: :: - ------------ - -{ { { { { AA APAAPPPIIIPCICICICIICDDDII DD === == 000 1200534 NNNONOONDDODOEEDEDEIEIIIDIDDD D = === =00 000000 00 C CCCOOCOROROREERERIEIIEDDIDID D == = = = 0 00 250103}}4}} } -- ----------- -- * AmmmmmPiii ciircccc0rr1orrcoooooccccoooodddddeee:ee:: :: e eqeeeuqqqqiuuuuiiivivvvavaalaallelleneeentnnntttt rrrrereeveevv vv i idiii dddd ==== = 0 00x00x1xxx10111a00000aaaa0000,,, ,, c ccuccuruuurrrrrerrrrneeeennntnttt t p ppappataaatcttthcccchhhh iiiididdd d = == == 0 x00000xxxx00000000000000000000000000000000000 0000 startemmmmmiidiiiccccc rr rrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff mmmmm*i iiiiccccAcrPrrrrooooo cc0cccooooo2dddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss sctccccpppappruuuuuSSStSSeeeeeettttdtAA AAAMMMMM DDDDDMMMMMSSSSSRRRRR * AP 0 ddd3ddooooonnnnneeeee siiiiitnnainnntiiiirttt_ttf____efffdif diiiidddd vvivvvidiii_dddds____ssststttataagaaggegge2eee2 222a paaaapppipiiiciccicciidiid:ddd ::::0 000014253 * AP 04started * AP 05started POST: 0x38 cimx/rd890 early.c nb_Poweron_Init() Start cimx/rd890 early.c nb_Poweron_Init() End. return status=0 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 POST: 0x39 POST: 0x3a End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 AmdHtInit status: 0 POST: 0x3b fill_mem_ctrl() POST: 0x40 raminit_amdmct() raminit_amdmct begin: SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=c DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=10 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=10 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 1000 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDGetTCL_D: DIMMCASL 4 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 1000 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: e00000 Node: 00 base: 03 limit: 21fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:e00000 CPUMemTyping: Bottom32bIO:e00000 CPUMemTyping: Bottom40bIO:2200000 mctAutoInitMCT_D: DQSTiming_D SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. TrainRcvrEn: Status 1100 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 1100 InterleaveNodes_D: ErrStatus 0 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 1100 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D All Done raminit_amdmct end: POST: 0x41 POST: 0x42 v_esp=000cbef8 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1310720 bytes), entry @ 0x200000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-4.0-2039-gd16b170-dirty Wed Feb 8 18:05:44 CET 2012 booting... POST: 0x40 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Mainboard ASUS M5A99X-EVO Enable. dev=0x00239e38 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=5 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled CPU: APIC: 04 enabled CPU: APIC: 05 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled POST: 0x25 PCI: Using configuration type 1 PCI: 00:00.0 [1002/5a14] ops PCI: 00:00.0 [1002/5a14] enabled Capability: type 0x08 @ 0xf0 flags: 0xa803 Capability: type 0x08 @ 0xf0 Capability: type 0x08 @ 0xc4 flags: 0x0281 PCI: pci_scan_bus for bus 00 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff PCI: pci_scan_bus upper limit too big. Using 0xff. POST: 0x24 PCI: 00:00.0 [1002/5a14] enabled PCI: 00:11.0 [1002/4393] enabled PCI: 00:12.0 [1002/4397] enabled PCI: 00:12.2 [1002/4396] enabled PCI: 00:13.0 [1002/4397] enabled PCI: 00:13.2 [1002/4396] enabled PCI: 00:14.0 [1002/4385] enabled PCI: 00:14.1 [1002/439c] enabled PCI: 00:14.2 [1002/4383] enabled PCI: 00:14.3 [1002/439d] enabled PCI: 00:14.4 [1002/4384] enabled PCI: 00:14.5 [1002/4399] enabled PCI: 00:16.0 [1002/4397] enabled PCI: 00:16.2 [1002/4396] enabled PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:14.4 PCI: pci_scan_bus for bus 01 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 do_pci_scan_bridge returns max 1 PCI: pci_scan_bus returning with max=001 POST: 0x55 PCI: pci_scan_bus returning with max=001 POST: 0x55 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done POST: 0x66 Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources APIC: 02 missing read_resources APIC: 03 missing read_resources APIC: 04 missing read_resources APIC: 05 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:14.4 read_resources bus 1 link: 0 PCI: 00:14.4 read_resources bus 1 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 PCI: 00:00.0 missing read_resources PCI: 00:02.0 missing read_resources PCI: 00:0d.0 missing read_resources PCI: 00:11.0 missing read_resources PCI: 00:12.0 missing read_resources PCI: 00:12.2 missing read_resources PCI: 00:13.0 missing read_resources PCI: 00:13.2 missing read_resources PCI: 00:14.0 missing read_resources PCI: 00:14.1 missing read_resources PCI: 00:14.2 missing read_resources PCI: 00:14.3 missing read_resources PCI: 00:14.5 missing read_resources PCI: 00:15.0 missing read_resources PCI: 00:15.1 missing read_resources PCI: 00:15.2 missing read_resources PCI: 00:15.3 missing read_resources PCI: 00:16.0 missing read_resources PCI: 00:16.2 missing read_resources PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI: 00:18.0 read_resources bus 0 link: 3 PCI: 00:18.0 read_resources bus 0 link: 3 done PCI: 00:18.0 read_resources bus 0 link: 4 PCI: 00:18.0 read_resources bus 0 link: 4 done PCI: 00:18.0 read_resources bus 0 link: 5 PCI: 00:18.0 read_resources bus 0 link: 5 done PCI: 00:18.0 read_resources bus 0 link: 6 PCI: 00:18.0 read_resources bus 0 link: 6 done PCI: 00:18.0 read_resources bus 0 link: 7 PCI: 00:18.0 read_resources bus 0 link: 7 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110a8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110a0 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 1200 index fc PCI: 00:11.0 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.3 PCI: 00:14.4 PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:02.0 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0d.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.2 PCI: 00:13.0 PCI: 00:13.2 PCI: 00:14.0 child on link 0 I2C: 00:50 I2C: 00:50 I2C: 00:51 I2C: 00:52 I2C: 00:53 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 child on link 0 PNP: 002e.0 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:14.4 PCI: 00:14.5 PCI: 00:14.6 PCI: 00:15.0 PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: 00:16.0 PCI: 00:16.2 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:11.0 20 * [0x0 - 0xf] io PCI: 00:14.1 20 * [0x10 - 0x1f] io PCI: 00:11.0 10 * [0x20 - 0x27] io PCI: 00:11.0 18 * [0x28 - 0x2f] io PCI: 00:14.1 10 * [0x30 - 0x37] io PCI: 00:14.1 18 * [0x38 - 0x3f] io PCI: 00:11.0 14 * [0x40 - 0x43] io PCI: 00:11.0 1c * [0x44 - 0x47] io PCI: 00:14.1 14 * [0x48 - 0x4b] io PCI: 00:14.1 1c * [0x4c - 0x4f] io PCI: 00:18.0 compute_resources_io: base: 50 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 10d8 * [0x0 - 0xfff] io PCI_DOMAIN: 0000 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.0 fc * [0x0 - 0xff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI: 00:14.2 10 * [0x4000000 - 0x4003fff] mem PCI: 00:12.0 10 * [0x4004000 - 0x4004fff] mem PCI: 00:13.0 10 * [0x4005000 - 0x4005fff] mem PCI: 00:14.5 10 * [0x4006000 - 0x4006fff] mem PCI: 00:16.0 10 * [0x4007000 - 0x4007fff] mem PCI: 00:11.0 24 * [0x4008000 - 0x40083ff] mem PCI: 00:12.2 10 * [0x4008400 - 0x40084ff] mem PCI: 00:13.2 10 * [0x4008500 - 0x40085ff] mem PCI: 00:16.2 10 * [0x4008600 - 0x40086ff] mem PCI: 00:18.0 compute_resources_mem: base: 4008700 size: 4100000 align: 26 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done PCI: 00:18.0 10b0 * [0x0 - 0x40fffff] mem PCI: 00:18.3 94 * [0x8000000 - 0xbffffff] mem PCI: 00:18.0 10b8 * [0xc000000 - 0xc0fffff] prefmem PCI_DOMAIN: 0000 compute_resources_mem: base: c100000 size: c100000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:11.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:12.2 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:13.2 constrain_resources: PCI: 00:14.0 constrain_resources: PCI: 00:14.1 constrain_resources: PCI: 00:14.2 constrain_resources: PCI: 00:14.3 constrain_resources: PCI: 00:14.4 constrain_resources: PCI: 00:14.5 constrain_resources: PCI: 00:16.0 constrain_resources: PCI: 00:16.2 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:0d.0 constrain_resources: PCI: 00:11.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:12.2 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:13.2 constrain_resources: PCI: 00:14.0 constrain_resources: I2C: 00:50 constrain_resources: I2C: 00:51 constrain_resources: I2C: 00:52 constrain_resources: I2C: 00:53 constrain_resources: PCI: 00:14.1 constrain_resources: PCI: 00:14.2 constrain_resources: PCI: 00:14.3 constrain_resources: PNP: 002e.2 skipping PNP: 002e.2@60 fixed resource, size=0! skipping PNP: 002e.2@70 fixed resource, size=0! constrain_resources: PNP: 002e.3 skipping PNP: 002e.3@60 fixed resource, size=0! skipping PNP: 002e.3@70 fixed resource, size=0! constrain_resources: PNP: 002e.5 skipping PNP: 002e.5@60 fixed resource, size=0! skipping PNP: 002e.5@62 fixed resource, size=0! skipping PNP: 002e.5@70 fixed resource, size=0! skipping PNP: 002e.5@72 fixed resource, size=0! constrain_resources: PNP: 002e.b skipping PNP: 002e.b@60 fixed resource, size=0! skipping PNP: 002e.b@70 fixed resource, size=0! constrain_resources: PCI: 00:14.5 constrain_resources: PCI: 00:15.0 constrain_resources: PCI: 00:15.1 constrain_resources: PCI: 00:15.2 constrain_resources: PCI: 00:15.3 constrain_resources: PCI: 00:16.0 constrain_resources: PCI: 00:16.2 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00000000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit dfffffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:0 size:1000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 10d8 * [0x0 - 0xfff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1000 size: 1000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:0 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 00:11.0 20 * [0x0 - 0xf] io Assigned: PCI: 00:14.1 20 * [0x10 - 0x1f] io Assigned: PCI: 00:11.0 10 * [0x20 - 0x27] io Assigned: PCI: 00:11.0 18 * [0x28 - 0x2f] io Assigned: PCI: 00:14.1 10 * [0x30 - 0x37] io Assigned: PCI: 00:14.1 18 * [0x38 - 0x3f] io Assigned: PCI: 00:11.0 14 * [0x40 - 0x43] io Assigned: PCI: 00:11.0 1c * [0x44 - 0x47] io Assigned: PCI: 00:14.1 14 * [0x48 - 0x4b] io Assigned: PCI: 00:14.1 1c * [0x4c - 0x4f] io PCI: 00:18.0 allocate_resources_io: next_base: 50 size: 1000 align: 12 gran: 12 done PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:18.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:18.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:c100000 align:26 gran:0 limit:dfffffff Assigned: PCI: 00:18.0 10b0 * [0xd0000000 - 0xd40fffff] mem Assigned: PCI: 00:18.3 94 * [0xd8000000 - 0xdbffffff] mem Assigned: PCI: 00:18.0 10b8 * [0xdc000000 - 0xdc0fffff] prefmem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: dc100000 size: c100000 align: 26 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:dc000000 size:100000 align:20 gran:20 limit:dfffffff Assigned: PCI: 00:00.0 fc * [0xdc000000 - 0xdc0000ff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: dc000100 size: 100000 align: 20 gran: 20 done PCI: 00:14.4 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:14.4 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:d0000000 size:4100000 align:26 gran:20 limit:dfffffff Assigned: PCI: 00:18.3 94 * [0xd0000000 - 0xd3ffffff] mem Assigned: PCI: 00:14.2 10 * [0xd4000000 - 0xd4003fff] mem Assigned: PCI: 00:12.0 10 * [0xd4004000 - 0xd4004fff] mem Assigned: PCI: 00:13.0 10 * [0xd4005000 - 0xd4005fff] mem Assigned: PCI: 00:14.5 10 * [0xd4006000 - 0xd4006fff] mem Assigned: PCI: 00:16.0 10 * [0xd4007000 - 0xd4007fff] mem Assigned: PCI: 00:11.0 24 * [0xd4008000 - 0xd40083ff] mem Assigned: PCI: 00:12.2 10 * [0xd4008400 - 0xd40084ff] mem Assigned: PCI: 00:13.2 10 * [0xd4008500 - 0xd40085ff] mem Assigned: PCI: 00:16.2 10 * [0xd4008600 - 0xd40086ff] mem PCI: 00:18.0 allocate_resources_mem: next_base: d4008700 size: 4100000 align: 26 gran: 20 done PCI: 00:14.4 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:14.4 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:18.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:18.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 split: 64K table at =cfff0000 0: mmio_basek=00340000, basek=00400000, limitk=00880000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:18.0 10d8 <- [0x0000000000 - 0x0000000fff] size 0x00001000 gran 0x0c io PCI: 00:18.0 10b8 <- [0x00dc000000 - 0x00dc0fffff] size 0x00100000 gran 0x14 prefmem PCI: 00:18.0 10b0 <- [0x00d0000000 - 0x00d40fffff] size 0x04100000 gran 0x14 mem PCI: 00:18.0 110d0 <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c io PCI: 00:18.0 110a8 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 prefmem PCI: 00:18.0 110a0 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:00.0 fc <- [0x00dc000000 - 0x00dc0000ff] size 0x00000100 gran 0x08 prefmem PCI: 00:11.0 10 <- [0x0000000020 - 0x0000000027] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000000040 - 0x0000000043] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000000028 - 0x000000002f] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000000044 - 0x0000000047] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000000000 - 0x000000000f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00d4008000 - 0x00d40083ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00d4004000 - 0x00d4004fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00d4008400 - 0x00d40084ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00d4005000 - 0x00d4005fff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00d4008500 - 0x00d40085ff] size 0x00000100 gran 0x08 mem PCI: 00:14.1 10 <- [0x0000000030 - 0x0000000037] size 0x00000008 gran 0x03 io PCI: 00:14.1 14 <- [0x0000000048 - 0x000000004b] size 0x00000004 gran 0x02 io PCI: 00:14.1 18 <- [0x0000000038 - 0x000000003f] size 0x00000008 gran 0x03 io PCI: 00:14.1 1c <- [0x000000004c - 0x000000004f] size 0x00000004 gran 0x02 io PCI: 00:14.1 20 <- [0x0000000010 - 0x000000001f] size 0x00000010 gran 0x04 io PCI: 00:14.2 10 <- [0x00d4000000 - 0x00d4003fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:14.4 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:14.4 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:14.5 10 <- [0x00d4006000 - 0x00d4006fff] size 0x00001000 gran 0x0c mem PCI: 00:16.0 10 <- [0x00d4007000 - 0x00d4007fff] size 0x00001000 gran 0x0c mem PCI: 00:16.2 10 <- [0x00d4008600 - 0x00d40086ff] size 0x00000100 gran 0x08 mem PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 1000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base d0000000 size c100000 align 26 gran 0 limit dfffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size cff40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base 100000000 size 120000000 align 0 gran 0 limit 0 flags e0004200 index 30 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 1000 align 12 gran 12 limit ffff flags 60080100 index 10d8 PCI: 00:18.0 resource base dc000000 size 100000 align 20 gran 20 limit dfffffff flags 60081200 index 10b8 PCI: 00:18.0 resource base d0000000 size 4100000 align 26 gran 20 limit dfffffff flags 60080200 index 10b0 PCI: 00:18.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080100 index 110d0 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081200 index 110a8 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080200 index 110a0 PCI: 00:00.0 PCI: 00:00.0 resource base dc000000 size 100 align 8 gran 8 limit dfffffff flags 60001200 index fc PCI: 00:11.0 PCI: 00:11.0 resource base 20 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:11.0 resource base 40 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:11.0 resource base 28 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:11.0 resource base 44 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:11.0 resource base d4008000 size 400 align 10 gran 10 limit dfffffff flags 60000200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base d4004000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base d4008400 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base d4005000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base d4008500 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.1 resource base 30 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:14.1 resource base 48 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:14.1 resource base 38 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:14.1 resource base 4c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:14.1 resource base 10 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base d4000000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 10 PCI: 00:14.3 PCI: 00:14.4 PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base d4006000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base d4007000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base d4008600 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base d0000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 PCI: 00:18.4 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:02.0 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0d.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.2 PCI: 00:13.0 PCI: 00:13.2 PCI: 00:14.0 child on link 0 I2C: 00:50 I2C: 00:50 I2C: 00:51 I2C: 00:52 I2C: 00:53 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 child on link 0 PNP: 002e.0 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:14.4 PCI: 00:14.5 PCI: 00:14.6 PCI: 00:15.0 PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: 00:16.0 PCI: 00:16.2 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base d8000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 PCI: 00:18.4 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/843e PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/843e PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1043/843e PCI: 00:18.4 cmd <- 00 PCI: 00:00.0 cmd <- 02 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 cmd <- 02 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 cmd <- 02 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 cmd <- 0f PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 cmd <- 02 PCI: 00:16.0 cmd <- 02 PCI: 00:16.2 cmd <- 02 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00006000, offset=0x00200000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 00 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #0 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 1. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #1 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 01 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x01 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #1 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 2. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #2 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 02 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x02 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #2 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 3. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #3 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 03 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x03 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #3 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 4. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #4 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 04 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x04 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #4 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 5. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #5 Waiting for 1 CPUS to stop CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 05 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x05 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #5 initialized All AP CPUs stopped SB900 - Early.c - sb_After_Pci_Init - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_After_Pci_Init - End. SB900 - Early.c - sb_Mid_Post_Init - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_Mid_Post_Init - End. PCI: 00:18.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init PCI: 00:00.0 init IOAPIC: Initializing IOAPIC at 0xdc000000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x01 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC not responding. PCI: 00:11.0 init PCI: 00:12.0 init PCI: 00:12.2 init PCI: 00:13.0 init PCI: 00:13.2 init PCI: 00:14.0 init PCI: 00:14.1 init PCI: 00:14.2 init PCI: 00:14.3 init PCI: 00:14.5 init PCI: 00:16.0 init PCI: 00:16.2 init PCI: 00:18.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 APIC: 01: enabled 1 APIC: 02: enabled 1 APIC: 03: enabled 1 APIC: 04: enabled 1 APIC: 05: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 POST: 0x89 Initializing CBMEM area to 0xcfff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to cfff0200...ok High Tables Base is cfff0000. POST: 0x9a SB900 - Early.c - sb_Late_Post - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_Late_Post - End. Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done. Adding CBMEM entry as no. 2 Writing IRQ routing tables to 0xcfff0400...write_pirq_routing_table done. PIRQ table: 48 bytes. POST: 0x9b Wrote the mp table end at: 000f0410 - 000f055c Adding CBMEM entry as no. 3 Wrote the mp table end at: cfff1410 - cfff155c MP table: 348 bytes. POST: 0x9c Adding CBMEM entry as no. 4 ACPI: Writing ACPI tables at cfff2400... ACPI: * HPET at cfff24c8 ACPI: added table 1/32, length now 40 ACPI: * MADT at cfff2500 ACPI: added table 2/32, length now 44 ACPI: * SRAT at cfff2580 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=0033fd00 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00480000 ACPI: added table 3/32, length now 48 ACPI: * SLIT at cfff2688 ACPI: added table 4/32, length now 52 ACPI: * SSDT at cfff26c0 ACPI: added table 5/32, length now 56 ACPI: * SSDT for PState at cfff2cf5 ACPI: * DSDT at cfff2cf8 ACPI: * DSDT @ cfff2cf8 Length 288b ACPI: * FACS at cfff5588 ACPI: * FADT at cfff55c8 ACPI_BLK_BASE: 0x0800 ACPI: added table 6/32, length now 60 ACPI: done. ACPI tables: 12988 bytes. Adding CBMEM entry as no. 5 smbios_write_tables: cfffd800 Root Device (ASUS M5A99X-EVO Mainboard) APIC_CLUSTER: 0 (AMD FAM10 Root Complex) APIC: 00 (socket AM3) PCI_DOMAIN: 0000 (AMD FAM10 Root Complex) PCI: 00:18.0 (AMD FAM10 Northbridge) PCI: 00:00.0 (ATI rd890) PCI: 00:00.1 (ATI rd890) PCI: 00:02.0 (ATI rd890) PCI: 00:03.0 (ATI rd890) PCI: 00:04.0 (ATI rd890) PCI: 00:05.0 (ATI rd890) PCI: 00:06.0 (ATI rd890) PCI: 00:07.0 (ATI rd890) PCI: 00:08.0 (ATI rd890) PCI: 00:09.0 (ATI rd890) PCI: 00:0a.0 (ATI rd890) PCI: 00:0b.0 (ATI rd890) PCI: 00:0c.0 (ATI rd890) PCI: 00:0d.0 (ATI rd890) PCI: 00:11.0 (ATI SB900) PCI: 00:12.0 (ATI SB900) PCI: 00:12.2 (ATI SB900) PCI: 00:13.0 (ATI SB900) PCI: 00:13.2 (ATI SB900) PCI: 00:14.0 (ATI SB900) I2C: 00:50 () I2C: 00:51 () I2C: 00:52 () I2C: 00:53 () PCI: 00:14.1 (ATI SB900) PCI: 00:14.2 (ATI SB900) PCI: 00:14.3 (ATI SB900) PNP: 002e.0 (ITE IT8721F Super I/O) PNP: 002e.1 (ITE IT8721F Super I/O) PNP: 002e.2 (ITE IT8721F Super I/O) PNP: 002e.3 (ITE IT8721F Super I/O) PNP: 002e.5 (ITE IT8721F Super I/O) PNP: 002e.6 (ITE IT8721F Super I/O) PNP: 002e.7 (ITE IT8721F Super I/O) PNP: 002e.8 (ITE IT8721F Super I/O) PNP: 002e.9 (ITE IT8721F Super I/O) PNP: 002e.a (ITE IT8721F Super I/O) PNP: 002e.b (ITE IT8721F Super I/O) PCI: 00:14.4 (ATI SB900) PCI: 00:14.5 (ATI SB900) PCI: 00:14.6 (ATI SB900) PCI: 00:15.0 (ATI SB900) PCI: 00:15.1 (ATI SB900) PCI: 00:15.2 (ATI SB900) PCI: 00:15.3 (ATI SB900) PCI: 00:16.0 (ATI SB900) PCI: 00:16.2 (ATI SB900) PCI: 00:18.1 (AMD FAM10 Northbridge) PCI: 00:18.2 (AMD FAM10 Northbridge) PCI: 00:18.3 (AMD FAM10 Northbridge) PCI: 00:18.4 (AMD FAM10 Northbridge) APIC: 01 () APIC: 02 () APIC: 03 () APIC: 04 () APIC: 05 () PCI: 00:00.0 () PCI: 00:11.0 () PCI: 00:12.0 () PCI: 00:12.2 () PCI: 00:13.0 () PCI: 00:13.2 () PCI: 00:14.0 () PCI: 00:14.1 () PCI: 00:14.2 () PCI: 00:14.3 () PCI: 00:14.4 () PCI: 00:14.5 () PCI: 00:16.0 () PCI: 00:16.2 () PCI: 00:18.0 () PCI: 00:18.1 () PCI: 00:18.2 () PCI: 00:18.3 () PCI: 00:18.4 () SMBIOS tables: 275 bytes. POST: 0x9d Adding CBMEM entry as no. 6 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 4fde New low_table_end: 0x00000518 Now going to write high coreboot table at 0xcfffe000 rom_table_end = 0xcfffe000 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0xcfffe000 to 0xd0000000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-00000000cffeffff: RAM 3. 00000000cfff0000-00000000cfffffff: CONFIGURATION TABLES 4. 00000000e0000000-00000000efffffff: RESERVED 5. 0000000100000000-000000021fffffff: RAM Wrote coreboot table at: cfffe000 - cfffe1e4 checksum 684b coreboot table: 484 bytes. POST: 0x9e POST: 0x9d Multiboot Information structure has been written. 0. FREE SPACE d0000000 00000000 1. GDT cfff0200 00000200 2. IRQ TABLE cfff0400 00001000 3. SMP TABLE cfff1400 00001000 4. ACPI cfff2400 0000b400 5. SMBIOS cfffd800 00000800 6. COREBOOT cfffe000 00002000 Searching for fallback/payload Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Got a payload Loading segment from rom address 0xffc43ef8 data (compression=1) New segment dstaddr 0xed150 memsize 0x12eb0 srcaddr 0xffc43f30 filesize 0x9759 (cleaned up) New segment addr 0xed150 size 0x12eb0 offset 0xffc43f30 filesize 0x9759 Loading segment from rom address 0xffc43f14 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000ed150 memsz: 0x0000000000012eb0 filesz: 0x0000000000009759 lb: [0x0000000000200000, 0x0000000000340000) Post relocation: addr: 0x00000000000ed150 memsz: 0x0000000000012eb0 filesz: 0x0000000000009759 using LZMA [ 0x000ed150, 00100000, 0x00100000) <- ffc43f30 dest 000ed150, end 00100000, bouncebuffer cfd70000 Loaded segments Jumping to boot code at fc63c POST: 0xf8 entry = 0x000fc63c lb_start = 0x00200000 lb_size = 0x00140000 adjust = 0xcfcb0000 buffer = 0xcfd70000 elf_boot_notes = 0x0023b1d0 adjusted_boot_notes = 0xcfeeb1d0 Start bios (version 1.6.3-20120208_175037-oldx86) Find memory size Attempting to find coreboot table Found coreboot table forwarder. Now attempting to find coreboot memory map Add to e820 map: 00000000 00001000 2 Add to e820 map: 00001000 0009f000 1 Add to e820 map: 000c0000 cff30000 1 Add to e820 map: cfff0000 00010000 2 Add to e820 map: e0000000 10000000 2 Add to e820 map: 00000000 20000000 1 Add to e820 map: 00000000 00004000 1 Found mainboard ASUS M5A99X-EVO Found CBFS header at 0xfffffca0 Add to e820 map: 000a0000 00050000 -1 Add to e820 map: 000f0000 00010000 2 Ram Size=0xcfff0000 (0x0000000120000000 high) malloc setup Add to e820 map: cffe0000 00010000 2 init ivt init bda Add to e820 map: 0009fc00 00000400 2 init pic init timer init timer: 01 init timer: 02 init timer: 03 init timer: 04 init timer: 05 init timer: 06 init timer: 07 init timer: 08 init timer: 09 init timer: 10 init timer: 11 init timer: 12 math cp init PCI probe Searching CBFS for prefix etc/extra-pci-roots Found CBFS file cmos_layout.bin Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file config Found CBFS file pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfe70 (detail=0xcffdfee0) PCI device 00:00.0 (vd=1002:5a14 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfdd0 (detail=0xcffdfe40) PCI device 00:11.0 (vd=1002:4393 c=0101) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfd30 (detail=0xcffdfda0) PCI device 00:12.0 (vd=1002:4397 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfc90 (detail=0xcffdfd00) PCI device 00:12.2 (vd=1002:4396 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfbf0 (detail=0xcffdfc60) PCI device 00:13.0 (vd=1002:4397 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfb50 (detail=0xcffdfbc0) PCI device 00:13.2 (vd=1002:4396 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfab0 (detail=0xcffdfb20) PCI device 00:14.0 (vd=1002:4385 c=0c05) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfa10 (detail=0xcffdfa80) PCI device 00:14.1 (vd=1002:439c c=0101) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf970 (detail=0xcffdf9e0) PCI device 00:14.2 (vd=1002:4383 c=0403) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf8d0 (detail=0xcffdf940) PCI device 00:14.3 (vd=1002:439d c=0601) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf830 (detail=0xcffdf8a0) PCI device 00:14.4 (vd=1002:4384 c=0604) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf790 (detail=0xcffdf800) PCI device 00:14.5 (vd=1002:4399 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf6f0 (detail=0xcffdf760) PCI device 00:16.0 (vd=1002:4397 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf650 (detail=0xcffdf6c0) PCI device 00:16.2 (vd=1002:4396 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf5b0 (detail=0xcffdf620) PCI device 00:18.0 (vd=1022:1200 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf510 (detail=0xcffdf580) PCI device 00:18.1 (vd=1022:1201 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf470 (detail=0xcffdf4e0) PCI device 00:18.2 (vd=1022:1202 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf3d0 (detail=0xcffdf440) PCI device 00:18.3 (vd=1022:1203 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf330 (detail=0xcffdf3a0) PCI device 00:18.4 (vd=1022:1204 c=0600) Found 19 PCI devices (max PCI bus is 01) Searching CBFS for prefix bootorder Found CBFS file cmos_layout.bin Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file config Found CBFS file Found 1 cpu(s) max supported 1 cpu(s) init bios32 hhhhheandlwpi_h1 irc0rqq=fde=c0=0q= init PMM init PNPBIOS table init keybhahhaandrehh_dll eandwpi_ h irc1=0cq1rq= ideicf=0qrq000=ffd6 c init mouse Relocating coreboot bios tablehhshhhdan dle anpi_hw1 irc0rqq=cfde= pmm_malloc zone=0x000f6754 handle=fffffhffhhahandhfle andswpi_h iric10zc1q=rq= ei=f=00qf0e004 82 align=10 ret=0x000fdbc0hah (anhdhldndlaehwte_ac1pi irqirql=0==f=000000e0x=fc03c0fh=hhh‰nfandda‰fe_‰lw‰p3hc01i‰ir‰ 0=‰0)qh=hh n a‰hn‰da‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰hwp‰c1‰i‰r i‰q=0hhhhand‰le_‰wp‰h‰1ic ir‰h0q=ahhhand‰le_‰wp‰h‰1ic‰ irq=0‰fhq=hahh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰andle_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰andle_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰andle_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1 ‰ir=0q‰h0=fahhhan‰dle‰_‰phw‰ic1 ir‰0hq=hahh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰l W0AfdRNbcIN0 G - hhTanimdlee_wohipuc1t i rqat=0 =f0p0a0s2524 _ rehacnvdblyte_e:hw1pðic! 1 hiarnqdl=0e _ hwpic1 hiarnq=dl0 e_ hwpihcpanlmd_emhw_pimc1al ilrq0o= c zhaonndel=0e_x0hw0p0ifc671 54ir qh=a0nd le=fhfafnffdlffe_fh wspizice=1 3i4r8q =a0li ghn=an1d0l er_eht=wp0ixc010 0ifdrqa=600 (detahialn=0dlxce_fhfwdpfi2cd01 )i r q=0 h andl_ewhpic1 irq=c82=8a6f8 hanhdlanehad_nlhdewl_piehwc_p1hwi pcii1rc q=1ir0 q ir= q0= 0 hCaonpydlien_gh wMpPTicA1B LiEr qfr=0o m 0xcfffh1a4n00dl/ce_fhfwfp14ic101 itroq 0=0x0 0h0fanddal6e0 _h wpic1 irqhh=aanlnded_whlepi_c1h iwrq0p= ic 1ha indrql=e_0 hw pic1 irhhqaanlnded_whlepi_c1h iwrq0p= ic 1ha indrql=e_0 hw pic1 irhhqaanndl_dewhlepi_c1h iwrq0p= ic 1ha inrdql=e_0 hw pic1 irhhqaanndl_dewhlepi_c1h iwrq0p= ic 1ha indrql=e_0 hw pic1 irhhqaanndl_dewhlepi_c1h iwrqp=0fi=00c10f 25i4 r qh=a0nd le_hwhapnicdl1 e_irhwqp=0ic 1h ianrqdl=0e _h wpic1h anirdlq=e_0h w phiacn1dl ie_rqh=w0p ic 1 irhq=an0 dl eha_hndwplie_c1hw ipirqc=1 0 ir q=0 handlhenhadal_endhwlpiec1_ iqhr0=w pi cha1 nidrlqe=_0hw pic1h ainrdqhl=ane0 d_h lwe_pihcwp1 icir1 q=i0rq =0 hhaannddllee__hhwwppiicc11 iirrqq==00 hphhaamnhdnmed_lamhn_lpeawdlcli_e hl1wor_iqh=pc=i 0wz0pcci81o0nc e1 i hr=aq0i=xrn0qd00=l 0e 0 _f h67wp5i4 c1ha indrql=e=0 ff ffffhffha andsndlileze_e_h=2hw0wpi picac1l1 i ignir=rq=1q=000 r et=h0axn00dl0ef_dhaw4p0 ic(1d eitraqil=0= 0 xcffdf2haha0)and ndl lee__hhwpwpiicc11 iirqrq==00 Cohhhaanhplaydni_denlwdnhgiepl_1e c_Aih rwqhC0wP=pIi pc i hcR11S aDin Prdiqlr =eqf0_=rh0o m w p 0icxc1 ffirfq24=000 to 0x0h0a0fnddale4_0h w pich1a nirdlqe=_0h w pihc1hananddl_lehewp_ich1i wprqi=0fc=0100 afif=3rqf0=00f0f5 3 hapmnhmda_lenm_dalhllwe_ophciw c1pzo inicer1 =qi0=rx0 q00 =00 f6 75h4a nhhdanaldne_ldlheew=_pfhiffwc1fp ficif1rf qfi= sr0 iq z=0e =3 1 alighna=n10dl er_ehtw=p0xic010 0ifrdqa2=00 (detailh=a0nxhdcalfnefdd_hflw2ep7_hi0wc)p1 i ic1r q=ir0 q= 0 Chhohaahpnaylnded_niwdnhlieplg1e c_Sih _wqhMrwB0p= ipIciO cSh1 a 1eni drinqrtlqre==y_00 h pw op iinct1 ifrroqm= 00 x cfffd80hah0na tdndoll ee0__xhwh00pw0ipifccd11a 2iri0 qr =q=00 hhShaacndnhedaalnh_lnped wlfci_1 heow_rir q=ph=iwV0G0ccp81iA0c o i1hr paqit=rinqod0nl = e 0_ roh mwp ic1 irqh=anSedlae_rhwcpi1hc iiqrng=0 =fC00B0f5F2=3Sf0 f00offr53 prheanfidlx ee_thcwp/oicpt1i oinrqro=0ms - chehckanshdualmne dl_ ehw_hpiwcp1i c1ir iq=rq0 = 0 Fhoaunnddl eC_BhFwSp fici1l ei rcqm=o0s _l ayhouantd.lbein_h w pich1a nidrlq=e_0h w pic1h andl_ewhip1c irq=0f=00f0ff4 handlhenahdl_aehnwpdicl1i e_rq0h= w phiacn1 dlire_qh=w0p i c1F oiurnq=d 0C B FS fhilhaeand nlfdleae_l_hlhwbwpapickic/c1r1 io rmirqsq=t=0a0 g e hhhnFaadonhlda_euhwnlnedpidc1 _lChe i_rqBw0Fph=iw Sp chf1ii cai1nlr deil qef=r_a0ql =h 0wl pb iacc1k /ciroqre=0b o ot_ram handleha_nhdwlpei_c1hw piircq1= 0 ir qha=0n d le_hwpic1ha indrqle=0_ hw hpaicnd1 leir_hqw=0pi c1 irq=0 hh aanndl_dewhlepi_c1h iwrqcp=6if=8c1a6 f8i r hq=a0n d le_hwphiacn1hd alirne_qdh=lw0e_p hi wc1pi ic1r q=ir0 q= 0 hhhaFanlnohdua_edhwlnneddpilc1_ ihCe B_qrw=0pFhSw=fi00c p1fi0fc25 i il14e rhq ia=fr0aqnl=d 0l leb _a hckwp/ipac1yl ioradq= 0 hhhaFanodlnhdaue_nhwlnieddpl 1c_ iheCw_BrqF=0phfiwS= 00cpf1if0ciff 4 i1lr e hqia=rcn0qo =nd0fl ie g_ hw piFco1 unird q=CB0F S hfanildle e _ hwpic1 irqhS=aenldae_rchwihpci1 nirgq0= CB FhaS ndfolre _phwrepificx1 eirtcq=/s03 - rehsauhnmead-nlevdl_geha_w-hpinwiipc1tic 1i riqr=q0= 0 hhhaSnaehlnded_aawrnhliepcd1hlc_eih iwqn_rgh0p= i wcCp Bih1ca FniS1dr qfilore=rq_0 =h 0w p pr iefci1 x iretq=c/0s crehehan-andandlnlede_-_hdehwbwpiupicgc1 1 irirqq==00 hhhanFalndho_auednwlhniddpe 1_clhieC _Bqwr=p0hFfwS=i 0c0p1fif0if fci 1l4 er qhi =arcnqm0=o ds l0e __ lahwypouict1.b iinrq = 0 hahnadnldel_hSe_wehpawircpchi1ic in1 rgiq r=CBq0F= S0 forh haprandendlfleie_x_h vhwgwpiapicrc1o1 m is/ir rq= q=00 hhhFaanlhodnu_dealwnnhddiepc_1l ieC hqwr_B0hF=pSi wc p hif1aci 1linerd qli =erc0_qmh=o 0s w_p li ac1y ouirt.q=b0in hhhnFaahdoln_daeunwnhldiedp_l1 c Ciheqw_rBh0F=pSiw cp ihf1ai cli1ner dqil =refq_a0hl =l 0w pb iacc1k /riroqm=s0ta ge hhhFananodlhe_adulnhwnpidedl_ c1C iehq_wBrpF0=h wiSpc 1fhiiac n1ild reiq lr=fe0a_qlh= w0 l bpi acck1/ ciorrqe=b0 oo t_ram ha hndanledl_ehw_hpiwpc1ic 1ir iq=rq0 =0 hhandiaehnnlidh_awpntld eic_1 lureshibw=q_0qh p i=cw08pc0 i1 c 1iha rniqdr=0lq e= _0 hw pic1h ianrdql=e0 _h whapindc1l ei_rhwq=pi0 c1 irq=0 h andl_ewhpic1 irq=c82=86ac8 hanhpdamlenm__dlmheaw_lphliwoc1pc iczi1or nqie=0r= q0x =00 00 f6h75an8had nlhdeal_ndehwl_pehwi=pcfi1fc ff1irf qfir=fq0f= 0 si ze=7h2a naldlieg_nh=w1p0 icr1e ti=r0qxc=0ff df1f0 (hdaentdahalineld_=0lhxewpc_ifhwcfp1di f2cir41q0 =)ir0 q = 0 EhhHhahCnaIdlna_dn ediwhlpielneic1_ ih_twh rqo=0pwfipn=i 00c0f1cd 1e254 i vri 0hqra=q0n0=:d 01 2l .e2_h (wpreicgs1= i0xrqd4=000 8 420) hahndpanlmmde_l_meha_wplhilwpcoci1 c z1io rqni=erq0=0= x0 0 0 0f675h8a nhadlnde_lhew=pfficff1 fifrfqf =0si ze=4h09an6 dlael_ihgnwp=1ic010 0i rrqet=0= 0 xcffdhheaa00nn0ddl lee(__dhhewwtappiiiclc11= 0iixrrcfqqf==0d0 f 1c0) hh aannddllee__hhwwppiicc11 iirrqq==00 /chhhhfanalnafdnd_edhwldeel0pi0c1_eih_0 h\qrw=0pw pS=fi00cit1ca0fr25 1 i t4i rhqrta=qh0=rn0ed al de _h wpi|cc1ff ider0q=000 | phammnd_mlae_llhwocpi zco1 neir=0q=x000 0f675c hhaandndllee_=hfwfpiffcf1f fifr q=si0z e =409h6a naldlieg_nh=w1p00ic0 1 riertq=0=0xc ffef000h (hadandendltleae_i_hl=hw0wpixpiccc1f1 f idfir1rq=9q=000 ) |hchhfanhalanfddd_enhwdlee0pilc1e_0_h0 i|rqhw0wp =ip pm ichc1m1 _aimn radillrqeq=l_=0oh0 c w zpoicne1 =0irx0q0=00f 675hc anhadlned_lhe=wpfficf1f fiffrqf =0s i ze=48h aanlhdialgndenl_=4ehw0_p hirwcepi1tc =01irx qci=fr0fq= e0 ef c 0 (hdaentadliel_=h0wxpcficfd1 fi1r6q0)=0 |chhhnfahalandfd_denwdlheei0pl01e_c_hi0 r|qhw0wp= ip pm ichc1m1 _aimn radillrqleq=o_=0h0 c w zpoince1= 0irx0q0=00f 6 75hhcaa nnhaddlnlede__lhheww=ppffiicfc11f fiifrrfqqf ==0s0 i ze=48hh aaannliddlglene__=hh4ww0pp riicec1t1 =ii0rrxqqcf==0f0 e ef80 hh(aadnnetddlaleie__lhh=ww0ppxciicfc11f diifrr1qq30==0)0 hhh|anahndlce_fadfnlhwpiddeel_c1h i0eq0_wrhp0=0 |wi pc i1hp amcinm1d_ rmiqlar=elq0_= hl wo0pc i czo1 neir=0q=x000 0f6758h ahnandldle_eh=wfpfficff1 fifrfq s=0iz eh=4an0d9l6e a_hliwpginc=11 0i00rq =r0e t =0xcfhfadnd0dl00e_ h(wdpeitcai1 li=r0qx=c0ff dhf1an0d0l)e _ hwpic1 hiandl_ewhip1c irq=0f=00f0ff4 handlhheaanlnded_whlepi_c1h iwrq0p= ic 1ha indrql=e_0 hw pic1 irq=h0andl_ewhpic1 irq=f00a052=3f000ff35 handle_hhwandl_ewhip1c irq=0f=00f0ff4 handlhheaanlnded_whlepi_c1h iwrq0p= ic 1ha indrql=e_0 hw pic1 irhhqaanlnded_whlepi_c1h iwrq0p= ic 1ha indrql=e_0 hw pic1 irhhqaanlnded_whlepi_c1h iwrq0p= ic 1ha indrql=e_0 hw pic1 irhhqaanlnded_whlepi_c1h iwrq0p= ic 1ha indrql=e_0 hw pic1 irhhqaanlnded_whlepi_c1h iwrq0p= ic 1ha indrql=e_0 hw pic1 irhhqaanndlde_lhwiep1c_h iwrqp=0i=f0c001aff i4 r qha=0nd f‰þgf]éXýfƒÄ f[f^f_f]fÃ/chfafndddl0e0_h0\w pSihtcana1dr ilt retq_h=hwr0 pea idc 1 irq=0 |hcanfdfdlee_0h00wp| hipac1mnd mli_erfr_q=ehw0ep i 0xc1c ffidrdq=0000 (detail=0xcffdf100) \chafnfddlde00_h0w/p iEhacnn1dd tlirhe_qrh=ew0adp i c1 irq=0 |hcafnfddele0_00hw|p hipacmmn1_d imlera_qlh=low0 cpi czo1n eir=q0x=000 0f6758 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf100) /hcafnfdddle0_00hw\p hiStac1an rdliter t_qhh=0rwp ei acd1 irq=0 |hcafnfddele0_00hw|p hipacmmn1 _diflrre_qeeh= w0 0p xiccf1f dird0q0=00 (detail=0xcffdf100) \chaffnddlde00_h0w/ phEianc1nd d ilthre_rq=he0wa pd ic 1 irq=0 |chaffnddle0e0_h0w| piphcman1m_d mliraeql_=lhw0ocp izco1n ie=r0qx=00 00 f6758 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf100) /hcfanfdddle0_0h0\wp iShactn1ad rtli erqt_h=hw0rp eai dc 1 irq=0 |hacfnfdldee0_h0w0|pih cap1nmm d_ilefrq_r=he0we pi0 cx1cf ifrdqd0=00 0 (detail=0xcffdf100) \chaffnddlde00_h0w/ pEihncand1 d iltrehrq_he=wa0 pd i c1 irq=0 |chaffnddlee00_h0w| ppihamc1nm d_ilmare_lqhl=0wo pc izc1o nier=0q=x00 0 0f6758 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf100) /hcafnfdddle0_00hw\p ihScat1nar dltie rq_t=hhr0we pia cd1 irq=0 |hacnffddlee_00hw0p|i hcpa1mnd m_liferqr_=eh0ewp 0i xcc1 ffidrdq0=000 (detail=0xcffdf100) \hcafnfdddle0_00hw/p hiEnac1dn dliterhr_qeh=0awp di c 1 irq=0 |chaffnddlee00_h0w| ppihamc1nm d_ilmare_lq=hl0wo pc izco1 nier=0q=x00 0 0f6758 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf100) /hcfanfdddle0_0h0\wp hiSactan1 rditler _qth=hrw0 epi acd1 irq=0 |hhaacfnndfdlldeee__00hh0wwp|pii ccp11mm i_irrfqqr==ee00 0 xcffdd000 (detail=0xcffdf100) \chaffnddld0e_0h0w/ piEhcnan1d d itlrheqr_h=ew0adp i c1 irq=0 |phcfsanf2d drlee0ea_0h0dh aw|np 0p dilcm 1me __hifwrrpqeei=0 c1 0 xicrffqe=f0 0 00 (detail=0xcffdf190) D|hcifsacnfdadrlee0d_0ih0nahnw|g dpplipcmse2_1mh _ fdwiprraetiqac=e0 10 0i x0c rf(qfs=0eta eft cus0= (0d3e) ta il=0xcffdf160) |hcfanfddele0_0h0|wp hipacmmn1 _diflrre_qeeh= w0 0p xiccf1f eirefq8=00 (detail=0xcffdf130) |hcafnfddele0_00hw|p hipmacmn1 _dliferr_qeeh=0 w 0pi xcc1ff dirfq1=f00 (detail=0xcffdf240) pmham_ndflreee_h w0xpchicfa1fn ddlieer00_q=0h0 w (pi dec1ta iilr=q=0x0c f fdf1c0) \cphafs2nfdd erlee00a_0hdh w/ap n0d iEcnl de1 _ ithrhwqrpi=eac0 d1 irq=0 Ahlisaln cadtlhrrde_einhahdagwn psi dplscc21oem_ diphrlwaptqe=tiac 0e0 .1 0 ir(sq=t0a t us=03) hmahnamdn_mldaelel_h_lwhopwc ipizc1co 1ni e=ri0qrqx=0=0 00 0f 6758 handle=ffffffff size=72 align=10 ret=0xcffdf1f0 (detail=0xcffdf240) EhhHaCannIdd llinee_i_hthww pponii cc1d1 eiivrr 0qq=0=00: 1 3.2 (regs=0xd4008520) phamnmd_mlea_llhwopchi zac1on ndieler=_q0xh=00w 0p 0icf617 5i8rq h=a0n dle=ffffffff size=4096 align=1000 ret=0xcffde000 (detail=0xcffdf1c0) /hcfanfddle0e_0h0\wp hiStacan1 rdliter _qthh=0rw epi acd1 irq=0 |chafnfddlee00_h0w|p phicma1mn _dlimaerql_=lh0owp c i zc1o nei=r0q=x000 0 f675c handle=ffffffff size=4096 align=1000 ret=0xcffef000 (detail=0xcffdf190) |phcsafnf2d drle0eea_0hh0d| awnp 0ip d lcm1me_ _himwralpq=lic0o1 c ziroqne==0 0 x000f675c handle=ffffffff size=48 align=40 ret=0xcffeefc0 (detail=0xcffdf160) Dhcisaffcnaddler0de_0ih0nhgaw|np ppdilcms1m2e _ _imdhawrapqltlai=c0o c010 z iro(sqnt=e=a00t xu0s0=00f3)67 5 c handle=ffffffff size=48 align=40 ret=0xcffeef80 (detail=0xcffdf130) hha|anncfddflldee_e_hh0ww00pp|iic c1p1 mmii_rrmqq=a=00l lo c zone=0x000f6758 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf100) /chfafnddld0e0_h0w\ pihStcaa1ndr ltire tq_h=hr0wpe iacd1 irq=0 |hcfanfddel0e_00h|wp pihamcnm1d_ ilfrereq_he=w 0p0 ixcc1f fiddr0q=000 ( detail=0xcffdf100) \hpcfasn2fdd lrde0e0_ahhd0w /a np0i Ednlc e1d _ thihwrqrpi=ec0ad1 irq=0 |ichasffncdadreled0i0_0hhnwg|a np dippsmlce12m __mhidraawtlpqi=al oc0c1 0 0 zi (orsnqte=0a=0 tux s00=003f)6 75 8 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf100) /pchasffn2d drdl0eea0_h0hdw a\3n pSi d ltca1e_r htirw qpth=icr01e a idr q =0 i|hshcafncaanfdddlredlee0_i0hn_gh0w|p wpp iipcs12cm1m _id aifrrqtr=aqe=e0 00 3 0 x c(fstfaddt0us0=00 (3d) e tail=0xcffdf100) \pchsfafn2d drdlee0a0_hd0h/wa n0 p Eidcl nd1e_ ihthrwrqpe=ica01d irq=0 |hicfascfnddalred0e_i0hhn0g|wa pn dppimcls1e2m _ _ihdmaarwlqptial=o0c 10c0 i zor(snqte=0a= t0x u0s0=003f)67 58 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf100) /chaffnddld0e0_0hw\ pihScata1nr dltie rq_th=hr0we pia cd1 irq=0 h|acnfdlfede_0hw00p|i hcpa1 mndimlr_feqr_=0eh ewp 0icxc1f firdqd0=000 (detail=0xcffdf100) \chaffnddld0e0_h0w/ pEhinacdn1 dlitherr_qeh=0aw dpi c1 irq=0 |chfafnddle0e0_h0|w phpiamcnm1 d_milare_lqhl=0wo pc iczo1 nier=q0x=00 0 0f6758 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf100) /pchasffn2d drdl0eea0_d0hhaw \p0 nSdi c tlae1r_ ithwr pqthi=rc0 e1 a id r q=0 i|hasccfndafrdleed_i0n0hh0awgp |n dipcspl2me1_ md_hifwraqtrpei=ac0 e0 1 00 xi(crqsff=td0atd u0 s0=00 (3)d e tail=0xcffdf100) \chaffnddld0e0_h0w/ phEianc1nd d tilehr_rqhe=0wad pi c 1 irq=0 |chpsfan2f ddelree00_a0hdh a|wn p0i dplmc 1em_ _hmiwarplq=ilo0c1c izronqe=0= 0 x000f6758 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf100) Dhicfasncfddalrdd0e0_ihhn0wg\a np ipSdtlcse12a r_ hidtra wtpqt=ahi rc01 0e0a i d r(s qt=a0 t us=03) h|acnfdfdled_00h0wp| hicpan1md mli_merqa_=lhw0lp oi c c1z oiner=q=00x0 0 0f6758 handle=ffffffff size=24 align=10 ret=0xcffdf0b0 (detail=0xcffdf0d0) |chafnfddlde00_h0w|p hiOacHn1CId i leri_qnh=itw0 p oicn 1d iervq 0=00 : 13.0 (regs=0xd4005000) |hcfanfdddle0_0h0|wp pihamc1nm d_ilmare_lqhl=0wo pc izc1o nier=0q=x00 0 0f6758 handle=ffffffff size=4096 align=1000 ret=0xcffdc000 (detail=0xcffdf080) /hcafnfddcle0_00hw\p iShactn1ad rtlir eqt_h=hw0rp eai dc 1 irq=0 |hcafnfddlce0_00hw|p ihpmcanm1d_ ilmrealq_l=hwo0 pc i cz1o nie=rq0=x000 0 f675c handle=ffffffff size=256 align=100 ret=0xcffeee00 (detail=0xcffdf050) |chaffnddlce00_h0w| piphacmmn1_d imlrae_qlh=low0 cp izco1n eir=0qx=00 0 0f675c handle=ffffffff size=16 align=10 ret=0xcffeeff0 (detail=0xcffdf020) h|ancfdlfed_c0hw0p0|i chp1anm idmrl_qema=_hl0wl poicc 1zo inreq==0x0 0 00f6758 handle=ffffffff size=4096 align=1000 ret=0xcffda000 (detail=0xcffdbfd0) /hcafnfddale0_00h\wp ihScat1nar dltie rq_t=hhr0we pia cd1 irq=0 |hcafnfddcle0_00hw|p hipacmn1m_d iflerr_qeh=e w0 0p xiccf1f idraq00=00 (detail=0xcffdbfd0) \hcafnfddale0_00hw/p hiEacndn1 d itlerh_qrh=eaw0 dpi c 1 irq=0 |hcfanfddcle0_0h0|wp ihpmcam1nd_ ilmreaq_ll=hwo0 pc i cz1o nei=rq0=x000 0f6758 handle=ffffffff size=4096 align=1000 ret=0xcffda000 (detail=0xcffdbfd0) /chaffnddlae00_h0w\ pSihatc1na drilt re_tq=hh0wr pea idc 1 irq=0 |hcfanfddlc0e_0h0|w piphcman1md _flirreqe_=ehw0 0p xiccf1f idar0q0=00 ( detail=0xcffdbfd0) \hcpsafnf2 ddlar0ee_0ahh0d/ wa0pn dE i cln1ed _ ihthrwprqie=0ca 1d irq=0 Dcihfsacnfddacrle0d0i_0hnhgw|a n pdpipcmlse21m __mhdiarawqlptia=l0oc 10 c0 zi or(nqste=0a=0 tx u0s0=003f)67 5 8 handle=ffffffff size=4096 align=1000 ret=0xcffda000 (detail=0xcffdbfd0) /phcfsa2nfd drlae0ea_00dhh aw\p 0n diSct lae1 r_ithwr pqti=hrc0 e1 aidr q=0 Dh|isacnfcadfldradei_00hnhagw0p|n dpi cWlsAe21 R_NhdiwarIqNptia=G 0 c-10 0 Ti ir(smq=te0aou tt us a=t03 )oh c i_hub_reset:65! |chaffnddlce00_h0w| pihpmcanm1 d_ilfrereq_e=hw 0 p0 ixcc1f fidarq0=000 ( detail=0xcffdbfd0) \hcafnfddale0_00hw/p ihEncand1 d iltrehrq_he=wa0 pd i c1 irq=0 |chaffnddlc0e0_h0w| piphacmn1m_d imlraeql_h=low0cp izco1n ier=0qx=00 00 f6758 handle=ffffffff size=4096 align=1000 ret=0xcffda000 (detail=0xcffdbfd0) /chaffnddlae00_h0w\ phiStacan1 rdliter _qthh=0rw epi acd1 irq=0 |hcfanfddcle0_0h0|wp iphcman1md _lifrerqe_h=ew0 p 0xi ccf1 fidar0q=000 ( detail=0xcffdbfd0) \hcafnfddale0_00hw/p Ehicna1dn dlitherqr_=eh0awp di c1 irq=0 |cphafs2nfdd crlee00a_h0hda w|0p npd i cml1me __imhwralpqli=0oc c1 izornqe==0 0x 000f6758 handle=ffffffff size=4096 align=1000 ret=0xcffda000 (detail=0xcffdbfd0) Dhcisafnfcaddlar0dei_0nhh0aw\g npdiSpctsl2e1a r _dhitwr attpqi=ha0r c01 e a0 d i (r sq=ta0t u s=03) |chaffnddlc0e0_h0w| piphacmn1m_d flirre_qeh=ew0 0p xiccf1f idra0q0=00 (detail=0xcffdbfd0) \hcfanfddale0_0h0/wp iEhacnn1dd tlirhe_qrh=ew0adp i c1 irq=0 |hacnffdldec0_h0w0p|hi acpmn1md i_lerf_qrh=eew0 p 0icxc1f fireqee=00 0 (detail=0xcffdf050) |hcafnfddlce0_00hw|p iphcman1md _flirerqe_h=ew0 p 0xi ccf1 fieerfqf=00 ( detail=0xcffdf020) |hcafnfdddle0_00hw|p hipmac1mn _diflerre_qeh=0 w 0pi xccf1f dicrq00=00 ( detail=0xcffdf080) \chafnfddlce00_h0w/p ihEcand1nd iltrehq_re=hwa0pd i c 1 irq=0 |hcafnfddele0_00hw|p hipmac1mn _dliferr_qeeh=0 wp 0i xcc1ff didrq0=000 (detail=0xcffdf100) \chaffnddlde00_h0w/ phiEnacdn1 ditlerh_qreh=0aw dp ic 1 irq=0 |hcfanfddele0_0h0|wp ihpmcanm1d_ ilfrerq_ee=hw 0 p0 ixcc1f feifrq0=000 (detail=0xcffdf190) |chaffnddlee00_h0w| pphimac1mnd _liferre_q=ehw0 p 0i xcc1f feierqf=c00 ( detail=0xcffdf160) |chaffnddlee00_h0w|p iphacmmn1_d iflrre_qeh=e w0 0p xiccf1f eirefq8=00 (detail=0xcffdf130) |hcfanfddele0_0h0|wp hpicam1nm d_filerr_eq=he0w 0 px iccf1 fidrfq1f=00 (detail=0xcffdf240) phmamn_fdlree_e hw0pxchifac1fnd dlieer00_q=0h0 wp (i dec1t aiilrq==00xc f fdf1c0) \chaffnddlee00_h0w/p iEhacndn1 d itlrhe_qrh=eaw0 dp i c1 irq=0 Ahlpsaln 2 dtlhrreea_eadhh awdps0n di lcc oe1 m_iphwrlpqei=tec0 .1 i rq=0 Dhmisamn_cadmlarlde_lihhoncgaw np izpdslcoe1n2e _ hi=dr0awtpqx=0ai c001 00f0 i6 (r75sq8t= a0 htu asn=dl0e3=) ff ffffff size=24 align=10 ret=0xcffdf220 (detail=0xcffdf240) OhHCanId line_iht wpoinhac dn1ed ivlr eq0_h=0:w0 1p 4i.c51 (irreqg=s0 =0 xd4006000) phmamn_mdalel_lohwcp izhacon1ned i=lr0eqx_h=00w00p fi6c715 i8r hqa=n0 dl e=ffffffff size=4096 align=1000 ret=0xcffde000 (detail=0xcffdf1f0) /hcfanfddle0e_0h0\wp iShactn1ad rtlir eqt_h=hw0rp eai dc 1 irq=0 |hcafnfddele0_00hw|p hpiamc1nm d_milare_lq=hl0wo pc iczo1 nier=0qx=00 0 0f675c handle=ffffffff size=256 align=100 ret=0xcffeff00 (detail=0xcffdf1c0) |chaffnddlee00_h0w| piphcman1md _mliraeql_=lhw0ocp i zco1 nie=r0qx=000 0 f675c handle=ffffffff size=16 align=10 ret=0xcffefef0 (detail=0xcffdf190) ha|ncdfflde_eh00wp0i| hc1pa mnimdlr_meqa_=0lh lwp oic cz1o nire=q0=x00 00f6758 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf160) /hcfanfddld0e_0h0\wp Sihatc1na drilt re_tq=hh0wr pea idc 1 irq=0 |hcfafnddle0e_0h0|w phipmac1mn _diflerre_qeh=0 w 0p xiccf1f didrq00=00 ( detail=0xcffdf160) \chaffnddlde00_h0w/p iEhacndn1 d itlrhe_qrh=eaw0 dp i c1 irq=0 |hcafnfddele0_00hw|p ihpmcanm1 d_ilmrealq_hl=wo0 pc i zc1o nie=rq0=x00 00 f6758 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf160) /hcafnfdddle0_00hw\p ihScata1ndr ltire q_th=hr0wpe iacd1 irq=0 |hcafnfddele0_00h|wp iphacmmn1 _diflrre_qeh=e w0 0p xiccf1f dird0q0=00 (detail=0xcffdf160) \hcafnfdddle0_00hw/p ihEcand1nd ltirehq_re=ha0wpd i c 1 irq=0 |hcanfdfdlee_0h00wp|i hcpa1mnd mli_ferqr_=eh0ewp 0i xcc1 ffierfq=f000 (detail=0xcffdf1c0) |chaffnddlee00_h0w| piphcman1md _lifrerqe_h=ew0 p 0xi ccf1 fiefreqf=00 ( detail=0xcffdf190) phmamn_dfrlee_e hw0pxichacfn1fd delir0eq0_h=0w0 p (di ect1 aiirl=q0=0x cf fdf1f0) \hcafnfddele0_00hw/p iEhacnn1dd tliherqr_h=ew0ap d i c1 irq=0 Ahlaln tdlher_eahwdpsh icac1no dmpilelrq_e=ht0we. pi c 1 irq=0 hmahnamdn_mldaelel_h_lwhopwc ipizcco1 1ni e=ri0qrqx=0=0 00 0f 6758 handle=ffffffff size=72 align=10 ret=0xcffdf1a0 (detail=0xcffdf1f0) EhhHaCannIdd llinee_i_hthww pponii cc1d1 eiivrr 0qq=0=0:0 1 6.2 (regs=0xd4008620) phamnm_dmlea_llhwopc hicza1on ndlie=er0_q=xh00wp 0i 0fc167 5i8r q=ha0n d le=ffffffff size=4096 align=1000 ret=0xcffde000 (detail=0xcffdf170) /cphafsf2ndd erlee0_0a0dhh aw\p 0n diSlct ae1 r_ithwr pqti=hrc0 e1 aidr q=0 Dcihafsfcnddaerlde0_0i0nhhgwa|n ppidpclmsm21e __ mdiharwapltqa=il0co c0 1 0iz ro(qnst=ea0=0t xu0s0=003f6)7 5 c handle=ffffffff size=4096 align=1000 ret=0xcffef000 (detail=0xcffdf140) |hcafnfddele0_00hw|p ihpcam1nm_ dmilearq_l=hl0woc pi cz1on ier=q0x=00 0 0f675c handle=ffffffff size=48 align=40 ret=0xcffeefc0 (detail=0xcffdf110) |chaffnddlee00_h0w| pihpcamm1nd_ lmireaq_l=hlo0wpc i cz1o neir=q0=x000 0f675c handle=ffffffff size=48 align=40 ret=0xcffeef80 (detail=0xcffdf080) hhaa|cnnfddlflede__e0hh0ww0ppi|icc 11pm miir_rqmq==al00l o c zone=0x000f6758 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf050) /hcfanfdddl0e_00h\wp ihScata1ndr ltie rq_th=hwr0pe ia cd1 irq=0 |hhaacfnndfdldleee__0hh00wwp|pi icpc11mm i_irfrqrq==ee00 0 xcffdd000 (detail=0xcffdf050) \hcfanfdddle0_00h/wp ihEcand1n dltiehrq_re=ha0wd pi c 1 irq=0 |chaffnddlee00_0hw| phpicam1nm_ dmilear_lq=hlo0wc p iczo1n ier=q0x=00 0 0f6758 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf050) /chfafnddld0e0_h0\w pihStcaa1nr dltire tq_h=hr0wpe ia cd1 irq=0 |chaffnddele00_0hw| pphimac1mnd _lifrere_q=eh0 wp 0xi ccf1 fdidr0q=000 ( detail=0xcffdf050) \chaffnddld0e0_0hw/ pEihncand1 d tilhrerq_he=0wa pd i c1 irq=0 |chfafnddle0e0_h0|w phpiamc1nm d_milear_lqhl=0woc p iczo1 nier=q0x=00 0 0f6758 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf050) /pchasf2fnd drdl0ee_a00hdhw a\n p0i dSltc a1er _htiw rqpt=ihr0c1e a idr q =0 i|hshccafafnanrdddleldeie0_0_nhgh0 w|w pppsipicmc21 1m _ dfiaitrrreqaq= =e0 00 0 0 x c(sftfdadtu0s0=0 0(3)d e tail=0xcffdf050) \chpsfan2f dddlree00_adh0h/w ap0n dEi c lned1_ ihthrwrqpie=ca0 1d irq=0 Dhicfasncfddalred0e0_ihnh0ga|w p npdpilmcs12em__ idhmawarlqtpail=co0 01c 0z io(rqnst=ea0=t 0xu 0s0=003f6)7 5 8 handle=ffffffff size=4096 align=1000 ret=0xcffdd000 (detail=0xcffdf050) /chpsfafn2 dddlree0a0_h0hd\w a0n pSi d ltcea1_r htirw tqph=icr01e aidr q =0 i|hshcafncaanfdddlredlee0_i0hn_gh0w|p wipp ipcs12cm 1m _id aifrrqtr=aqe=e0 00 0 0 x c(fstfaddt0u0s=00 (3d) e tail=0xcffdf050) \pchsfafn2d drdlee0a0_d0hhwa /0 pnEid l ncd1e _htiwhrqpre=ia0cd 1 i rq=0 |ichasfcfndadrel0ed_i0n0hh|wagn ppidplsmc2m1e _ _dfihrrwapteqe=ia0c 00 1 0x cir(fqsfe=tf0at0 u0s0= 0(d3)e t ail=0xcffdf140) |chpsfafn2 ddelree0a0_hhd0a |w pn3d pimcl 1em __fihrrwpeqie=0c 0 1x cifrfq=e0ef c 0 (detail=0xcffdf110) |ichasfcfndadrel0edi0_hhn0g|aw np ippdmlcse12m __ hidfrarwepqt=aei c0 1 003x i cfr(sfqte=ae0 tf8 u0s =0(3d)et ail=0xcffdf080) |chpsfan2f ddelree00_ahd0h|wa pn0 pidcl mem1__ ihfrrweqpe=ic 0 10 xcirfqf=df01 a0 (detail=0xcffdf1f0) pDhimsma_ncafdrlredehie_ hanng0w xpdilpcsfce1_2fh d eiwdpa0rt0qi=ca0 01 0(i0d er (tq=sa0ti al= t0uxs=c0f3fd) f 170) \chaffnddlee00_0hw/ pEhicnan1dd tliherqr_=ehw0adp i c1 irq=0 Alhla ntdlhree_hadwspih ccao1nm dlpireleq_t=he0wp. i c 1 irq=0 ihniant dples_2phowprthic an1 d lire_qh=w0 pi c1 irq=0 hpmanm_dmlea_llhowpc ihzcano1 dneil=re0q_hx=0w0 p00 ifc61 7i58r qh=0a nd le=ffffffff size=4096 align=1000 ret=0xcffde000 (detail=0xcffdf1f0) /chaffnddle0e0_0hw\ piShactn1ard tlir eqt_h=hrw0ep ai dc 1 irq=0 |chaffnddle0e0_h0w| pihic8a10nd 42li_erf_q=lhw0up shi c 1 irq=0 |chfafnddle0e0_h0|w phiia8c1n04 dl2ie_r_cq=hom0wm pia cn1d icrmqd==10 a a |chpsfafn2 ddelree0a0_h0hd|w a0n pii dc l8e01_4 h2irw_wqpa=ici01t _iwrrqi=te0 D|hiscancfafddlrede0_ihhn0g0aw|np ip dilcs128e 0_ hid4a2wr_pqt=awiac0 1 0i0t i _rr(seqta=ad0 t us=03) |pscha2f fnddrlee0ea_d0h0ah nw5|5 dpli ic 8e0_14h 2wir piqpc=ar10a mi=r5q5= 0 |Dhicfasncfaddelrd0e_hi0n0ha|wngd piilpces8201_ h 4d2iw_rpaitcqo=ca01 m5m i5ar nq(d=s c0tm atd u=s1a=1b9 ) |chaffnddle0e0_0hw| piihac80n14d 2lir_eqw_h=aiw0tp _i wcr1i itre q =0 |hpcfasn2fdd lree0e0_a0hhdwa |0 pnid i 8cl01e4 _2ihw_rqpw=iai0ct 1 _ ireraqd=0 Dhiasncdarled_inhwgp ihpcas21nd ldireaq_ta=h 0wp0 i0c 1( stiraqt=u0s= 19) handle_hwpic1 irq=0h a ndle_hwpic1 irq=0 handle_hwpic1 irq=0ha n dle_hwpic1 irq=0 handle_hwpic1 irq=0h a ndle_hwpic1 irq=0 handle_hwpic1 irq=h0 an dle_hwpic1 irq=0 handle_hwpic1 irq=0h a ndle_hwpic1 irq=0 handle_hwpic1 irq=0ha ndle_hwpic1 irq=0 handle_hwpic1 irq=h0a n dle_hwpic1 irq=0 handle_hwpic1 irq=0ha ndle_hwpic1 irq=0 handle_hwpic1 irq=0ha ndle_hwpic1 irq=0 handle_hwpic1 irq=0h a ndle_hwpic1 irq=0 |c ffde000| WARNING - Timeout at i8042_wait_read:36! |hcfanfddel0e_00h|wp hiia8cn01 d42il re_cqho=0wm pma icnd1 i1rabq =0f a iled pmhpsman2_ fdrlreeee_ad hhaw 0p0xncdi c flfe1d_ iehwr00pq0i= c0 (1 d ietraqi=l0 =0 xcffdf1f0) \ichasfcfndadrel0edi0_hnh0a/wg p npdEincsl12ed_ idhtawhrrqtpaie=ca0 01d 0 i (rsqt=a0 tu s=03) Aplhsla n2d trhleerae_dahhaw d0snp di c cloe1m_ iphwrlpqeti=ec0.1 i rq=0 ihiniasctn dalrsdee_irhhnigawalpn dp i cls1e2 _ ihdarwtqpia=0c 10 0 ir(qs=t0at us=03) hFanoudnlde_ 2h wpseirhcia1 andillr peqo_=0rh twp s ic 1 irq=0 Sehaarncdhlein_ghw CpBihaFcnS1d ilfreorq_h =wp0pr iefc1i xi irmq=g0/ haFondulnde_ hCwBFpiSch 1afi nlidlerqe =_c0hm wos p_icl1a yioruqt.=0b i n hSancadlne _fohwrp oiphcta1 indiolrneq r_=0oh mwp si c 1 irq=0 Ahttanedmplte_inhgwp ithcoan1 id nliierqt_h= w0PCp Ii cb1d if r0q0=:0 00 .0 (vd 1002:5a14) Shpeaas2rncd lrheie_anhhdg waCpn0d BiFcl 1eS _ fihorwrqpi =0cpr 1e fiirqx= 0pc i 1002,5a14.rom DhFisaonucadnldr dei_CBnhhgwaFnS ppid lfsci21e _l ediharw pctqa=imco 00 1s _0 il(raysqot=0ua tt .ubsi=n03 ) hAanttdleem_pthwipngic h1ta ondi mlrqae=p_0 hw op ptici1on irrqom= 0o n dev 00:00.0 Ohaptnidlone _hrwomp ihasc1niz diilnre_gq=h 0wre pt iucr1n ierd q0=0 0 Ahttanedmplte_inhgw pihtoca 1ni dlnireitq_ =hP0wpC iIc 1b dfi rq0=0:01 1 .0 (vd 1002:4393) Sehaarncdlhien_ghw CphBiaFc1nS d fileor_rqh =0wpr pie cfi1x i rpqci=01 0 02,4393.rom haFondulnde _hCwBFpiS hcfa1 indillreeq c_=mh0 ow sp_ilc1a yoiurqt=.b0 i n haAntdtelme_phtiwpnigc h1tan odi mlrqae=p_0 hw opp tici1on irrqom= 0o n dev 00:11.0 hOaptndiloen _hrwompi hacsn1id zilinerqg_h= w0rp eti ucr1 niedr q0=0 0 Athatendmlpeti_hnwg pithcoan1 d inliierqt_h= w0Pp CIi cb1 dif r0q0=0: 12 .0 (vd 1002:4397) Sheaanrdchlei_nhg wpCihBFcanS1d ilfreoq_r =hwp0 pr iecf1i xi prqc=i010 02,4397.rom haFnodunlde_ hCBwpFiSch 1af niliderle q=_c0hm wo psi_cl1ay ioruqt.=0b in hAanttdleem_pthwipngic h1ta ondi mlraeq=p_0 hw op pticio1n irrqom= 0o n dev 00:12.0 hOaptndilone _hrwompih casi1nz dliirenq_g=h r0wpe it cu1rn eirdq =0 0 0 Ahtatnedmplet_inhwgp htiaoc1n dinilire_tq=h 0wP pCI ic b1 difr 0q0=0: 1 2.2 (vd 1002:4396) Sheaanrdchlei_nhg wpChiBFac1Sn difleror_q= h0pw rpi ecf1ix iprqci=100 0 2,4396.rom haFondulnde_ hCwBFpiShc a1fin ldireleq _=ch0mw osp _icl1ay oirutq.=0b in hAanttdleem_pthwipngi chat1 noid rlmaqe_p=0h wo pptici1o n irrqo=m0 o n dev 00:12.2 hOaptndiloen _hrwomp ihasc1ni dzilinre_gqh =0wr pet iuc1r nierd q=00 0 Ahttaendmlpte_ihngw pihtcao 1ndi ilnreiq_t =hwP0pC iIc 1b dfir q0=00:1 3.0 (vd 1002:4397) Sehaarncdlhein_hgw pChBiaFc1nS d filore_rq=h 0wp pre icfi1 xi rpcqi=01 0 02,4397.rom haFondulnde_ hCwBFpiS hc1fan idillre eq=c_0mh owp si_lca1 yiourqt=.b0i n haAtndtlemep_htwinpighc a1ton i dlrmeqa_=p h0ow ppitico1 ni rroqm=0 on dev 00:13.0 Ohpantdilone_ hrowpmhi sacin1 zdliiern_qg h=0rw epi tcu1rn eirdq =0 00 Ahttanedmplte_ihngwp hitacon1 id nlirie_qth= w0PCp Iic b1d ifr 0q0=:0 1 3.2 (vd 1002:4396) Sehaarncdlhein_hgw CphBiaFc1nS d ilfore_rq=h 0wp pre icfi1 xi rpcq=i01 0 02,4396.rom haFondulnde_ hCwBFpSiha cnf1 diillere q_hc=wm0 po isc_1la iyroqut=0. bi n haAtndtlemep_htwinpigh c1at noid mrleaq=_p0h wop pitic1o ni rrqo=m0 on dev 00:13.2 hOapntidloen_ rhwopmhi acsin1 zdiilern_qg h=rw0 epi tcu1rn eirdq 0= 00 Ahttanedmplet_ihngwp tihaocn 1 diilniretq_h =0wP pC iI c1b difr 0q=00: 14 .0 (vd 1002:4385) Sheaanrcdlhei_nghw pCihBcaFS1nd lfireoq_r =hp0wpr iecf1i x irpqc=i100 02,4385.rom hFanoudlned _ChwBpFSihc fa1in ildrelq e_=ch0mow sp _ilca1y oirutq.=b0 in haAntdtleme_phtiwpnighc ta1 oni dlrmeqa_=p h0 owp pitico1n i rroqm= 0 o n dev 00:14.0 hOaptndilone_ hrwomphi sac1in zdliierng_q h=0rwp ei tcu1rn eidrq =0 00 Ahttanedmlpte_ihngwp tihocan 1 diilnreitq_h =wP0 pC iI c1b dif rq0=00: 14 .1 (vd 1002:439c) Sheaanrdchlei_nghw pCBhicFa1Snd lifoerr_q= hw0pp ri efc1i x iprcq=i010 0 2,439c.rom haFondulnde_ hCwBFpiSch f1ani dlirleqe =_cm0ho wps i_lc1a yioruqt=.b0 i n hAanttdleemp_thwipngi hc1ta oni dlrmeqap_=0 h ow ppitico1n irroqm= 0 o n dev 00:14.1 hOaptnidloen _hrwompi hacsn1id zilinerqg_h= w0rp eti ucr1 niedr q0=0 0 Athatendmlpeti_hnwg phitacon1 id inlrie_qth= w0PCp Iic b1d ifr 0q0=:0 1 4.2 (vd 1002:4383) Sehaarncdlhein_hgw CpBihFcanS1 d ilfreorq_h =wp0 pr iefc1i xi prqc=i01 00 2,4383.rom haFondulnde_ hCBwFpiShc fa1 inildreleq c_=mh0ow sp_ilc1ay oiurqt.=b0 in haAtndtlemep_htwinpigh c1at no idmrleaq=_p0h wop pitic1o ni rroq=m0 on dev 00:14.2 hOapntidloen_ rhwopmi hcsan1id zliinerqg_h= w0rp eti ucr1 niedr q=00 0 Athatnemdlpeti_hnwgp ithacon1 d inlirieqt_h= w0PCp Ii cb1 difr 0q0=0: 14 .3 (vd 1002:439d) Sheaanrdchlei_nghw pChiBFac1Sn dlifero_qr h=0pwp ri ecf1ix iprqc=i100 02,439d.rom haFnodunlde_ hCBwpFiSc h1fan idilelrq e=c_0mh ow spi_lca1y oiurtq=.b0i n haAtndtleemp_htwinpighc a1tn o dirmlqae_=ph0 ow pp tiic1o ni rroq=m0 on dev 00:14.3