coreboot-4.0-2039-gd16b170 Wed Feb 8 17:50:46 CET 2012 starting... zomg1 zomg2 cimx/rd890 early.c nb_Poweron_Init() Start cimx/rd890 early.c nb_Poweron_Init() End. return status=0 zomg3 AmdHtInit status: 0 zomg4 BSP Family_Model: 00100fa0 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000 microcode: patch id to apply = 0x010000bf microcode: updated to patch id = 0x010000bf success POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 SB900 - Early.c - get_sbdn - Start. SB900 - Early.c - get_sbdn - End. cpuSetAMDPCI 00 done Prep FID/VID Node:00 P-state info in MSRC001_0064 is invalid !!! P-state info in MSRc0010064 is invalid !!! F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001016 F3xDC: 0000611a POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 POST: 0x37 started ap apicid: PPPPPOOOOOSSSSSTTTTT::::: 00000xxxxx3333300000 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000032514 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000021435}}}}} --------------- * AmmmmmPiiiiicc cccrrrr0r1ooooocccccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000 startmmmemmiiidiiccccc r rrrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff mmmmm*i iiiicccAccrrrrrPo ooooccc0ccooooo2dddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss scccccptppppuuuauuSSSSSreteeeetttettAAAAAdM MMMMDDD DDMMMMMSSSSSRRRRR * AP 0dddd3dooooonnnnneeeee stiiiiinnnanniiiiirtttttt___e__fffffdi iiiiddd ddvvvvviiiiiddddd_____aaaaappppp(((((ssssstttttaaaaagggggeeeee11111))))) aaaaapppppiiiiiccccciiiiiddddd::::: 0000043152 FFFF*F IIIIIDDADDDVVVVPV IIIIIDD0DDD 4 ooooonnnnn AAAAAPPPPP::::: 0000024315 started * AP 05started POST: 0x38 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 POST: 0x39 FIDVID on BSP, APIC_id: 00 BSP fid = 0 Wait for AP stage 1: ap_apicid = 1 readback = 1000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2 readback = 2000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 3 readback = 3000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 4 readback = 4000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 5 readback = 5000001 common_fid(packed) = 0 common_fid = 0 POST: 0x3a End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 ...WARM RESET... coreboot-4.0-2039-gd16b170 Wed Feb 8 17:50:46 CET 2012 starting... zomg1 zomg2 cimx/rd890 early.c nb_Poweron_Init() Start cimx/rd890 early.c nb_Poweron_Init() End. return status=0 zomg3 AmdHtInit status: 0 zomg4 BSP Family_Model: 00100fa0 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000 microcode: patch id to apply = 0x010000bf microcode: updated to patch id = 0x010000bf success POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 SB900 - Early.c - get_sbdn - Start. SB900 - Early.c - get_sbdn - End. cpuSetAMDPCI 00 done Prep FID/VID Node:00 P-state info in MSRC001_0064 is invalid !!! P-state info in MSRc0010064 is invalid !!! F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001016 F3xDC: 0000611a POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 POST: 0x37 started ap apicid: PPPPPOOOOOSSSSSTTTTT::::: 00000xxxxx3333300000 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000043215 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000015423}}}}} --------------- * AmmmmmiiPiiicc cccrr0rrroo1ooocccccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000 startmmemmmdiiiii ccccc rrrrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff mmmmm*iii iicccAccrrrPrroo ooocc0cccoo2ooodddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss sccppccctuupppaSuuurSeSSSteteeeetAtttdAAAA MMMMM DDDDDMMSSMMMSSRRS RRR * AP 0 d3ddddooooonnnnneeeee siiitiinnannniiriiitttttt_e____fdffffi iiiid ddddvvvvviiiiiddddd_____ssssstttttaaaaagggggeeeee22222 aaaaapppppiiiiiccccciiiiiddddd::::: 0000032145 * AP 04started * AP 05started POST: 0x38 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 POST: 0x39 POST: 0x3a End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 POST: 0x3b fill_mem_ctrl() POST: 0x40 raminit_amdmct() raminit_amdmct begin: SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=c DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=10 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=10 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 1000 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDGetTCL_D: DIMMCASL 4 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 1000 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: e00000 Node: 00 base: 03 limit: 21fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:e00000 CPUMemTyping: Bottom32bIO:e00000 CPUMemTyping: Bottom40bIO:2200000 mctAutoInitMCT_D: DQSTiming_D SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. TrainRcvrEn: Status 1100 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 1100 InterleaveNodes_D: ErrStatus 0 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 1100 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D All Done raminit_amdmct end: POST: 0x41 POST: 0x42 v_esp=000cbef8 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1310720 bytes), entry @ 0x200000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-4.0-2039-gd16b170 Wed Feb 8 17:50:46 CET 2012 booting... POST: 0x40 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Mainboard ASUS M5A99X-EVO Enable. dev=0x00239e2c scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=5 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled CPU: APIC: 04 enabled CPU: APIC: 05 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled POST: 0x25 PCI: Using configuration type 1 PCI: 00:00.0 [1002/5a14] ops PCI: 00:00.0 [1002/5a14] enabled Capability: type 0x08 @ 0xf0 flags: 0xa803 Capability: type 0x08 @ 0xf0 Capability: type 0x08 @ 0xc4 flags: 0x0281 PCI: pci_scan_bus for bus 00 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff PCI: pci_scan_bus upper limit too big. Using 0xff. POST: 0x24 PCI: 00:00.0 [1002/5a14] enabled PCI: 00:11.0 [1002/4393] enabled PCI: 00:12.0 [1002/4397] enabled PCI: 00:12.2 [1002/4396] enabled PCI: 00:13.0 [1002/4397] enabled PCI: 00:13.2 [1002/4396] enabled PCI: 00:14.0 [1002/4385] enabled PCI: 00:14.1 [1002/439c] enabled PCI: 00:14.2 [1002/4383] enabled PCI: 00:14.3 [1002/439d] enabled PCI: 00:14.4 [1002/4384] enabled PCI: 00:14.5 [1002/4399] enabled PCI: 00:16.0 [1002/4397] enabled PCI: 00:16.2 [1002/4396] enabled PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:14.4 PCI: pci_scan_bus for bus 01 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 do_pci_scan_bridge returns max 1 PCI: pci_scan_bus returning with max=001 POST: 0x55 PCI: pci_scan_bus returning with max=001 POST: 0x55 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done POST: 0x66 Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources APIC: 02 missing read_resources APIC: 03 missing read_resources APIC: 04 missing read_resources APIC: 05 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:14.4 read_resources bus 1 link: 0 PCI: 00:14.4 read_resources bus 1 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 PCI: 00:00.0 missing read_resources PCI: 00:02.0 missing read_resources PCI: 00:0d.0 missing read_resources PCI: 00:11.0 missing read_resources PCI: 00:12.0 missing read_resources PCI: 00:12.2 missing read_resources PCI: 00:13.0 missing read_resources PCI: 00:13.2 missing read_resources PCI: 00:14.0 missing read_resources PCI: 00:14.1 missing read_resources PCI: 00:14.2 missing read_resources PCI: 00:14.3 missing read_resources PCI: 00:14.5 missing read_resources PCI: 00:15.0 missing read_resources PCI: 00:15.1 missing read_resources PCI: 00:15.2 missing read_resources PCI: 00:15.3 missing read_resources PCI: 00:16.0 missing read_resources PCI: 00:16.2 missing read_resources PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI: 00:18.0 read_resources bus 0 link: 3 PCI: 00:18.0 read_resources bus 0 link: 3 done PCI: 00:18.0 read_resources bus 0 link: 4 PCI: 00:18.0 read_resources bus 0 link: 4 done PCI: 00:18.0 read_resources bus 0 link: 5 PCI: 00:18.0 read_resources bus 0 link: 5 done PCI: 00:18.0 read_resources bus 0 link: 6 PCI: 00:18.0 read_resources bus 0 link: 6 done PCI: 00:18.0 read_resources bus 0 link: 7 PCI: 00:18.0 read_resources bus 0 link: 7 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110a8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110a0 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 1200 index fc PCI: 00:11.0 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.3 PCI: 00:14.4 PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:02.0 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0d.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.2 PCI: 00:13.0 PCI: 00:13.2 PCI: 00:14.0 child on link 0 I2C: 00:50 I2C: 00:50 I2C: 00:51 I2C: 00:52 I2C: 00:53 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 child on link 0 PNP: 002e.0 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:14.4 PCI: 00:14.5 PCI: 00:14.6 PCI: 00:15.0 PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: 00:16.0 PCI: 00:16.2 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:11.0 20 * [0x0 - 0xf] io PCI: 00:14.1 20 * [0x10 - 0x1f] io PCI: 00:11.0 10 * [0x20 - 0x27] io PCI: 00:11.0 18 * [0x28 - 0x2f] io PCI: 00:14.1 10 * [0x30 - 0x37] io PCI: 00:14.1 18 * [0x38 - 0x3f] io PCI: 00:11.0 14 * [0x40 - 0x43] io PCI: 00:11.0 1c * [0x44 - 0x47] io PCI: 00:14.1 14 * [0x48 - 0x4b] io PCI: 00:14.1 1c * [0x4c - 0x4f] io PCI: 00:18.0 compute_resources_io: base: 50 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 10d8 * [0x0 - 0xfff] io PCI_DOMAIN: 0000 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.0 fc * [0x0 - 0xff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI: 00:14.2 10 * [0x4000000 - 0x4003fff] mem PCI: 00:12.0 10 * [0x4004000 - 0x4004fff] mem PCI: 00:13.0 10 * [0x4005000 - 0x4005fff] mem PCI: 00:14.5 10 * [0x4006000 - 0x4006fff] mem PCI: 00:16.0 10 * [0x4007000 - 0x4007fff] mem PCI: 00:11.0 24 * [0x4008000 - 0x40083ff] mem PCI: 00:12.2 10 * [0x4008400 - 0x40084ff] mem PCI: 00:13.2 10 * [0x4008500 - 0x40085ff] mem PCI: 00:16.2 10 * [0x4008600 - 0x40086ff] mem PCI: 00:18.0 compute_resources_mem: base: 4008700 size: 4100000 align: 26 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done PCI: 00:18.0 10b0 * [0x0 - 0x40fffff] mem PCI: 00:18.3 94 * [0x8000000 - 0xbffffff] mem PCI: 00:18.0 10b8 * [0xc000000 - 0xc0fffff] prefmem PCI_DOMAIN: 0000 compute_resources_mem: base: c100000 size: c100000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:11.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:12.2 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:13.2 constrain_resources: PCI: 00:14.0 constrain_resources: PCI: 00:14.1 constrain_resources: PCI: 00:14.2 constrain_resources: PCI: 00:14.3 constrain_resources: PCI: 00:14.4 constrain_resources: PCI: 00:14.5 constrain_resources: PCI: 00:16.0 constrain_resources: PCI: 00:16.2 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:0d.0 constrain_resources: PCI: 00:11.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:12.2 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:13.2 constrain_resources: PCI: 00:14.0 constrain_resources: I2C: 00:50 constrain_resources: I2C: 00:51 constrain_resources: I2C: 00:52 constrain_resources: I2C: 00:53 constrain_resources: PCI: 00:14.1 constrain_resources: PCI: 00:14.2 constrain_resources: PCI: 00:14.3 constrain_resources: PNP: 002e.2 skipping PNP: 002e.2@60 fixed resource, size=0! skipping PNP: 002e.2@70 fixed resource, size=0! constrain_resources: PNP: 002e.3 skipping PNP: 002e.3@60 fixed resource, size=0! skipping PNP: 002e.3@70 fixed resource, size=0! constrain_resources: PNP: 002e.5 skipping PNP: 002e.5@60 fixed resource, size=0! skipping PNP: 002e.5@62 fixed resource, size=0! skipping PNP: 002e.5@70 fixed resource, size=0! skipping PNP: 002e.5@72 fixed resource, size=0! constrain_resources: PNP: 002e.b skipping PNP: 002e.b@60 fixed resource, size=0! skipping PNP: 002e.b@70 fixed resource, size=0! constrain_resources: PCI: 00:14.5 constrain_resources: PCI: 00:15.0 constrain_resources: PCI: 00:15.1 constrain_resources: PCI: 00:15.2 constrain_resources: PCI: 00:15.3 constrain_resources: PCI: 00:16.0 constrain_resources: PCI: 00:16.2 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00000000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit dfffffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:0 size:1000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 10d8 * [0x0 - 0xfff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1000 size: 1000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:0 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 00:11.0 20 * [0x0 - 0xf] io Assigned: PCI: 00:14.1 20 * [0x10 - 0x1f] io Assigned: PCI: 00:11.0 10 * [0x20 - 0x27] io Assigned: PCI: 00:11.0 18 * [0x28 - 0x2f] io Assigned: PCI: 00:14.1 10 * [0x30 - 0x37] io Assigned: PCI: 00:14.1 18 * [0x38 - 0x3f] io Assigned: PCI: 00:11.0 14 * [0x40 - 0x43] io Assigned: PCI: 00:11.0 1c * [0x44 - 0x47] io Assigned: PCI: 00:14.1 14 * [0x48 - 0x4b] io Assigned: PCI: 00:14.1 1c * [0x4c - 0x4f] io PCI: 00:18.0 allocate_resources_io: next_base: 50 size: 1000 align: 12 gran: 12 done PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:18.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:18.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:c100000 align:26 gran:0 limit:dfffffff Assigned: PCI: 00:18.0 10b0 * [0xd0000000 - 0xd40fffff] mem Assigned: PCI: 00:18.3 94 * [0xd8000000 - 0xdbffffff] mem Assigned: PCI: 00:18.0 10b8 * [0xdc000000 - 0xdc0fffff] prefmem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: dc100000 size: c100000 align: 26 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:dc000000 size:100000 align:20 gran:20 limit:dfffffff Assigned: PCI: 00:00.0 fc * [0xdc000000 - 0xdc0000ff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: dc000100 size: 100000 align: 20 gran: 20 done PCI: 00:14.4 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:14.4 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:d0000000 size:4100000 align:26 gran:20 limit:dfffffff Assigned: PCI: 00:18.3 94 * [0xd0000000 - 0xd3ffffff] mem Assigned: PCI: 00:14.2 10 * [0xd4000000 - 0xd4003fff] mem Assigned: PCI: 00:12.0 10 * [0xd4004000 - 0xd4004fff] mem Assigned: PCI: 00:13.0 10 * [0xd4005000 - 0xd4005fff] mem Assigned: PCI: 00:14.5 10 * [0xd4006000 - 0xd4006fff] mem Assigned: PCI: 00:16.0 10 * [0xd4007000 - 0xd4007fff] mem Assigned: PCI: 00:11.0 24 * [0xd4008000 - 0xd40083ff] mem Assigned: PCI: 00:12.2 10 * [0xd4008400 - 0xd40084ff] mem Assigned: PCI: 00:13.2 10 * [0xd4008500 - 0xd40085ff] mem Assigned: PCI: 00:16.2 10 * [0xd4008600 - 0xd40086ff] mem PCI: 00:18.0 allocate_resources_mem: next_base: d4008700 size: 4100000 align: 26 gran: 20 done PCI: 00:14.4 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:14.4 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:18.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:18.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 split: 64K table at =cfff0000 0: mmio_basek=00340000, basek=00400000, limitk=00880000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:18.0 10d8 <- [0x0000000000 - 0x0000000fff] size 0x00001000 gran 0x0c io PCI: 00:18.0 10b8 <- [0x00dc000000 - 0x00dc0fffff] size 0x00100000 gran 0x14 prefmem PCI: 00:18.0 10b0 <- [0x00d0000000 - 0x00d40fffff] size 0x04100000 gran 0x14 mem PCI: 00:18.0 110d0 <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c io PCI: 00:18.0 110a8 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 prefmem PCI: 00:18.0 110a0 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:00.0 fc <- [0x00dc000000 - 0x00dc0000ff] size 0x00000100 gran 0x08 prefmem PCI: 00:11.0 10 <- [0x0000000020 - 0x0000000027] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000000040 - 0x0000000043] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000000028 - 0x000000002f] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000000044 - 0x0000000047] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000000000 - 0x000000000f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00d4008000 - 0x00d40083ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00d4004000 - 0x00d4004fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00d4008400 - 0x00d40084ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00d4005000 - 0x00d4005fff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00d4008500 - 0x00d40085ff] size 0x00000100 gran 0x08 mem PCI: 00:14.1 10 <- [0x0000000030 - 0x0000000037] size 0x00000008 gran 0x03 io PCI: 00:14.1 14 <- [0x0000000048 - 0x000000004b] size 0x00000004 gran 0x02 io PCI: 00:14.1 18 <- [0x0000000038 - 0x000000003f] size 0x00000008 gran 0x03 io PCI: 00:14.1 1c <- [0x000000004c - 0x000000004f] size 0x00000004 gran 0x02 io PCI: 00:14.1 20 <- [0x0000000010 - 0x000000001f] size 0x00000010 gran 0x04 io PCI: 00:14.2 10 <- [0x00d4000000 - 0x00d4003fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:14.4 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:14.4 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:14.5 10 <- [0x00d4006000 - 0x00d4006fff] size 0x00001000 gran 0x0c mem PCI: 00:16.0 10 <- [0x00d4007000 - 0x00d4007fff] size 0x00001000 gran 0x0c mem PCI: 00:16.2 10 <- [0x00d4008600 - 0x00d40086ff] size 0x00000100 gran 0x08 mem PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 1000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base d0000000 size c100000 align 26 gran 0 limit dfffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size cff40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base 100000000 size 120000000 align 0 gran 0 limit 0 flags e0004200 index 30 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 1000 align 12 gran 12 limit ffff flags 60080100 index 10d8 PCI: 00:18.0 resource base dc000000 size 100000 align 20 gran 20 limit dfffffff flags 60081200 index 10b8 PCI: 00:18.0 resource base d0000000 size 4100000 align 26 gran 20 limit dfffffff flags 60080200 index 10b0 PCI: 00:18.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080100 index 110d0 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081200 index 110a8 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080200 index 110a0 PCI: 00:00.0 PCI: 00:00.0 resource base dc000000 size 100 align 8 gran 8 limit dfffffff flags 60001200 index fc PCI: 00:11.0 PCI: 00:11.0 resource base 20 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:11.0 resource base 40 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:11.0 resource base 28 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:11.0 resource base 44 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:11.0 resource base d4008000 size 400 align 10 gran 10 limit dfffffff flags 60000200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base d4004000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base d4008400 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base d4005000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base d4008500 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.1 resource base 30 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:14.1 resource base 48 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:14.1 resource base 38 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:14.1 resource base 4c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:14.1 resource base 10 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base d4000000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 10 PCI: 00:14.3 PCI: 00:14.4 PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base d4006000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base d4007000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base d4008600 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base d0000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 PCI: 00:18.4 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:02.0 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0d.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.2 PCI: 00:13.0 PCI: 00:13.2 PCI: 00:14.0 child on link 0 I2C: 00:50 I2C: 00:50 I2C: 00:51 I2C: 00:52 I2C: 00:53 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 child on link 0 PNP: 002e.0 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:14.4 PCI: 00:14.5 PCI: 00:14.6 PCI: 00:15.0 PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: 00:16.0 PCI: 00:16.2 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base d8000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 PCI: 00:18.4 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/843e PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/843e PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1043/843e PCI: 00:18.4 cmd <- 00 PCI: 00:00.0 cmd <- 02 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 cmd <- 02 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 cmd <- 02 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 cmd <- 0f PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 cmd <- 02 PCI: 00:16.0 cmd <- 02 PCI: 00:16.2 cmd <- 02 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00006000, offset=0x00200000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 00 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #0 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 1. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #1 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 01 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x01 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #1 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 2. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #2 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 02 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x02 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #2 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 3. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #3 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 03 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x03 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #3 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 4. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #4 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 04 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x04 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #4 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 5. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #5 Waiting for 1 CPUS to stop CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 05 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x05 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #5 initialized All AP CPUs stopped SB900 - Early.c - sb_After_Pci_Init - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_After_Pci_Init - End. SB900 - Early.c - sb_Mid_Post_Init - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_Mid_Post_Init - End. PCI: 00:18.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init PCI: 00:00.0 init IOAPIC: Initializing IOAPIC at 0xdc000000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x01 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC not responding. PCI: 00:11.0 init PCI: 00:12.0 init PCI: 00:12.2 init PCI: 00:13.0 init PCI: 00:13.2 init PCI: 00:14.0 init PCI: 00:14.1 init PCI: 00:14.2 init PCI: 00:14.3 init PCI: 00:14.5 init PCI: 00:16.0 init PCI: 00:16.2 init PCI: 00:18.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 APIC: 01: enabled 1 APIC: 02: enabled 1 APIC: 03: enabled 1 APIC: 04: enabled 1 APIC: 05: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 POST: 0x89 Initializing CBMEM area to 0xcfff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to cfff0200...ok High Tables Base is cfff0000. POST: 0x9a SB900 - Early.c - sb_Late_Post - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_Late_Post - End. Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done. Adding CBMEM entry as no. 2 Writing IRQ routing tables to 0xcfff0400...write_pirq_routing_table done. PIRQ table: 48 bytes. POST: 0x9b Wrote the mp table end at: 000f0410 - 000f055c Adding CBMEM entry as no. 3 Wrote the mp table end at: cfff1410 - cfff155c MP table: 348 bytes. POST: 0x9c Adding CBMEM entry as no. 4 ACPI: Writing ACPI tables at cfff2400... ACPI: * HPET at cfff24c8 ACPI: added table 1/32, length now 40 ACPI: * MADT at cfff2500 ACPI: added table 2/32, length now 44 ACPI: * SRAT at cfff2580 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=0033fd00 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00480000 ACPI: added table 3/32, length now 48 ACPI: * SLIT at cfff2688 ACPI: added table 4/32, length now 52 ACPI: * SSDT at cfff26c0 ACPI: added table 5/32, length now 56 ACPI: * SSDT for PState at cfff2cf5 ACPI: * DSDT at cfff2cf8 ACPI: * DSDT @ cfff2cf8 Length 288b ACPI: * FACS at cfff5588 ACPI: * FADT at cfff55c8 ACPI_BLK_BASE: 0x0800 ACPI: added table 6/32, length now 60 ACPI: done. ACPI tables: 12988 bytes. Adding CBMEM entry as no. 5 smbios_write_tables: cfffd800 Root Device (ASUS M5A99X-EVO Mainboard) APIC_CLUSTER: 0 (AMD FAM10 Root Complex) APIC: 00 (socket AM3) PCI_DOMAIN: 0000 (AMD FAM10 Root Complex) PCI: 00:18.0 (AMD FAM10 Northbridge) PCI: 00:00.0 (ATI rd890) PCI: 00:00.1 (ATI rd890) PCI: 00:02.0 (ATI rd890) PCI: 00:03.0 (ATI rd890) PCI: 00:04.0 (ATI rd890) PCI: 00:05.0 (ATI rd890) PCI: 00:06.0 (ATI rd890) PCI: 00:07.0 (ATI rd890) PCI: 00:08.0 (ATI rd890) PCI: 00:09.0 (ATI rd890) PCI: 00:0a.0 (ATI rd890) PCI: 00:0b.0 (ATI rd890) PCI: 00:0c.0 (ATI rd890) PCI: 00:0d.0 (ATI rd890) PCI: 00:11.0 (ATI SB900) PCI: 00:12.0 (ATI SB900) PCI: 00:12.2 (ATI SB900) PCI: 00:13.0 (ATI SB900) PCI: 00:13.2 (ATI SB900) PCI: 00:14.0 (ATI SB900) I2C: 00:50 () I2C: 00:51 () I2C: 00:52 () I2C: 00:53 () PCI: 00:14.1 (ATI SB900) PCI: 00:14.2 (ATI SB900) PCI: 00:14.3 (ATI SB900) PNP: 002e.0 (ITE IT8721F Super I/O) PNP: 002e.1 (ITE IT8721F Super I/O) PNP: 002e.2 (ITE IT8721F Super I/O) PNP: 002e.3 (ITE IT8721F Super I/O) PNP: 002e.5 (ITE IT8721F Super I/O) PNP: 002e.6 (ITE IT8721F Super I/O) PNP: 002e.7 (ITE IT8721F Super I/O) PNP: 002e.8 (ITE IT8721F Super I/O) PNP: 002e.9 (ITE IT8721F Super I/O) PNP: 002e.a (ITE IT8721F Super I/O) PNP: 002e.b (ITE IT8721F Super I/O) PCI: 00:14.4 (ATI SB900) PCI: 00:14.5 (ATI SB900) PCI: 00:14.6 (ATI SB900) PCI: 00:15.0 (ATI SB900) PCI: 00:15.1 (ATI SB900) PCI: 00:15.2 (ATI SB900) PCI: 00:15.3 (ATI SB900) PCI: 00:16.0 (ATI SB900) PCI: 00:16.2 (ATI SB900) PCI: 00:18.1 (AMD FAM10 Northbridge) PCI: 00:18.2 (AMD FAM10 Northbridge) PCI: 00:18.3 (AMD FAM10 Northbridge) PCI: 00:18.4 (AMD FAM10 Northbridge) APIC: 01 () APIC: 02 () APIC: 03 () APIC: 04 () APIC: 05 () PCI: 00:00.0 () PCI: 00:11.0 () PCI: 00:12.0 () PCI: 00:12.2 () PCI: 00:13.0 () PCI: 00:13.2 () PCI: 00:14.0 () PCI: 00:14.1 () PCI: 00:14.2 () PCI: 00:14.3 () PCI: 00:14.4 () PCI: 00:14.5 () PCI: 00:16.0 () PCI: 00:16.2 () PCI: 00:18.0 () PCI: 00:18.1 () PCI: 00:18.2 () PCI: 00:18.3 () PCI: 00:18.4 () SMBIOS tables: 269 bytes. POST: 0x9d Adding CBMEM entry as no. 6 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 4fde New low_table_end: 0x00000518 Now going to write high coreboot table at 0xcfffe000 rom_table_end = 0xcfffe000 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0xcfffe000 to 0xd0000000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-00000000cffeffff: RAM 3. 00000000cfff0000-00000000cfffffff: CONFIGURATION TABLES 4. 00000000e0000000-00000000efffffff: RESERVED 5. 0000000100000000-000000021fffffff: RAM Wrote coreboot table at: cfffe000 - cfffe1e0 checksum 729e coreboot table: 480 bytes. POST: 0x9e POST: 0x9d Multiboot Information structure has been written. 0. FREE SPACE d0000000 00000000 1. GDT cfff0200 00000200 2. IRQ TABLE cfff0400 00001000 3. SMP TABLE cfff1400 00001000 4. ACPI cfff2400 0000b400 5. SMBIOS cfffd800 00000800 6. COREBOOT cfffe000 00002000 Searching for fallback/payload Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Got a payload Loading segment from rom address 0xffc43f38 data (compression=1) New segment dstaddr 0xed150 memsize 0x12eb0 srcaddr 0xffc43f70 filesize 0x9759 (cleaned up) New segment addr 0xed150 size 0x12eb0 offset 0xffc43f70 filesize 0x9759 Loading segment from rom address 0xffc43f54 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000ed150 memsz: 0x0000000000012eb0 filesz: 0x0000000000009759 lb: [0x0000000000200000, 0x0000000000340000) Post relocation: addr: 0x00000000000ed150 memsz: 0x0000000000012eb0 filesz: 0x0000000000009759 using LZMA [ 0x000ed150, 00100000, 0x00100000) <- ffc43f70 dest 000ed150, end 00100000, bouncebuffer cfd70000 Loaded segments Jumping to boot code at fc63c POST: 0xf8 entry = 0x000fc63c lb_start = 0x00200000 lb_size = 0x00140000 adjust = 0xcfcb0000 buffer = 0xcfd70000 elf_boot_notes = 0x0023b1c4 adjusted_boot_notes = 0xcfeeb1c4 Start bios (version 1.6.3-20120208_175037-oldx86) Find memory size Attempting to find coreboot table Found coreboot table forwarder. Now attempting to find coreboot memory map Add to e820 map: 00000000 00001000 2 Add to e820 map: 00001000 0009f000 1 Add to e820 map: 000c0000 cff30000 1 Add to e820 map: cfff0000 00010000 2 Add to e820 map: e0000000 10000000 2 Add to e820 map: 00000000 20000000 1 Add to e820 map: 00000000 00004000 1 Found mainboard ASUS M5A99X-EVO Found CBFS header at 0xfffffca0 Add to e820 map: 000a0000 00050000 -1 Add to e820 map: 000f0000 00010000 2 Ram Size=0xcfff0000 (0x0000000120000000 high) malloc setup Add to e820 map: cffe0000 00010000 2 init ivt init bda Add to e820 map: 0009fc00 00000400 2 init pic init timer init timer: 01 init timer: 02 init timer: 03 init timer: 04 init timer: 05 init timer: 06 init timer: 07 init timer: 08 init timer: 09 init timer: 10 init timer: 11 init timer: 12 math cp init PCI probe Searching CBFS for prefix etc/extra-pci-roots Found CBFS file cmos_layout.bin Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file config Found CBFS file pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfe70 (detail=0xcffdfee0) PCI device 00:00.0 (vd=1002:5a14 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfdd0 (detail=0xcffdfe40) PCI device 00:11.0 (vd=1002:4393 c=0101) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfd30 (detail=0xcffdfda0) PCI device 00:12.0 (vd=1002:4397 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfc90 (detail=0xcffdfd00) PCI device 00:12.2 (vd=1002:4396 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfbf0 (detail=0xcffdfc60) PCI device 00:13.0 (vd=1002:4397 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfb50 (detail=0xcffdfbc0) PCI device 00:13.2 (vd=1002:4396 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfab0 (detail=0xcffdfb20) PCI device 00:14.0 (vd=1002:4385 c=0c05) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfa10 (detail=0xcffdfa80) PCI device 00:14.1 (vd=1002:439c c=0101) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf970 (detail=0xcffdf9e0) PCI device 00:14.2 (vd=1002:4383 c=0403) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf8d0 (detail=0xcffdf940) PCI device 00:14.3 (vd=1002:439d c=0601) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf830 (detail=0xcffdf8a0) PCI device 00:14.4 (vd=1002:4384 c=0604) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf790 (detail=0xcffdf800) PCI device 00:14.5 (vd=1002:4399 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf6f0 (detail=0xcffdf760) PCI device 00:16.0 (vd=1002:4397 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf650 (detail=0xcffdf6c0) PCI device 00:16.2 (vd=1002:4396 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf5b0 (detail=0xcffdf620) PCI device 00:18.0 (vd=1022:1200 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf510 (detail=0xcffdf580) PCI device 00:18.1 (vd=1022:1201 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf470 (detail=0xcffdf4e0) PCI device 00:18.2 (vd=1022:1202 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf3d0 (detail=0xcffdf440) PCI device 00:18.3 (vd=1022:1203 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf330 (detail=0xcffdf3a0) PCI device 00:18.4 (vd=1022:1204 c=0600) Found 19 PCI devices (max PCI bus is 01) Searching CBFS for prefix bootorder Found CBFS file cmos_layout.bin Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file config Found CBFS file Found 1 cpu(s) max supported 1 cpu(s) init bios32 hhhhahndl_hwpe1 iicq=0crrq1 i01 i==f0rq0f0e0f003=ff540qh=hh‰nhahndl‰ah‰we_ic1p‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰rq‰ i=0hhha‰nhhdla‰n_h‰ew‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰ec‰1piirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_ic1p‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1piirq ‰h==0qahhhhndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰rq‰ i=0hhh‰nhhandl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch7hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1piirq ‰h==0qahhhhndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_ic1p‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch3hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1piirq ‰h==0qahhhhndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i=0 i‰0rq=hahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1prq ‰ih=0h h‰hha‰ndla_hw‰eic‰1p‰rq i=0 i‰0rq=hahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰rq‰ i=0hhh‰nhhandl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0chahh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch9hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch7hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_i‰c1prq ‰ih=0h h‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch6hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch5hh‰nhahand‰lh‰we_ic1p‰irq‰ h=0qh‰hhahndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch2hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_i‰c1prq ‰ih=0h h‰hha‰ndla_hw‰eic‰1p‰rq i=0 i‰0rq=hahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰rq‰ i=0hhh‰nhhandl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰rq‰ i=0hhh‰nhhandl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰rq‰ i=0hhh‰nhhandl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰we‰c1piirq‰ h=0hqh‰hhandla‰_hw‰ec‰1piirq ‰h==0qahhhhndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰ah‰we_ic1p‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1prq ‰ih=0h h‰hha‰ndla_hw‰eic‰1p‰rq i=0 i‰0rq=hahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰rq‰ i=0hhh‰nhhandl‰a_h‰we‰c1pi irq‰h ‰=0rqhhh‰nhhandl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰ah‰we_ic1p‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1prq ‰ih=0h h‰hha‰ndla_hw‰eic‰1p‰rq i=0 i‰0rq=hahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1piirq ‰h==0qahhhhndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch1hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0chfhh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1piirq ‰h==0qahhhhndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_‰ic1pirq‰ =0hqhhhha‰ndl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰ndlahw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ =0hqhhhha‰ndl‰ah‰we_‰ic1pirq‰ h=0hqh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_i‰c1prq ‰ih=0h h‰hha‰ndla_hw‰eic‰1p‰rq i=0 i‰0rq=hahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1prq ‰ih=0h h‰hha‰ndla_hw‰eic‰1p‰rq i=0 i‰0rq=hahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_ic1p‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1piirq ‰h==0qahhhhndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_ic1p‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1piirq ‰h==0qahhhhndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhahnd‰la‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_i‰c1prq ‰ih=0h h‰hha‰ndla_hw‰eic‰1p‰rq i=0 i‰0rq=hahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ h=0qh‰hhahndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1piirq ‰h==0qahhhhndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1piirq ‰h==0qahhhhndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰l‰we_hpic‰1r‰q i0 i=‰h0rq=hhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_i‰c1prq ‰ih=0h h‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch5hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch4hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch2hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch1hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1p‰rq i0 i‰=hrqh=h‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch0hh‰nhahand‰lh‰we_ic INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- Issuing SOFT_RESET... coreboot-4.0-2039-gd16b170 Wed Feb 8 17:50:46 CET 2012 starting... zomg1 zomg2 cimx/rd890 early.c nb_Poweron_Init() Start cimx/rd890 early.c nb_Poweron_Init() End. return status=0 zomg3 AmdHtInit status: 0 zomg4 BSP Family_Model: 00100fa0 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000 microcode: patch id to apply = 0x010000bf microcode: updated to patch id = 0x010000bf success POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 SB900 - Early.c - get_sbdn - Start. SB900 - Early.c - get_sbdn - End. cpuSetAMDPCI 00 done Prep FID/VID Node:00 P-state info in MSRC001_0064 is invalid !!! P-state info in MSRc0010064 is invalid !!! F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001016 F3xDC: 0000611a POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 POST: 0x37 started ap apicid: PPPOPSPOOOSSSTOT:STT T:::0 : 0 0x0x0xxx3333300000 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000013254 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000034251}}}}} --------------- * AmmmmmiiiiiPcc ccc0rrrrrooo1oocccccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000 startmmmmmediiiiiccc ccr rrrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff mmmmm* iiiiicccAccPrrrrroooo oc0ccccoooo2odddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss stcccccpappppuuuuruStSSSSeeeeeettdtttAAAAA MM MMMDDDDDMMMMMSSSSSRRRRR * AP 0d3ddddooooonnnnneeeee siiiiitninnnnaiirtiit_tttt___ef_diffffiii di vddddvvvviiiididdd_d__s__stssstatttgaaaaggggeeeee2222 2 a aapaaippppciiiiicccciiididdd:d:: :: 0 05000 1324 * AP 04started * AP 05started POST: 0x38 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 POST: 0x39 POST: 0x3a End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 POST: 0x3b fill_mem_ctrl() POST: 0x40 raminit_amdmct() raminit_amdmct begin: SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=c DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=10 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=10 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 1000 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDGetTCL_D: DIMMCASL 4 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 1000 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: e00000 Node: 00 base: 03 limit: 21fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:e00000 CPUMemTyping: Bottom32bIO:e00000 CPUMemTyping: Bottom40bIO:2200000 mctAutoInitMCT_D: DQSTiming_D SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. TrainRcvrEn: Status 1100 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 1100 InterleaveNodes_D: ErrStatus 0 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 1100 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D All Done raminit_amdmct end: POST: 0x41 POST: 0x42 v_esp=000cbef8 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1310720 bytes), entry @ 0x200000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-4.0-2039-gd16b170 Wed Feb 8 17:50:46 CET 2012 booting... POST: 0x40 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Mainboard ASUS M5A99X-EVO Enable. dev=0x00239e2c scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=5 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled CPU: APIC: 04 enabled CPU: APIC: 05 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled POST: 0x25 PCI: Using configuration type 1 PCI: 00:00.0 [1002/5a14] ops PCI: 00:00.0 [1002/5a14] enabled Capability: type 0x08 @ 0xf0 flags: 0xa803 Capability: type 0x08 @ 0xf0 Capability: type 0x08 @ 0xc4 flags: 0x0281 PCI: pci_scan_bus for bus 00 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff PCI: pci_scan_bus upper limit too big. Using 0xff. POST: 0x24 PCI: 00:00.0 [1002/5a14] enabled PCI: 00:11.0 [1002/4393] enabled PCI: 00:12.0 [1002/4397] enabled PCI: 00:12.2 [1002/4396] enabled PCI: 00:13.0 [1002/4397] enabled PCI: 00:13.2 [1002/4396] enabled PCI: 00:14.0 [1002/4385] enabled PCI: 00:14.1 [1002/439c] enabled PCI: 00:14.2 [1002/4383] enabled PCI: 00:14.3 [1002/439d] enabled PCI: 00:14.4 [1002/4384] enabled PCI: 00:14.5 [1002/4399] enabled PCI: 00:16.0 [1002/4397] enabled PCI: 00:16.2 [1002/4396] enabled PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:14.4 PCI: pci_scan_bus for bus 01 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 do_pci_scan_bridge returns max 1 PCI: pci_scan_bus returning with max=001 POST: 0x55 PCI: pci_scan_bus returning with max=001 POST: 0x55 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done POST: 0x66 Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources APIC: 02 missing read_resources APIC: 03 missing read_resources APIC: 04 missing read_resources APIC: 05 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:14.4 read_resources bus 1 link: 0 PCI: 00:14.4 read_resources bus 1 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 PCI: 00:00.0 missing read_resources PCI: 00:02.0 missing read_resources PCI: 00:0d.0 missing read_resources PCI: 00:11.0 missing read_resources PCI: 00:12.0 missing read_resources PCI: 00:12.2 missing read_resources PCI: 00:13.0 missing read_resources PCI: 00:13.2 missing read_resources PCI: 00:14.0 missing read_resources PCI: 00:14.1 missing read_resources PCI: 00:14.2 missing read_resources PCI: 00:14.3 missing read_resources PCI: 00:14.5 missing read_resources PCI: 00:15.0 missing read_resources PCI: 00:15.1 missing read_resources PCI: 00:15.2 missing read_resources PCI: 00:15.3 missing read_resources PCI: 00:16.0 missing read_resources PCI: 00:16.2 missing read_resources PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI: 00:18.0 read_resources bus 0 link: 3 PCI: 00:18.0 read_resources bus 0 link: 3 done PCI: 00:18.0 read_resources bus 0 link: 4 PCI: 00:18.0 read_resources bus 0 link: 4 done PCI: 00:18.0 read_resources bus 0 link: 5 PCI: 00:18.0 read_resources bus 0 link: 5 done PCI: 00:18.0 read_resources bus 0 link: 6 PCI: 00:18.0 read_resources bus 0 link: 6 done PCI: 00:18.0 read_resources bus 0 link: 7 PCI: 00:18.0 read_resources bus 0 link: 7 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110a8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110a0 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 1200 index fc PCI: 00:11.0 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.3 PCI: 00:14.4 PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:02.0 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0d.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.2 PCI: 00:13.0 PCI: 00:13.2 PCI: 00:14.0 child on link 0 I2C: 00:50 I2C: 00:50 I2C: 00:51 I2C: 00:52 I2C: 00:53 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 child on link 0 PNP: 002e.0 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:14.4 PCI: 00:14.5 PCI: 00:14.6 PCI: 00:15.0 PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: 00:16.0 PCI: 00:16.2 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:11.0 20 * [0x0 - 0xf] io PCI: 00:14.1 20 * [0x10 - 0x1f] io PCI: 00:11.0 10 * [0x20 - 0x27] io PCI: 00:11.0 18 * [0x28 - 0x2f] io PCI: 00:14.1 10 * [0x30 - 0x37] io PCI: 00:14.1 18 * [0x38 - 0x3f] io PCI: 00:11.0 14 * [0x40 - 0x43] io PCI: 00:11.0 1c * [0x44 - 0x47] io PCI: 00:14.1 14 * [0x48 - 0x4b] io PCI: 00:14.1 1c * [0x4c - 0x4f] io PCI: 00:18.0 compute_resources_io: base: 50 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 10d8 * [0x0 - 0xfff] io PCI_DOMAIN: 0000 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.0 fc * [0x0 - 0xff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI: 00:14.2 10 * [0x4000000 - 0x4003fff] mem PCI: 00:12.0 10 * [0x4004000 - 0x4004fff] mem PCI: 00:13.0 10 * [0x4005000 - 0x4005fff] mem PCI: 00:14.5 10 * [0x4006000 - 0x4006fff] mem PCI: 00:16.0 10 * [0x4007000 - 0x4007fff] mem PCI: 00:11.0 24 * [0x4008000 - 0x40083ff] mem PCI: 00:12.2 10 * [0x4008400 - 0x40084ff] mem PCI: 00:13.2 10 * [0x4008500 - 0x40085ff] mem PCI: 00:16.2 10 * [0x4008600 - 0x40086ff] mem PCI: 00:18.0 compute_resources_mem: base: 4008700 size: 4100000 align: 26 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done PCI: 00:18.0 10b0 * [0x0 - 0x40fffff] mem PCI: 00:18.3 94 * [0x8000000 - 0xbffffff] mem PCI: 00:18.0 10b8 * [0xc000000 - 0xc0fffff] prefmem PCI_DOMAIN: 0000 compute_resources_mem: base: c100000 size: c100000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:11.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:12.2 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:13.2 constrain_resources: PCI: 00:14.0 constrain_resources: PCI: 00:14.1 constrain_resources: PCI: 00:14.2 constrain_resources: PCI: 00:14.3 constrain_resources: PCI: 00:14.4 constrain_resources: PCI: 00:14.5 constrain_resources: PCI: 00:16.0 constrain_resources: PCI: 00:16.2 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:0d.0 constrain_resources: PCI: 00:11.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:12.2 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:13.2 constrain_resources: PCI: 00:14.0 constrain_resources: I2C: 00:50 constrain_resources: I2C: 00:51 constrain_resources: I2C: 00:52 constrain_resources: I2C: 00:53 constrain_resources: PCI: 00:14.1 constrain_resources: PCI: 00:14.2 constrain_resources: PCI: 00:14.3 constrain_resources: PNP: 002e.2 skipping PNP: 002e.2@60 fixed resource, size=0! skipping PNP: 002e.2@70 fixed resource, size=0! constrain_resources: PNP: 002e.3 skipping PNP: 002e.3@60 fixed resource, size=0! skipping PNP: 002e.3@70 fixed resource, size=0! constrain_resources: PNP: 002e.5 skipping PNP: 002e.5@60 fixed resource, size=0! skipping PNP: 002e.5@62 fixed resource, size=0! skipping PNP: 002e.5@70 fixed resource, size=0! skipping PNP: 002e.5@72 fixed resource, size=0! constrain_resources: PNP: 002e.b skipping PNP: 002e.b@60 fixed resource, size=0! skipping PNP: 002e.b@70 fixed resource, size=0! constrain_resources: PCI: 00:14.5 constrain_resources: PCI: 00:15.0 constrain_resources: PCI: 00:15.1 constrain_resources: PCI: 00:15.2 constrain_resources: PCI: 00:15.3 constrain_resources: PCI: 00:16.0 constrain_resources: PCI: 00:16.2 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00000000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit dfffffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:0 size:1000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 10d8 * [0x0 - 0xfff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1000 size: 1000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:0 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 00:11.0 20 * [0x0 - 0xf] io Assigned: PCI: 00:14.1 20 * [0x10 - 0x1f] io Assigned: PCI: 00:11.0 10 * [0x20 - 0x27] io Assigned: PCI: 00:11.0 18 * [0x28 - 0x2f] io Assigned: PCI: 00:14.1 10 * [0x30 - 0x37] io Assigned: PCI: 00:14.1 18 * [0x38 - 0x3f] io Assigned: PCI: 00:11.0 14 * [0x40 - 0x43] io Assigned: PCI: 00:11.0 1c * [0x44 - 0x47] io Assigned: PCI: 00:14.1 14 * [0x48 - 0x4b] io Assigned: PCI: 00:14.1 1c * [0x4c - 0x4f] io PCI: 00:18.0 allocate_resources_io: next_base: 50 size: 1000 align: 12 gran: 12 done PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:18.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:18.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:c100000 align:26 gran:0 limit:dfffffff Assigned: PCI: 00:18.0 10b0 * [0xd0000000 - 0xd40fffff] mem Assigned: PCI: 00:18.3 94 * [0xd8000000 - 0xdbffffff] mem Assigned: PCI: 00:18.0 10b8 * [0xdc000000 - 0xdc0fffff] prefmem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: dc100000 size: c100000 align: 26 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:dc000000 size:100000 align:20 gran:20 limit:dfffffff Assigned: PCI: 00:00.0 fc * [0xdc000000 - 0xdc0000ff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: dc000100 size: 100000 align: 20 gran: 20 done PCI: 00:14.4 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:14.4 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:d0000000 size:4100000 align:26 gran:20 limit:dfffffff Assigned: PCI: 00:18.3 94 * [0xd0000000 - 0xd3ffffff] mem Assigned: PCI: 00:14.2 10 * [0xd4000000 - 0xd4003fff] mem Assigned: PCI: 00:12.0 10 * [0xd4004000 - 0xd4004fff] mem Assigned: PCI: 00:13.0 10 * [0xd4005000 - 0xd4005fff] mem Assigned: PCI: 00:14.5 10 * [0xd4006000 - 0xd4006fff] mem Assigned: PCI: 00:16.0 10 * [0xd4007000 - 0xd4007fff] mem Assigned: PCI: 00:11.0 24 * [0xd4008000 - 0xd40083ff] mem Assigned: PCI: 00:12.2 10 * [0xd4008400 - 0xd40084ff] mem Assigned: PCI: 00:13.2 10 * [0xd4008500 - 0xd40085ff] mem Assigned: PCI: 00:16.2 10 * [0xd4008600 - 0xd40086ff] mem PCI: 00:18.0 allocate_resources_mem: next_base: d4008700 size: 4100000 align: 26 gran: 20 done PCI: 00:14.4 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:14.4 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:18.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:18.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 split: 64K table at =cfff0000 0: mmio_basek=00340000, basek=00400000, limitk=00880000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:18.0 10d8 <- [0x0000000000 - 0x0000000fff] size 0x00001000 gran 0x0c io PCI: 00:18.0 10b8 <- [0x00dc000000 - 0x00dc0fffff] size 0x00100000 gran 0x14 prefmem PCI: 00:18.0 10b0 <- [0x00d0000000 - 0x00d40fffff] size 0x04100000 gran 0x14 mem PCI: 00:18.0 110d0 <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c io PCI: 00:18.0 110a8 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 prefmem PCI: 00:18.0 110a0 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:00.0 fc <- [0x00dc000000 - 0x00dc0000ff] size 0x00000100 gran 0x08 prefmem PCI: 00:11.0 10 <- [0x0000000020 - 0x0000000027] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000000040 - 0x0000000043] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000000028 - 0x000000002f] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000000044 - 0x0000000047] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000000000 - 0x000000000f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00d4008000 - 0x00d40083ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00d4004000 - 0x00d4004fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00d4008400 - 0x00d40084ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00d4005000 - 0x00d4005fff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00d4008500 - 0x00d40085ff] size 0x00000100 gran 0x08 mem PCI: 00:14.1 10 <- [0x0000000030 - 0x0000000037] size 0x00000008 gran 0x03 io PCI: 00:14.1 14 <- [0x0000000048 - 0x000000004b] size 0x00000004 gran 0x02 io PCI: 00:14.1 18 <- [0x0000000038 - 0x000000003f] size 0x00000008 gran 0x03 io PCI: 00:14.1 1c <- [0x000000004c - 0x000000004f] size 0x00000004 gran 0x02 io PCI: 00:14.1 20 <- [0x0000000010 - 0x000000001f] size 0x00000010 gran 0x04 io PCI: 00:14.2 10 <- [0x00d4000000 - 0x00d4003fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:14.4 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:14.4 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:14.5 10 <- [0x00d4006000 - 0x00d4006fff] size 0x00001000 gran 0x0c mem PCI: 00:16.0 10 <- [0x00d4007000 - 0x00d4007fff] size 0x00001000 gran 0x0c mem PCI: 00:16.2 10 <- [0x00d4008600 - 0x00d40086ff] size 0x00000100 gran 0x08 mem PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 1000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base d0000000 size c100000 align 26 gran 0 limit dfffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size cff40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base 100000000 size 120000000 align 0 gran 0 limit 0 flags e0004200 index 30 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 1000 align 12 gran 12 limit ffff flags 60080100 index 10d8 PCI: 00:18.0 resource base dc000000 size 100000 align 20 gran 20 limit dfffffff flags 60081200 index 10b8 PCI: 00:18.0 resource base d0000000 size 4100000 align 26 gran 20 limit dfffffff flags 60080200 index 10b0 PCI: 00:18.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080100 index 110d0 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081200 index 110a8 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080200 index 110a0 PCI: 00:00.0 PCI: 00:00.0 resource base dc000000 size 100 align 8 gran 8 limit dfffffff flags 60001200 index fc PCI: 00:11.0 PCI: 00:11.0 resource base 20 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:11.0 resource base 40 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:11.0 resource base 28 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:11.0 resource base 44 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:11.0 resource base d4008000 size 400 align 10 gran 10 limit dfffffff flags 60000200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base d4004000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base d4008400 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base d4005000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base d4008500 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.1 resource base 30 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:14.1 resource base 48 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:14.1 resource base 38 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:14.1 resource base 4c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:14.1 resource base 10 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base d4000000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 10 PCI: 00:14.3 PCI: 00:14.4 PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base d4006000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base d4007000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base d4008600 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base d0000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 PCI: 00:18.4 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:02.0 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0d.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.2 PCI: 00:13.0 PCI: 00:13.2 PCI: 00:14.0 child on link 0 I2C: 00:50 I2C: 00:50 I2C: 00:51 I2C: 00:52 I2C: 00:53 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 child on link 0 PNP: 002e.0 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:14.4 PCI: 00:14.5 PCI: 00:14.6 PCI: 00:15.0 PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: 00:16.0 PCI: 00:16.2 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base d8000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 PCI: 00:18.4 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/843e PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/843e PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1043/843e PCI: 00:18.4 cmd <- 00 PCI: 00:00.0 cmd <- 02 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 cmd <- 02 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 cmd <- 02 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 cmd <- 0f PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 cmd <- 02 PCI: 00:16.0 cmd <- 02 PCI: 00:16.2 cmd <- 02 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00006000, offset=0x00200000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 00 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #0 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 1. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #1 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 01 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x01 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #1 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 2. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #2 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 02 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x02 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #2 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 3. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #3 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 03 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x03 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #3 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 4. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #4 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 04 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x04 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #4 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 5. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #5 Waiting for 1 CPUS to stop CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 05 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x05 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #5 initialized All AP CPUs stopped SB900 - Early.c - sb_After_Pci_Init - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_After_Pci_Init - End. SB900 - Early.c - sb_Mid_Post_Init - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_Mid_Post_Init - End. PCI: 00:18.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init PCI: 00:00.0 init IOAPIC: Initializing IOAPIC at 0xdc000000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x01 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC not responding. PCI: 00:11.0 init PCI: 00:12.0 init PCI: 00:12.2 init PCI: 00:13.0 init PCI: 00:13.2 init PCI: 00:14.0 init PCI: 00:14.1 init PCI: 00:14.2 init PCI: 00:14.3 init PCI: 00:14.5 init PCI: 00:16.0 init PCI: 00:16.2 init PCI: 00:18.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 APIC: 01: enabled 1 APIC: 02: enabled 1 APIC: 03: enabled 1 APIC: 04: enabled 1 APIC: 05: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 POST: 0x89 Initializing CBMEM area to 0xcfff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to cfff0200...ok High Tables Base is cfff0000. POST: 0x9a SB900 - Early.c - sb_Late_Post - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_Late_Post - End. Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done. Adding CBMEM entry as no. 2 Writing IRQ routing tables to 0xcfff0400...write_pirq_routing_table done. PIRQ table: 48 bytes. POST: 0x9b Wrote the mp table end at: 000f0410 - 000f055c Adding CBMEM entry as no. 3 Wrote the mp table end at: cfff1410 - cfff155c MP table: 348 bytes. POST: 0x9c Adding CBMEM entry as no. 4 ACPI: Writing ACPI tables at cfff2400... ACPI: * HPET at cfff24c8 ACPI: added table 1/32, length now 40 ACPI: * MADT at cfff2500 ACPI: added table 2/32, length now 44 ACPI: * SRAT at cfff2580 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=0033fd00 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00480000 ACPI: added table 3/32, length now 48 ACPI: * SLIT at cfff2688 ACPI: added table 4/32, length now 52 ACPI: * SSDT at cfff26c0 ACPI: added table 5/32, length now 56 ACPI: * SSDT for PState at cfff2cf5 ACPI: * DSDT at cfff2cf8 ACPI: * DSDT @ cfff2cf8 Length 288b ACPI: * FACS at cfff5588 ACPI: * FADT at cfff55c8 ACPI_BLK_BASE: 0x0800 ACPI: added table 6/32, length now 60 ACPI: done. ACPI tables: 12988 bytes. Adding CBMEM entry as no. 5 smbios_write_tables: cfffd800 Root Device (ASUS M5A99X-EVO Mainboard) APIC_CLUSTER: 0 (AMD FAM10 Root Complex) APIC: 00 (socket AM3) PCI_DOMAIN: 0000 (AMD FAM10 Root Complex) PCI: 00:18.0 (AMD FAM10 Northbridge) PCI: 00:00.0 (ATI rd890) PCI: 00:00.1 (ATI rd890) PCI: 00:02.0 (ATI rd890) PCI: 00:03.0 (ATI rd890) PCI: 00:04.0 (ATI rd890) PCI: 00:05.0 (ATI rd890) PCI: 00:06.0 (ATI rd890) PCI: 00:07.0 (ATI rd890) PCI: 00:08.0 (ATI rd890) PCI: 00:09.0 (ATI rd890) PCI: 00:0a.0 (ATI rd890) PCI: 00:0b.0 (ATI rd890) PCI: 00:0c.0 (ATI rd890) PCI: 00:0d.0 (ATI rd890) PCI: 00:11.0 (ATI SB900) PCI: 00:12.0 (ATI SB900) PCI: 00:12.2 (ATI SB900) PCI: 00:13.0 (ATI SB900) PCI: 00:13.2 (ATI SB900) PCI: 00:14.0 (ATI SB900) I2C: 00:50 () I2C: 00:51 () I2C: 00:52 () I2C: 00:53 () PCI: 00:14.1 (ATI SB900) PCI: 00:14.2 (ATI SB900) PCI: 00:14.3 (ATI SB900) PNP: 002e.0 (ITE IT8721F Super I/O) PNP: 002e.1 (ITE IT8721F Super I/O) PNP: 002e.2 (ITE IT8721F Super I/O) PNP: 002e.3 (ITE IT8721F Super I/O) PNP: 002e.5 (ITE IT8721F Super I/O) PNP: 002e.6 (ITE IT8721F Super I/O) PNP: 002e.7 (ITE IT8721F Super I/O) PNP: 002e.8 (ITE IT8721F Super I/O) PNP: 002e.9 (ITE IT8721F Super I/O) PNP: 002e.a (ITE IT8721F Super I/O) PNP: 002e.b (ITE IT8721F Super I/O) PCI: 00:14.4 (ATI SB900) PCI: 00:14.5 (ATI SB900) PCI: 00:14.6 (ATI SB900) PCI: 00:15.0 (ATI SB900) PCI: 00:15.1 (ATI SB900) PCI: 00:15.2 (ATI SB900) PCI: 00:15.3 (ATI SB900) PCI: 00:16.0 (ATI SB900) PCI: 00:16.2 (ATI SB900) PCI: 00:18.1 (AMD FAM10 Northbridge) PCI: 00:18.2 (AMD FAM10 Northbridge) PCI: 00:18.3 (AMD FAM10 Northbridge) PCI: 00:18.4 (AMD FAM10 Northbridge) APIC: 01 () APIC: 02 () APIC: 03 () APIC: 04 () APIC: 05 () PCI: 00:00.0 () PCI: 00:11.0 () PCI: 00:12.0 () PCI: 00:12.2 () PCI: 00:13.0 () PCI: 00:13.2 () PCI: 00:14.0 () PCI: 00:14.1 () PCI: 00:14.2 () PCI: 00:14.3 () PCI: 00:14.4 () PCI: 00:14.5 () PCI: 00:16.0 () PCI: 00:16.2 () PCI: 00:18.0 () PCI: 00:18.1 () PCI: 00:18.2 () PCI: 00:18.3 () PCI: 00:18.4 () SMBIOS tables: 269 bytes. POST: 0x9d Adding CBMEM entry as no. 6 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 4fde New low_table_end: 0x00000518 Now going to write high coreboot table at 0xcfffe000 rom_table_end = 0xcfffe000 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0xcfffe000 to 0xd0000000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-00000000cffeffff: RAM 3. 00000000cfff0000-00000000cfffffff: CONFIGURATION TABLES 4. 00000000e0000000-00000000efffffff: RESERVED 5. 0000000100000000-000000021fffffff: RAM Wrote coreboot table at: cfffe000 - cfffe1e0 checksum 729e coreboot table: 480 bytes. POST: 0x9e POST: 0x9d Multiboot Information structure has been written. 0. FREE SPACE d0000000 00000000 1. GDT cfff0200 00000200 2. IRQ TABLE cfff0400 00001000 3. SMP TABLE cfff1400 00001000 4. ACPI cfff2400 0000b400 5. SMBIOS cfffd800 00000800 6. COREBOOT cfffe000 00002000 Searching for fallback/payload Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Got a payload Loading segment from rom address 0xffc43f38 data (compression=1) New segment dstaddr 0xed150 memsize 0x12eb0 srcaddr 0xffc43f70 filesize 0x9759 (cleaned up) New segment addr 0xed150 size 0x12eb0 offset 0xffc43f70 filesize 0x9759 Loading segment from rom address 0xffc43f54 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000ed150 memsz: 0x0000000000012eb0 filesz: 0x0000000000009759 lb: [0x0000000000200000, 0x0000000000340000) Post relocation: addr: 0x00000000000ed150 memsz: 0x0000000000012eb0 filesz: 0x0000000000009759 using LZMA [ 0x000ed150, 00100000, 0x00100000) <- ffc43f70 dest 000ed150, end 00100000, bouncebuffer cfd70000 Loaded segments Jumping to boot code at fc63c POST: 0xf8 entry = 0x000fc63c lb_start = 0x00200000 lb_size = 0x00140000 adjust = 0xcfcb0000 buffer = 0xcfd70000 elf_boot_notes = 0x0023b1c4 adjusted_boot_notes = 0xcfeeb1c4 Start bios (version 1.6.3-20120208_175037-oldx86) Find memory size Attempting to find coreboot table Found coreboot table forwarder. Now attempting to find coreboot memory map Add to e820 map: 00000000 00001000 2 Add to e820 map: 00001000 0009f000 1 Add to e820 map: 000c0000 cff30000 1 Add to e820 map: cfff0000 00010000 2 Add to e820 map: e0000000 10000000 2 Add to e820 map: 00000000 20000000 1 Add to e820 map: 00000000 00004000 1 Found mainboard ASUS M5A99X-EVO Found CBFS header at 0xfffffca0 Add to e820 map: 000a0000 00050000 -1 Add to e820 map: 000f0000 00010000 2 Ram Size=0xcfff0000 (0x0000000120000000 high) malloc setup Add to e820 map: cffe0000 00010000 2 init ivt init bda Add to e820 map: 0009fc00 00000400 2 init pic init timer init timer: 01 init timer: 02 init timer: 03 init timer: 04 init timer: 05 init timer: 06 init timer: 07 init timer: 08 init timer: 09 init timer: 10 init timer: 11 init timer: 12 math cp init PCI probe Searching CBFS for prefix etc/extra-pci-roots Found CBFS file cmos_layout.bin Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file config Found CBFS file pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfe70 (detail=0xcffdfee0) PCI device 00:00.0 (vd=1002:5a14 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfdd0 (detail=0xcffdfe40) PCI device 00:11.0 (vd=1002:4393 c=0101) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfd30 (detail=0xcffdfda0) PCI device 00:12.0 (vd=1002:4397 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfc90 (detail=0xcffdfd00) PCI device 00:12.2 (vd=1002:4396 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfbf0 (detail=0xcffdfc60) PCI device 00:13.0 (vd=1002:4397 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfb50 (detail=0xcffdfbc0) PCI device 00:13.2 (vd=1002:4396 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfab0 (detail=0xcffdfb20) PCI device 00:14.0 (vd=1002:4385 c=0c05) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfa10 (detail=0xcffdfa80) PCI device 00:14.1 (vd=1002:439c c=0101) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf970 (detail=0xcffdf9e0) PCI device 00:14.2 (vd=1002:4383 c=0403) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf8d0 (detail=0xcffdf940) PCI device 00:14.3 (vd=1002:439d c=0601) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf830 (detail=0xcffdf8a0) PCI device 00:14.4 (vd=1002:4384 c=0604) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf790 (detail=0xcffdf800) PCI device 00:14.5 (vd=1002:4399 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf6f0 (detail=0xcffdf760) PCI device 00:16.0 (vd=1002:4397 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf650 (detail=0xcffdf6c0) PCI device 00:16.2 (vd=1002:4396 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf5b0 (detail=0xcffdf620) PCI device 00:18.0 (vd=1022:1200 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf510 (detail=0xcffdf580) PCI device 00:18.1 (vd=1022:1201 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf470 (detail=0xcffdf4e0) PCI device 00:18.2 (vd=1022:1202 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf3d0 (detail=0xcffdf440) PCI device 00:18.3 (vd=1022:1203 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf330 (detail=0xcffdf3a0) PCI device 00:18.4 (vd=1022:1204 c=0600) Found 19 PCI devices (max PCI bus is 01) Searching CBFS for prefix bootorder Found CBFS file cmos_layout.bin Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file config Found CBFS file Found 1 cpu(s) max supported 1 cpu(s) init bios32 hhphnhh‰a(hhhandl¸ahwe_ic1phrqa in i=0rq=fd0fl005e4qf09=_ch4h=h‰hwhaapnd‰e_‰liw‰pchc11i‰ir‰ ‰0iq=hhrhhaqnd‰e_‰l=w‰p0hc 1i‰ ir‰ =‰0qh=hh‰nahand‰le_‰wp‰h‰1ic‰ irq=0‰fhq=hahh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1 ‰ir=0q‰h0=fahhhan‰dle‰_‰phw‰ic1 ir‰0hq=hahh‰ndale_‰wp‰hic‰1i‰r =0q‰h0=fhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lw‰phi‰c1‰ir =0‰qfh=hhah‰nd‰ae‰_l‰wphic1‰ ir‰0q=hhhhaand‰e_‰lw‰hpi‰c1ir ‰h0q=ahhhan‰dle‰_‰phw‰ic1 ir‰0hq=hahh‰ndale_‰wp‰hic‰1i‰r =0q‰h0=fhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lw‰phi‰c1‰ir =0‰qfh=hhah‰nd‰ae‰_l‰wphic1‰ ir‰0q=hhhhaand‰e_‰lw‰hp‰c1i i‰rq=‰0q=hha‰hh‰ndale_‰hwp‰c1‰i‰r i‰q=0hhhhand‰le_‰wp‰h‰1ic ir‰h0q=ahhhand‰le_‰wp‰h‰1ic‰ irq=0‰fhq=hahh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lw‰phi‰c1‰ir =0‰qfh=hhah‰nd‰ae‰_l‰wphic1‰ ir‰0q=hhhhaand‰e_‰lw‰hpi‰c1ir ‰h0q=ahhhan‰dle‰_‰phw‰ic1 ir‰0hq=hahh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰andle_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=h wp‰c1‰ii‰r ‰=q0hhhh‰ndale‰_hw‰p‰1ic ir‰h0q=ahhhand‰le_‰wp‰h‰1ic‰ irq=0‰fhq=hahhha‰ndl‰e_awpnh‰cd1‰ii‰r l‰=0eqhhh_hnhd‰ae‰_lwwpph‰ci1‰ii‰r c‰=01qhhh hnid‰ae‰_lrwpqh‰c=1‰ii‰r 0‰=0 qhhh hnd‰ale‰_‰phw‰ic1 ir‰0hq=hahh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰andle_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰h0q=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰andle_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lw‰phi‰c1‰ir =0‰qfh=hhah‰nd‰ae‰_l‰wphic1‰ ir‰0q=hhhhaand‰e_‰lw‰hp‰c1i i‰rq=‰0q=hha‰hh‰ndale_‰hwp‰c1‰i‰r i‰q=0hhhhand‰le_‰wp‰h‰1ic ir‰h0q=ahhhand‰le_‰wp‰h‰1ic‰ irq=0‰fhq=hahh‰ndale_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰andle_‰wp‰hic‰1i‰r =0q‰fh0=hahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰c1‰i i‰r=‰0qh=hh‰nahand‰e_‰lw‰phi‰c1‰ir =0‰qfh=hhah‰nd‰ae‰_l‰wph‰ic1 ir‰0q=hahhhand‰_‰le‰wph‰ic1 ir‰0q=hahhhand‰_‰leh‰wp‰c1i i‰r=‰0qh=hhn‰ah‰ndale_‰wp‰hc‰1i ‰ir‰=0qhhhhand‰e_‰lw‰ph‰c1i‰ irq=0‰fq=hahhhand‰_‰leh‰wp‰c1i i‰r=‰0qh=hhn‰ah‰ndale_‰wp‰hc‰1i ‰ir‰=0qhhhhand‰e_‰lw‰ph‰c1i‰ irq=0‰fq=hahhhand‰_‰leh‰wp‰c1i i‰rq=‰0q=hha‰hh‰ndale_‰wp‰hc‰1i ‰ir‰=0qhhhhand‰e_‰lw‰phi‰c1‰ir =0‰qh=hfha‰hn‰dae_l‰hwp‰c1‰ii‰ rq‰=0hqhh‰nahand‰e_‰lw‰ph‰c1i‰ irq=0‰fq=hahhhand‰_‰le‰wph‰ic1 ir‰0q=hahhhand‰_‰leh‰wp‰c1i i‰rq=‰0q=hha‰hh‰ndale_‰wp‰hc‰1i ‰ir‰=0qhhhhand‰e_‰lw‰phi‰c1‰ir =0‰qfh=hhah‰d‰anl‰e_‰wphic‰1 i‰r‰0q=hhhh‰andle_‰wp‰hic‰1i‰r =0q‰h0=fhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰e_‰lhw‰pc‰1iir ‰=h0qhahhnda‰le_‰wp‰hc‰i1‰ir q=‰0hqh=h‰haa‰nd‰e_lhwp‰ic1‰ir‰ ‰0q=hhhh‰andle_‰wp‰hic‰1i‰r =0q‰fh0=ha ir ‰0hq=hhahan‰de‰_l‰wphic1‰ ir‰=0hqhhhaand‰e_‰lhw‰pc‰1i‰ir ‰q=0hhhhand‰le_‰hwp‰c1‰i i‰r=‰0qh=hhh‰na‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ir‰ q=‰0hq=hh‰aha‰nd‰e_lhwp‰ic1‰ ir‰0hq=hhhand‰ale‰_w‰ph‰c1i ir‰q=0hhhhaand‰le_‰wp‰hic‰1i‰r ‰=0qhhhh‰andle_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰ndale_‰hwp‰ic1‰ir‰ q=‰0hq=hh‰aha‰nd‰e_lhwp‰ic1‰ ir‰0hq=hhhand‰ale‰_w‰ph‰c1i ir‰q=0hhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰andle_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰ndale_‰hwp‰ic1‰ir‰ q=‰0hq=hh‰aha‰nd‰e_lhwp‰ic1‰ ir‰0hq=hhhand‰ale‰_w‰ph‰c1i ir‰q=0hhhhaand‰le_‰wp‰hic‰1i‰r ‰=0qhhhh‰andle_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ir‰ q=‰0hq=hh‰aha‰nd‰e_lhwp‰ic1‰ ir‰0hq=hhhand‰ale‰_w‰ph‰c1i ir‰q=0hhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰andle_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ir‰ q=‰0hq=hh‰aha‰nd‰e_lhwp‰ic1‰ ir‰0hq=hhhand‰ale‰_w‰ph‰c1i ir‰q=0hhhhaand‰le_‰wp‰hic‰1i‰r ‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ir‰ q=‰0hq=hh‰aha‰nd‰e_lhwp‰ic1‰ ir‰0hq=hhhand‰ale‰_w‰ph‰c1i ir‰q=0hhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_lh‰wp‰c1i ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ q=‰0hq=hh‰ah‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_lh‰wp‰c1i ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_lh‰wp‰c1i ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_lh‰wp‰c1i ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ q=‰0hq=hh‰ah‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_lh‰wp‰c1i ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ q=‰0hq=hh‰ah‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_lh‰wp‰c1i ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ q=‰0hq=hh‰ah‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_lh‰wp‰c1i ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ir‰ q=‰0hq=hh‰aha‰nd‰e_lhwp‰ic1‰ ir‰0hq=hhhand‰ae‰_lh‰wp‰c1i ir‰q=0hhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhhand‰ae‰_l‰wph‰ic1 ir‰=0hqhhhaand‰le_‰wp‰hc‰1i ‰ir‰=0qhhhh‰ndale_‰hwp‰ic1‰ir‰ =‰0qhh=hh‰an‰nda‰le_hwp‰ic1‰ ir‰0hq=hhh INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- Issuing SOFT_RESET... coreboot-4.0-2039-gd16b170 Wed Feb 8 17:50:46 CET 2012 starting... zomg1 zomg2 cimx/rd890 early.c nb_Poweron_Init() Start cimx/rd890 early.c nb_Poweron_Init() End. return status=0 zomg3 AmdHtInit status: 0 zomg4 BSP Family_Model: 00100fa0 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000 microcode: patch id to apply = 0x010000bf microcode: updated to patch id = 0x010000bf success POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 SB900 - Early.c - get_sbdn - Start. SB900 - Early.c - get_sbdn - End. cpuSetAMDPCI 00 done Prep FID/VID Node:00 P-state info in MSRC001_0064 is invalid !!! P-state info in MSRc0010064 is invalid !!! F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001016 F3xDC: 0000611a POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 POST: 0x37 started ap apicid: PPPPPOOOOOSSSSSTTTTT::::: 00000xxxxx3333300000 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000043521 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000012543}}}}} --------------- * AmmmmmiiiiiPcc cccrrrrr0oo1ooocccccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000 startemmmmmidiiiicccc cr rrrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff mmmmm*i iiiiccccAcrPrrrroooo oc0ccccooooo2dddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss stcccccpappppuuuuruStSSSSeeeeeettdtttAAAAA MM MMMDDDDDMMMMMSSSSSRRRRR * AP 0 d3ddddooooonnnnneeeee siiiiitninnnnaiirtiit_tttt___ef_diffffiii di vddddvvvviiiididdd_d_s___stsssattttaaaagggggeeee2e22 22 a apaaappppiiiiiccccciiiididd:dd:: :: 0 40000 5123 * AP 04started * AP 05started POST: 0x38 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 POST: 0x39 POST: 0x3a End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 POST: 0x3b fill_mem_ctrl() POST: 0x40 raminit_amdmct() raminit_amdmct begin: SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - Start. DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=c DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=10 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=10 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 1000 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDGetTCL_D: DIMMCASL 4 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 1000 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: e00000 Node: 00 base: 03 limit: 21fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:e00000 CPUMemTyping: Bottom32bIO:e00000 CPUMemTyping: Bottom40bIO:2200000 mctAutoInitMCT_D: DQSTiming_D SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. SB900 - Smbus.c - do_smbus_read_byte - Start. SB900 - Smbus.c - do_smbus_read_byte - End. TrainRcvrEn: Status 1100 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 1100 InterleaveNodes_D: ErrStatus 0 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 1100 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D All Done raminit_amdmct end: POST: 0x41 POST: 0x42 v_esp=000cbef8 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1310720 bytes), entry @ 0x200000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-4.0-2039-gd16b170 Wed Feb 8 17:50:46 CET 2012 booting... POST: 0x40 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Mainboard ASUS M5A99X-EVO Enable. dev=0x00239e2c scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=5 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled CPU: APIC: 04 enabled CPU: APIC: 05 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled POST: 0x25 PCI: Using configuration type 1 PCI: 00:00.0 [1002/5a14] ops PCI: 00:00.0 [1002/5a14] enabled Capability: type 0x08 @ 0xf0 flags: 0xa803 Capability: type 0x08 @ 0xf0 Capability: type 0x08 @ 0xc4 flags: 0x0281 PCI: pci_scan_bus for bus 00 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff PCI: pci_scan_bus upper limit too big. Using 0xff. POST: 0x24 PCI: 00:00.0 [1002/5a14] enabled PCI: 00:11.0 [1002/4393] enabled PCI: 00:12.0 [1002/4397] enabled PCI: 00:12.2 [1002/4396] enabled PCI: 00:13.0 [1002/4397] enabled PCI: 00:13.2 [1002/4396] enabled PCI: 00:14.0 [1002/4385] enabled PCI: 00:14.1 [1002/439c] enabled PCI: 00:14.2 [1002/4383] enabled PCI: 00:14.3 [1002/439d] enabled PCI: 00:14.4 [1002/4384] enabled PCI: 00:14.5 [1002/4399] enabled PCI: 00:16.0 [1002/4397] enabled PCI: 00:16.2 [1002/4396] enabled PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:14.4 PCI: pci_scan_bus for bus 01 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 do_pci_scan_bridge returns max 1 PCI: pci_scan_bus returning with max=001 POST: 0x55 PCI: pci_scan_bus returning with max=001 POST: 0x55 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done POST: 0x66 Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources APIC: 02 missing read_resources APIC: 03 missing read_resources APIC: 04 missing read_resources APIC: 05 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:14.4 read_resources bus 1 link: 0 PCI: 00:14.4 read_resources bus 1 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 PCI: 00:00.0 missing read_resources PCI: 00:02.0 missing read_resources PCI: 00:0d.0 missing read_resources PCI: 00:11.0 missing read_resources PCI: 00:12.0 missing read_resources PCI: 00:12.2 missing read_resources PCI: 00:13.0 missing read_resources PCI: 00:13.2 missing read_resources PCI: 00:14.0 missing read_resources PCI: 00:14.1 missing read_resources PCI: 00:14.2 missing read_resources PCI: 00:14.3 missing read_resources PCI: 00:14.5 missing read_resources PCI: 00:15.0 missing read_resources PCI: 00:15.1 missing read_resources PCI: 00:15.2 missing read_resources PCI: 00:15.3 missing read_resources PCI: 00:16.0 missing read_resources PCI: 00:16.2 missing read_resources PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI: 00:18.0 read_resources bus 0 link: 3 PCI: 00:18.0 read_resources bus 0 link: 3 done PCI: 00:18.0 read_resources bus 0 link: 4 PCI: 00:18.0 read_resources bus 0 link: 4 done PCI: 00:18.0 read_resources bus 0 link: 5 PCI: 00:18.0 read_resources bus 0 link: 5 done PCI: 00:18.0 read_resources bus 0 link: 6 PCI: 00:18.0 read_resources bus 0 link: 6 done PCI: 00:18.0 read_resources bus 0 link: 7 PCI: 00:18.0 read_resources bus 0 link: 7 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110a8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110a0 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 1200 index fc PCI: 00:11.0 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.3 PCI: 00:14.4 PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:02.0 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0d.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.2 PCI: 00:13.0 PCI: 00:13.2 PCI: 00:14.0 child on link 0 I2C: 00:50 I2C: 00:50 I2C: 00:51 I2C: 00:52 I2C: 00:53 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 child on link 0 PNP: 002e.0 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:14.4 PCI: 00:14.5 PCI: 00:14.6 PCI: 00:15.0 PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: 00:16.0 PCI: 00:16.2 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:11.0 20 * [0x0 - 0xf] io PCI: 00:14.1 20 * [0x10 - 0x1f] io PCI: 00:11.0 10 * [0x20 - 0x27] io PCI: 00:11.0 18 * [0x28 - 0x2f] io PCI: 00:14.1 10 * [0x30 - 0x37] io PCI: 00:14.1 18 * [0x38 - 0x3f] io PCI: 00:11.0 14 * [0x40 - 0x43] io PCI: 00:11.0 1c * [0x44 - 0x47] io PCI: 00:14.1 14 * [0x48 - 0x4b] io PCI: 00:14.1 1c * [0x4c - 0x4f] io PCI: 00:18.0 compute_resources_io: base: 50 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 10d8 * [0x0 - 0xfff] io PCI_DOMAIN: 0000 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.0 fc * [0x0 - 0xff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI: 00:14.2 10 * [0x4000000 - 0x4003fff] mem PCI: 00:12.0 10 * [0x4004000 - 0x4004fff] mem PCI: 00:13.0 10 * [0x4005000 - 0x4005fff] mem PCI: 00:14.5 10 * [0x4006000 - 0x4006fff] mem PCI: 00:16.0 10 * [0x4007000 - 0x4007fff] mem PCI: 00:11.0 24 * [0x4008000 - 0x40083ff] mem PCI: 00:12.2 10 * [0x4008400 - 0x40084ff] mem PCI: 00:13.2 10 * [0x4008500 - 0x40085ff] mem PCI: 00:16.2 10 * [0x4008600 - 0x40086ff] mem PCI: 00:18.0 compute_resources_mem: base: 4008700 size: 4100000 align: 26 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done PCI: 00:18.0 10b0 * [0x0 - 0x40fffff] mem PCI: 00:18.3 94 * [0x8000000 - 0xbffffff] mem PCI: 00:18.0 10b8 * [0xc000000 - 0xc0fffff] prefmem PCI_DOMAIN: 0000 compute_resources_mem: base: c100000 size: c100000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:11.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:12.2 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:13.2 constrain_resources: PCI: 00:14.0 constrain_resources: PCI: 00:14.1 constrain_resources: PCI: 00:14.2 constrain_resources: PCI: 00:14.3 constrain_resources: PCI: 00:14.4 constrain_resources: PCI: 00:14.5 constrain_resources: PCI: 00:16.0 constrain_resources: PCI: 00:16.2 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:0d.0 constrain_resources: PCI: 00:11.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:12.2 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:13.2 constrain_resources: PCI: 00:14.0 constrain_resources: I2C: 00:50 constrain_resources: I2C: 00:51 constrain_resources: I2C: 00:52 constrain_resources: I2C: 00:53 constrain_resources: PCI: 00:14.1 constrain_resources: PCI: 00:14.2 constrain_resources: PCI: 00:14.3 constrain_resources: PNP: 002e.2 skipping PNP: 002e.2@60 fixed resource, size=0! skipping PNP: 002e.2@70 fixed resource, size=0! constrain_resources: PNP: 002e.3 skipping PNP: 002e.3@60 fixed resource, size=0! skipping PNP: 002e.3@70 fixed resource, size=0! constrain_resources: PNP: 002e.5 skipping PNP: 002e.5@60 fixed resource, size=0! skipping PNP: 002e.5@62 fixed resource, size=0! skipping PNP: 002e.5@70 fixed resource, size=0! skipping PNP: 002e.5@72 fixed resource, size=0! constrain_resources: PNP: 002e.b skipping PNP: 002e.b@60 fixed resource, size=0! skipping PNP: 002e.b@70 fixed resource, size=0! constrain_resources: PCI: 00:14.5 constrain_resources: PCI: 00:15.0 constrain_resources: PCI: 00:15.1 constrain_resources: PCI: 00:15.2 constrain_resources: PCI: 00:15.3 constrain_resources: PCI: 00:16.0 constrain_resources: PCI: 00:16.2 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00000000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit dfffffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:0 size:1000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 10d8 * [0x0 - 0xfff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1000 size: 1000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:0 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 00:11.0 20 * [0x0 - 0xf] io Assigned: PCI: 00:14.1 20 * [0x10 - 0x1f] io Assigned: PCI: 00:11.0 10 * [0x20 - 0x27] io Assigned: PCI: 00:11.0 18 * [0x28 - 0x2f] io Assigned: PCI: 00:14.1 10 * [0x30 - 0x37] io Assigned: PCI: 00:14.1 18 * [0x38 - 0x3f] io Assigned: PCI: 00:11.0 14 * [0x40 - 0x43] io Assigned: PCI: 00:11.0 1c * [0x44 - 0x47] io Assigned: PCI: 00:14.1 14 * [0x48 - 0x4b] io Assigned: PCI: 00:14.1 1c * [0x4c - 0x4f] io PCI: 00:18.0 allocate_resources_io: next_base: 50 size: 1000 align: 12 gran: 12 done PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:18.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:18.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:c100000 align:26 gran:0 limit:dfffffff Assigned: PCI: 00:18.0 10b0 * [0xd0000000 - 0xd40fffff] mem Assigned: PCI: 00:18.3 94 * [0xd8000000 - 0xdbffffff] mem Assigned: PCI: 00:18.0 10b8 * [0xdc000000 - 0xdc0fffff] prefmem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: dc100000 size: c100000 align: 26 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:dc000000 size:100000 align:20 gran:20 limit:dfffffff Assigned: PCI: 00:00.0 fc * [0xdc000000 - 0xdc0000ff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: dc000100 size: 100000 align: 20 gran: 20 done PCI: 00:14.4 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:14.4 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:d0000000 size:4100000 align:26 gran:20 limit:dfffffff Assigned: PCI: 00:18.3 94 * [0xd0000000 - 0xd3ffffff] mem Assigned: PCI: 00:14.2 10 * [0xd4000000 - 0xd4003fff] mem Assigned: PCI: 00:12.0 10 * [0xd4004000 - 0xd4004fff] mem Assigned: PCI: 00:13.0 10 * [0xd4005000 - 0xd4005fff] mem Assigned: PCI: 00:14.5 10 * [0xd4006000 - 0xd4006fff] mem Assigned: PCI: 00:16.0 10 * [0xd4007000 - 0xd4007fff] mem Assigned: PCI: 00:11.0 24 * [0xd4008000 - 0xd40083ff] mem Assigned: PCI: 00:12.2 10 * [0xd4008400 - 0xd40084ff] mem Assigned: PCI: 00:13.2 10 * [0xd4008500 - 0xd40085ff] mem Assigned: PCI: 00:16.2 10 * [0xd4008600 - 0xd40086ff] mem PCI: 00:18.0 allocate_resources_mem: next_base: d4008700 size: 4100000 align: 26 gran: 20 done PCI: 00:14.4 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:14.4 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:18.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:18.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 split: 64K table at =cfff0000 0: mmio_basek=00340000, basek=00400000, limitk=00880000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:18.0 10d8 <- [0x0000000000 - 0x0000000fff] size 0x00001000 gran 0x0c io PCI: 00:18.0 10b8 <- [0x00dc000000 - 0x00dc0fffff] size 0x00100000 gran 0x14 prefmem PCI: 00:18.0 10b0 <- [0x00d0000000 - 0x00d40fffff] size 0x04100000 gran 0x14 mem PCI: 00:18.0 110d0 <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c io PCI: 00:18.0 110a8 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 prefmem PCI: 00:18.0 110a0 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:00.0 fc <- [0x00dc000000 - 0x00dc0000ff] size 0x00000100 gran 0x08 prefmem PCI: 00:11.0 10 <- [0x0000000020 - 0x0000000027] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000000040 - 0x0000000043] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000000028 - 0x000000002f] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000000044 - 0x0000000047] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000000000 - 0x000000000f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00d4008000 - 0x00d40083ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00d4004000 - 0x00d4004fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00d4008400 - 0x00d40084ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00d4005000 - 0x00d4005fff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00d4008500 - 0x00d40085ff] size 0x00000100 gran 0x08 mem PCI: 00:14.1 10 <- [0x0000000030 - 0x0000000037] size 0x00000008 gran 0x03 io PCI: 00:14.1 14 <- [0x0000000048 - 0x000000004b] size 0x00000004 gran 0x02 io PCI: 00:14.1 18 <- [0x0000000038 - 0x000000003f] size 0x00000008 gran 0x03 io PCI: 00:14.1 1c <- [0x000000004c - 0x000000004f] size 0x00000004 gran 0x02 io PCI: 00:14.1 20 <- [0x0000000010 - 0x000000001f] size 0x00000010 gran 0x04 io PCI: 00:14.2 10 <- [0x00d4000000 - 0x00d4003fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:14.4 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:14.4 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:14.5 10 <- [0x00d4006000 - 0x00d4006fff] size 0x00001000 gran 0x0c mem PCI: 00:16.0 10 <- [0x00d4007000 - 0x00d4007fff] size 0x00001000 gran 0x0c mem PCI: 00:16.2 10 <- [0x00d4008600 - 0x00d40086ff] size 0x00000100 gran 0x08 mem PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 1000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base d0000000 size c100000 align 26 gran 0 limit dfffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size cff40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base 100000000 size 120000000 align 0 gran 0 limit 0 flags e0004200 index 30 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 1000 align 12 gran 12 limit ffff flags 60080100 index 10d8 PCI: 00:18.0 resource base dc000000 size 100000 align 20 gran 20 limit dfffffff flags 60081200 index 10b8 PCI: 00:18.0 resource base d0000000 size 4100000 align 26 gran 20 limit dfffffff flags 60080200 index 10b0 PCI: 00:18.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080100 index 110d0 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081200 index 110a8 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080200 index 110a0 PCI: 00:00.0 PCI: 00:00.0 resource base dc000000 size 100 align 8 gran 8 limit dfffffff flags 60001200 index fc PCI: 00:11.0 PCI: 00:11.0 resource base 20 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:11.0 resource base 40 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:11.0 resource base 28 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:11.0 resource base 44 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:11.0 resource base d4008000 size 400 align 10 gran 10 limit dfffffff flags 60000200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base d4004000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base d4008400 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base d4005000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base d4008500 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.1 resource base 30 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:14.1 resource base 48 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:14.1 resource base 38 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:14.1 resource base 4c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:14.1 resource base 10 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base d4000000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 10 PCI: 00:14.3 PCI: 00:14.4 PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base d4006000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base d4007000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base d4008600 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base d0000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 PCI: 00:18.4 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:02.0 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0d.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.2 PCI: 00:13.0 PCI: 00:13.2 PCI: 00:14.0 child on link 0 I2C: 00:50 I2C: 00:50 I2C: 00:51 I2C: 00:52 I2C: 00:53 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 child on link 0 PNP: 002e.0 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 PNP: 002e.7 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.7 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.b resource base 5 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:14.4 PCI: 00:14.5 PCI: 00:14.6 PCI: 00:15.0 PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: 00:16.0 PCI: 00:16.2 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base d8000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 PCI: 00:18.4 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/843e PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/843e PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1043/843e PCI: 00:18.4 cmd <- 00 PCI: 00:00.0 cmd <- 02 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 cmd <- 02 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 cmd <- 02 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 cmd <- 0f PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 cmd <- 02 PCI: 00:16.0 cmd <- 02 PCI: 00:16.2 cmd <- 02 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00006000, offset=0x00200000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 00 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #0 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 1. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #1 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 01 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x01 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #1 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 2. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #2 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 02 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x02 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #2 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 3. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #3 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 03 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x03 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #3 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 4. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #4 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 04 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x04 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #4 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 5. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #5 Waiting for 1 CPUS to stop CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 05 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 3328MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3584MB, range: 512MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x05 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #5 initialized All AP CPUs stopped SB900 - Early.c - sb_After_Pci_Init - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_After_Pci_Init - End. SB900 - Early.c - sb_Mid_Post_Init - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_Mid_Post_Init - End. PCI: 00:18.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init PCI: 00:00.0 init IOAPIC: Initializing IOAPIC at 0xdc000000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x01 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC not responding. PCI: 00:11.0 init PCI: 00:12.0 init PCI: 00:12.2 init PCI: 00:13.0 init PCI: 00:13.2 init PCI: 00:14.0 init PCI: 00:14.1 init PCI: 00:14.2 init PCI: 00:14.3 init PCI: 00:14.5 init PCI: 00:16.0 init PCI: 00:16.2 init PCI: 00:18.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 APIC: 01: enabled 1 APIC: 02: enabled 1 APIC: 03: enabled 1 APIC: 04: enabled 1 APIC: 05: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 POST: 0x89 Initializing CBMEM area to 0xcfff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to cfff0200...ok High Tables Base is cfff0000. POST: 0x9a SB900 - Early.c - sb_Late_Post - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_Late_Post - End. Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done. Adding CBMEM entry as no. 2 Writing IRQ routing tables to 0xcfff0400...write_pirq_routing_table done. PIRQ table: 48 bytes. POST: 0x9b Wrote the mp table end at: 000f0410 - 000f055c Adding CBMEM entry as no. 3 Wrote the mp table end at: cfff1410 - cfff155c MP table: 348 bytes. POST: 0x9c Adding CBMEM entry as no. 4 ACPI: Writing ACPI tables at cfff2400... ACPI: * HPET at cfff24c8 ACPI: added table 1/32, length now 40 ACPI: * MADT at cfff2500 ACPI: added table 2/32, length now 44 ACPI: * SRAT at cfff2580 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=0033fd00 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00480000 ACPI: added table 3/32, length now 48 ACPI: * SLIT at cfff2688 ACPI: added table 4/32, length now 52 ACPI: * SSDT at cfff26c0 ACPI: added table 5/32, length now 56 ACPI: * SSDT for PState at cfff2cf5 ACPI: * DSDT at cfff2cf8 ACPI: * DSDT @ cfff2cf8 Length 288b ACPI: * FACS at cfff5588 ACPI: * FADT at cfff55c8 ACPI_BLK_BASE: 0x0800 ACPI: added table 6/32, length now 60 ACPI: done. ACPI tables: 12988 bytes. Adding CBMEM entry as no. 5 smbios_write_tables: cfffd800 Root Device (ASUS M5A99X-EVO Mainboard) APIC_CLUSTER: 0 (AMD FAM10 Root Complex) APIC: 00 (socket AM3) PCI_DOMAIN: 0000 (AMD FAM10 Root Complex) PCI: 00:18.0 (AMD FAM10 Northbridge) PCI: 00:00.0 (ATI rd890) PCI: 00:00.1 (ATI rd890) PCI: 00:02.0 (ATI rd890) PCI: 00:03.0 (ATI rd890) PCI: 00:04.0 (ATI rd890) PCI: 00:05.0 (ATI rd890) PCI: 00:06.0 (ATI rd890) PCI: 00:07.0 (ATI rd890) PCI: 00:08.0 (ATI rd890) PCI: 00:09.0 (ATI rd890) PCI: 00:0a.0 (ATI rd890) PCI: 00:0b.0 (ATI rd890) PCI: 00:0c.0 (ATI rd890) PCI: 00:0d.0 (ATI rd890) PCI: 00:11.0 (ATI SB900) PCI: 00:12.0 (ATI SB900) PCI: 00:12.2 (ATI SB900) PCI: 00:13.0 (ATI SB900) PCI: 00:13.2 (ATI SB900) PCI: 00:14.0 (ATI SB900) I2C: 00:50 () I2C: 00:51 () I2C: 00:52 () I2C: 00:53 () PCI: 00:14.1 (ATI SB900) PCI: 00:14.2 (ATI SB900) PCI: 00:14.3 (ATI SB900) PNP: 002e.0 (ITE IT8721F Super I/O) PNP: 002e.1 (ITE IT8721F Super I/O) PNP: 002e.2 (ITE IT8721F Super I/O) PNP: 002e.3 (ITE IT8721F Super I/O) PNP: 002e.5 (ITE IT8721F Super I/O) PNP: 002e.6 (ITE IT8721F Super I/O) PNP: 002e.7 (ITE IT8721F Super I/O) PNP: 002e.8 (ITE IT8721F Super I/O) PNP: 002e.9 (ITE IT8721F Super I/O) PNP: 002e.a (ITE IT8721F Super I/O) PNP: 002e.b (ITE IT8721F Super I/O) PCI: 00:14.4 (ATI SB900) PCI: 00:14.5 (ATI SB900) PCI: 00:14.6 (ATI SB900) PCI: 00:15.0 (ATI SB900) PCI: 00:15.1 (ATI SB900) PCI: 00:15.2 (ATI SB900) PCI: 00:15.3 (ATI SB900) PCI: 00:16.0 (ATI SB900) PCI: 00:16.2 (ATI SB900) PCI: 00:18.1 (AMD FAM10 Northbridge) PCI: 00:18.2 (AMD FAM10 Northbridge) PCI: 00:18.3 (AMD FAM10 Northbridge) PCI: 00:18.4 (AMD FAM10 Northbridge) APIC: 01 () APIC: 02 () APIC: 03 () APIC: 04 () APIC: 05 () PCI: 00:00.0 () PCI: 00:11.0 () PCI: 00:12.0 () PCI: 00:12.2 () PCI: 00:13.0 () PCI: 00:13.2 () PCI: 00:14.0 () PCI: 00:14.1 () PCI: 00:14.2 () PCI: 00:14.3 () PCI: 00:14.4 () PCI: 00:14.5 () PCI: 00:16.0 () PCI: 00:16.2 () PCI: 00:18.0 () PCI: 00:18.1 () PCI: 00:18.2 () PCI: 00:18.3 () PCI: 00:18.4 () SMBIOS tables: 269 bytes. POST: 0x9d Adding CBMEM entry as no. 6 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 4fde New low_table_end: 0x00000518 Now going to write high coreboot table at 0xcfffe000 rom_table_end = 0xcfffe000 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0xcfffe000 to 0xd0000000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-00000000cffeffff: RAM 3. 00000000cfff0000-00000000cfffffff: CONFIGURATION TABLES 4. 00000000e0000000-00000000efffffff: RESERVED 5. 0000000100000000-000000021fffffff: RAM Wrote coreboot table at: cfffe000 - cfffe1e0 checksum 729e coreboot table: 480 bytes. POST: 0x9e POST: 0x9d Multiboot Information structure has been written. 0. FREE SPACE d0000000 00000000 1. GDT cfff0200 00000200 2. IRQ TABLE cfff0400 00001000 3. SMP TABLE cfff1400 00001000 4. ACPI cfff2400 0000b400 5. SMBIOS cfffd800 00000800 6. COREBOOT cfffe000 00002000 Searching for fallback/payload Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Got a payload Loading segment from rom address 0xffc43f38 data (compression=1) New segment dstaddr 0xed150 memsize 0x12eb0 srcaddr 0xffc43f70 filesize 0x9759 (cleaned up) New segment addr 0xed150 size 0x12eb0 offset 0xffc43f70 filesize 0x9759 Loading segment from rom address 0xffc43f54 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000ed150 memsz: 0x0000000000012eb0 filesz: 0x0000000000009759 lb: [0x0000000000200000, 0x0000000000340000) Post relocation: addr: 0x00000000000ed150 memsz: 0x0000000000012eb0 filesz: 0x0000000000009759 using LZMA [ 0x000ed150, 00100000, 0x00100000) <- ffc43f70 dest 000ed150, end 00100000, bouncebuffer cfd70000 Loaded segments Jumping to boot code at fc63c POST: 0xf8 entry = 0x000fc63c lb_start = 0x00200000 lb_size = 0x00140000 adjust = 0xcfcb0000 buffer = 0xcfd70000 elf_boot_notes = 0x0023b1c4 adjusted_boot_notes = 0xcfeeb1c4 Start bios (version 1.6.3-20120208_175037-oldx86) Find memory size Attempting to find coreboot table Found coreboot table forwarder. Now attempting to find coreboot memory map Add to e820 map: 00000000 00001000 2 Add to e820 map: 00001000 0009f000 1 Add to e820 map: 000c0000 cff30000 1 Add to e820 map: cfff0000 00010000 2 Add to e820 map: e0000000 10000000 2 Add to e820 map: 00000000 20000000 1 Add to e820 map: 00000000 00004000 1 Found mainboard ASUS M5A99X-EVO Found CBFS header at 0xfffffca0 Add to e820 map: 000a0000 00050000 -1 Add to e820 map: 000f0000 00010000 2 Ram Size=0xcfff0000 (0x0000000120000000 high) malloc setup Add to e820 map: cffe0000 00010000 2 init ivt init bda Add to e820 map: 0009fc00 00000400 2 init pic init timer init timer: 01 init timer: 02 init timer: 03 init timer: 04 init timer: 05 init timer: 06 init timer: 07 init timer: 08 init timer: 09 init timer: 10 init timer: 11 init timer: 12 math cp init PCI probe Searching CBFS for prefix etc/extra-pci-roots Found CBFS file cmos_layout.bin Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file config Found CBFS file pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfe70 (detail=0xcffdfee0) PCI device 00:00.0 (vd=1002:5a14 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfdd0 (detail=0xcffdfe40) PCI device 00:11.0 (vd=1002:4393 c=0101) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfd30 (detail=0xcffdfda0) PCI device 00:12.0 (vd=1002:4397 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfc90 (detail=0xcffdfd00) PCI device 00:12.2 (vd=1002:4396 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfbf0 (detail=0xcffdfc60) PCI device 00:13.0 (vd=1002:4397 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfb50 (detail=0xcffdfbc0) PCI device 00:13.2 (vd=1002:4396 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfab0 (detail=0xcffdfb20) PCI device 00:14.0 (vd=1002:4385 c=0c05) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdfa10 (detail=0xcffdfa80) PCI device 00:14.1 (vd=1002:439c c=0101) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf970 (detail=0xcffdf9e0) PCI device 00:14.2 (vd=1002:4383 c=0403) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf8d0 (detail=0xcffdf940) PCI device 00:14.3 (vd=1002:439d c=0601) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf830 (detail=0xcffdf8a0) PCI device 00:14.4 (vd=1002:4384 c=0604) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf790 (detail=0xcffdf800) PCI device 00:14.5 (vd=1002:4399 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf6f0 (detail=0xcffdf760) PCI device 00:16.0 (vd=1002:4397 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf650 (detail=0xcffdf6c0) PCI device 00:16.2 (vd=1002:4396 c=0c03) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf5b0 (detail=0xcffdf620) PCI device 00:18.0 (vd=1022:1200 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf510 (detail=0xcffdf580) PCI device 00:18.1 (vd=1022:1201 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf470 (detail=0xcffdf4e0) PCI device 00:18.2 (vd=1022:1202 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf3d0 (detail=0xcffdf440) PCI device 00:18.3 (vd=1022:1203 c=0600) pmm_malloc zone=0x000f6758 handle=ffffffff size=112 align=10 ret=0xcffdf330 (detail=0xcffdf3a0) PCI device 00:18.4 (vd=1022:1204 c=0600) Found 19 PCI devices (max PCI bus is 01) Searching CBFS for prefix bootorder Found CBFS file cmos_layout.bin Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file config Found CBFS file Found 1 cpu(s) max supported 1 cpu(s) init bios32 hhadnhhe_hlwc1 piq=0irf00q=fee0fhrqh=h‰hha‰ndla_hw‰eic‰1prq i‰hi=0 hhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰ndlahw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ =0hqhhhha‰ndl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰ndlahw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ h=0qh‰hhahndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰a‰we_hpic1‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰rq‰ i=0hhha‰nhhdla‰n_h‰ew‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1prq i‰hi=0 hhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ h=0qh‰hhahndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰we‰c1piirq‰ h=0hqh‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch8hh‰nhahand‰lh‰we_ic1p‰irq‰ h=0qh‰hhahndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰we‰c1piirq‰ h=0hqh‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch7hh‰nhahand‰lh‰we_ic1p‰irq‰ h=0qhh‰hhadla‰n_h‰ew‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰ec‰1piirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰ndlahw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ =0hqhhhha‰ndl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰ndlahw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ =0hqhhhha‰ndl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰ndlahw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ =0hqhhhha‰ndl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰ndlahw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ h=0qhh‰hhadla‰n_h‰ew‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰ec‰1piirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ h=0qhh‰hhadla‰n_h‰ew‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1prq i‰hi=0 hhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ h=0qh‰hhahndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰a‰we_hpic1‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰rq‰ i=0hhha‰nhhdla‰n_h‰ew‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1prq i‰hi=0 hhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰ndlahw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_i‰c1prq ‰ih=0h h‰hha‰ndla_hw‰eic‰1p‰rq i=0 i‰0rq=hahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰rq‰ i=0hhh‰nhhandl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰we‰c1piirq‰ h=0hqh‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0ch7hh‰nhahand‰lh‰we_ic1p‰irq‰ =0qhha‰hhhndla‰hw‰e_i‰c1prq ‰ih=0h h‰hha‰ndla_hw‰eic‰1p‰rq i=0 i‰0rq=hahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰==0qhhhhhadl‰an‰hwe_pic1‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰rq‰ i=0hhh‰nhhandl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰wec1pi‰irq‰ h=0qhh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰a‰we_hpic1‰rq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰rq‰ i=0hhha‰nhhdla‰n_h‰ew‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰eic‰1prq i‰hi=0 hhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰ndlahw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ =0hqhhhha‰ndl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰ndlahw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ =0hqhhhha‰ndl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰ndlahw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ =0hqhhhha‰ndl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰ndla_hw‰ec‰1piirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ h=0qh‰hhahndl‰a_h‰we‰c1pi irq‰hq=0rahhhhndl‰a_h‰we‰c1piirq‰ h=0hqh‰hhandla‰_hw‰ec‰1pi‰irq q=‰=0chdhh‰nhahand‰lh‰we_ic1p‰irq‰ h=0qhh‰hhadla‰n_h‰ew‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰ec‰1piirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ h=0qhh‰hhadla‰n_h‰ew‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰ec‰1piirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1prq‰ i=h0hh‰nhahand‰lh‰we_ic1p‰irq‰ h=0qhh‰hhadla‰n_h‰ew‰c1piirq‰ h=0hqh‰hha‰ndla_hw‰ec‰1piirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ h=0hqh‰hhandla‰hw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ =0hqhhhha‰ndl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰ndlahw‰e_i‰c1pirq ‰h==0qhhhhandl‰ah‰we_‰ic1pirq‰ =0hqhhhha‰ndl‰ah‰we_‰ic1pirq‰ h=0hqh‰hha‰nd