coreboot-4.0-2002-gee77cf1-dirty Fri Feb 3 03:53:31 CET 2012 starting... BSP Family_Model: 00100fa0 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000 microcode: patch id to apply = 0x010000bf microcode: updated to patch id = 0x010000bf success POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 SB900 - Early.c - get_sbdn - Start. SB900 - Early.c - get_sbdn - End. cpuSetAMDPCI 00 done Prep FID/VID Node:00 P-state info in MSRC001_0064 is invalid !!! P-state info in MSRc0010064 is invalid !!! F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001016 F3xDC: 0000611a POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 POST: 0x37 started ap apicid: PPPPPOOOOOSSSSSTTTTT::::: 00000xxxxx3333300000 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000043152 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000051324}}}}} --------------- * AmmmmmiPiiiiccc ccrrrrr0o1oooocccccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000 startemmmmmdiiiiicc cccrrrr rooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff mmmm*miiiii ccAcccrrrrPr ooooocc0cccoooo2odddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss sccccpctpppuuuupaurSSSSeeSteetttteetdAAAAMMA MMDDDDM DMMMMSSMSSRRRRS R * AP 0 3dddddooooonnnnneeeee stiiiiiannnniinriittttitte____ff_dffiiiif di dddvvvdviiiivdiddd___d__aaaappapp(((p((ssssttsttaaaataggggeegee1111e)1))) ) aaaa papppiiipiicccciciiidddidd:::: : 0000 05324 1 FFF*FFIIII IDADDDDVVVPVVIIIII D0DDDD 4 ooooonnnnn AAAAAPPPPP::::: 0000024153 started * AP 05started POST: 0x38 rs780_early_setup() fam10_optimization() rs780_por_init Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 POST: 0x39 FIDVID on BSP, APIC_id: 00 BSP fid = 0 Wait for AP stage 1: ap_apicid = 1 readback = 1000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2 readback = 2000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 3 readback = 3000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 4 readback = 4000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 5 readback = 5000001 common_fid(packed) = 0 common_fid = 0 POST: 0x3a End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 rs780_htinit cpu_ht_freq=b. rs780_htinit: HT3 mode ...WARM RESET... coreboot-4.0-2002-gee77cf1-dirty Fri Feb 3 03:53:31 CET 2012 starting... BSP Family_Model: 00100fa0 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000 microcode: patch id to apply = 0x010000bf microcode: updated to patch id = 0x010000bf success POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 SB900 - Early.c - get_sbdn - Start. SB900 - Early.c - get_sbdn - End. cpuSetAMDPCI 00 done Prep FID/VID Node:00 P-state info in MSRC001_0064 is invalid !!! P-state info in MSRc0010064 is invalid !!! F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001016 F3xDC: 0000611a POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 POST: 0x37 started ap apicid: PPPPPOOOOOSSSSSTTTTT::::: 00000xxxxx3333300000 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000054132 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000012435}}}}} --------------- * AmmmmmPiiiiiccccc rrrrr0oooo1occcccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000 startmmemmmiiidiiccc ccrr rrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff mm*mmm iiiiicccccArrrrrPoooo occc0ccoo2ooodddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss sccppccctuupppaSuuurSSSSteeeeettettdAAtA MMAA DDMMMMMDDDMSSMMSSRRS RRR * AP 0 ddddd3ooooonnnnneeeee stiiiiinnannniiriiitttttte_____fffffdiiiii dddd dvvvvviiiiiddddd_____ssssstttttaaaaagggggeeeee22222 aaaaapppppiiiiiccccciiiiiddddd::::: 0000032415 * AP 04started * AP 05started POST: 0x38 rs780_early_setup() fam10_optimization() rs780_por_init Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 POST: 0x39 POST: 0x3a End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 rs780_htinit cpu_ht_freq=b. rs780_htinit: HT3 mode POST: 0x3b fill_mem_ctrl() POST: 0x40 raminit_amdmct() raminit_amdmct begin: DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=c DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=10 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=10 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 1000 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 4 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 1000 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: c00000 Node: 00 base: 03 limit: 23fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:c00000 CPUMemTyping: Bottom32bIO:c00000 CPUMemTyping: Bottom40bIO:2400000 mctAutoInitMCT_D: DQSTiming_D TrainRcvrEn: Status 1100 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 1100 InterleaveNodes_D: ErrStatus 0 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 1100 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D All Done raminit_amdmct end: POST: 0x41 POST: 0x42 v_esp=000cbef8 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1277952 bytes), entry @ 0x200000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-4.0-2002-gee77cf1-dirty Fri Feb 3 03:53:31 CET 2012 booting... POST: 0x40 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Mainboard ASUS M5A99X-EVO Enable. dev=0x00233e40 m5a99x_evo_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000 m5a99x_evo_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000002 m5a99x_evo_enable: uma size 0x10000000, memory start 0xb0000000 m5a99x_evo_enable, w00t?! m5a99x_evo_enable, cya enable?! Enumerating buses... starting with root now scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... cpu_bus_scan: starting... PCI: 00:18.3 siblings=5 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled CPU: APIC: 04 enabled CPU: APIC: 05 enabled cpu_bus_scan: done. PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 pci_scan_bus: before pci_scan_get_dev! devfn: 192 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 193 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! PCI: 00:18.1 [1022/1201] enabled pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 194 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! PCI: 00:18.2 [1022/1202] enabled pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 195 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 196 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! PCI: 00:18.4 [1022/1204] enabled pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 197 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 198 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 199 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 200 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 208 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 216 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 224 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 232 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 240 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 248 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! POST: 0x25 amdfam10_scan_chains: starting... amdfam10_scan_chains: link: 002341b4 amdfam10_scan_chain: starting... amdfam10_scan_chain: link_type: 0x00000007 amdfam10_scan_chain: link_type: 0x00000007 amdfam10_scan_chain: before get_ht_c_index amdfam10_scan_chain: after get_ht_c_index amdfam10_scan_chain: before set_config_map_reg amdfam10_scan_chain: after set_config_map_reg amdfam10_scan_chain: before hypertransport_scan_chain hypertransport_scan_chain: before ht_collapse_early_enumeration hypertransport_scan_chain: after ht_collapse_early_enumeration hypertransport_scan_chain: before ht_scan_get_devs hypertransport_scan_chain: after ht_scan_get_devs hypertransport_scan_chain: before pci_probe_dev PCI: Using configuration type 1 rs780_enable: dev=0023440c, VID_DID=0x5a141002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() addr=e0000000,bus=0,devfn=40 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8 NB_PCI_REG04 = 2. NB_PCI_REG84 = 3000095. NB_PCI_REG4C = 52042. rs780_enable: done PCI: 00:00.0 [1002/5a14] enabled hypertransport_scan_chain: after pci_probe_dev hypertransport_scan_chain: before ht_lookup_slave_capability Capability: type 0x08 @ 0xf0 flags: 0xa803 Capability: type 0x08 @ 0xf0 Capability: type 0x08 @ 0xc4 flags: 0x0281 hypertransport_scan_chain: after ht_lookup_slave_capability hypertransport_scan_chain: end_of_chain. w00t! hypertransport_scan_chain: before pci_scan_bus! PCI: pci_scan_bus for bus 00 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff PCI: pci_scan_bus upper limit too big. Using 0xff. POST: 0x24 pci_scan_bus: before pci_scan_get_dev! devfn: 0 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! rs780_enable: dev=0023440c, VID_DID=0x5a141002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8 NB_PCI_REG04 = 2. NB_PCI_REG84 = 3000095. NB_PCI_REG4C = 52042. rs780_enable: done PCI: 00:00.0 [1002/5a14] enabled pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 1 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 2 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 3 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 4 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 5 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 6 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 7 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! pci_scan_bus: before pci_scan_get_dev! devfn: 8 pci_scan_bus: after pci_scan_get_dev! pci_scan_bus: before pci_probe_dev! pci_scan_bus: after pci_probe_dev! POST: 0x25 PCI: Left over static devices: PCI: 00:02.0 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.2 PCI: 00:13.0 PCI: 00:13.2 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 PCI: 00:14.4 PCI: 00:14.5 PCI: 00:14.6 PCI: 00:15.0 PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: 00:16.0 PCI: 00:16.2 PCI: Check your devicetree.cb. PCI: pci_scan_bus returning with max=000 POST: 0x55 hypertransport_scan_chain: after pci_scan_bus! amdfam10_scan_chain: after hypertransport_scan_chain amdfam10_scan_chain: before set_config_map_reg amdfam10_scan_chain: after set_config_map_reg amdfam10_scan_chain: before store_ht_c_conf_bus amdfam10_scan_chain: after store_ht_c_conf_bus amdfam10_scan_chain: done. amdfam10_scan_chains: link: 00278000 amdfam10_scan_chains: link: 00278018 amdfam10_scan_chains: link: 00278030 amdfam10_scan_chains: link: 00278048 amdfam10_scan_chains: link: 00278060 amdfam10_scan_chains: link: 00278078 amdfam10_scan_chains: link: 00278090 amdfam10_scan_chains: link2: 002341b4 amdfam10_scan_chains: link2: 00278000 amdfam10_scan_chain: starting... amdfam10_scan_chain: link_type: 0x00000000 amdfam10_scan_chains: link2: 00278018 amdfam10_scan_chain: starting... amdfam10_scan_chain: link_type: 0x00000000 amdfam10_scan_chains: link2: 00278030 amdfam10_scan_chain: starting... amdfam10_scan_chain: link_type: 0x00000000 amdfam10_scan_chains: link2: 00278048 amdfam10_scan_chain: starting... amdfam10_scan_chains: link2: 00278060 amdfam10_scan_chain: starting... amdfam10_scan_chain: link_type: 0x00000000 amdfam10_scan_chains: link2: 00278078 amdfam10_scan_chain: starting... amdfam10_scan_chain: link_type: 0x00000000 amdfam10_scan_chains: link2: 00278090 amdfam10_scan_chain: starting... amdfam10_scan_chain: link_type: 0x00000000 amdfam10_scan_chains: done. PCI: pci_scan_bus returning with max=000 POST: 0x55 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done POST: 0x66 ===============Enumeration done!======== Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources APIC: 02 missing read_resources APIC: 03 missing read_resources APIC: 04 missing read_resources APIC: 05 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI: 00:18.0 read_resources bus 0 link: 3 PCI: 00:18.0 read_resources bus 0 link: 3 done PCI: 00:18.0 read_resources bus 0 link: 4 PCI: 00:18.0 read_resources bus 0 link: 4 done PCI: 00:18.0 read_resources bus 0 link: 5 PCI: 00:18.0 read_resources bus 0 link: 5 done PCI: 00:18.0 read_resources bus 0 link: 6 PCI: 00:18.0 read_resources bus 0 link: 6 done PCI: 00:18.0 read_resources bus 0 link: 7 PCI: 00:18.0 read_resources bus 0 link: 7 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b8 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 201 index 1c PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:00.0 1c * [0x0 - 0xfffffff] mem PCI: 00:18.0 compute_resources_mem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffffff done PCI: 00:18.0 10b8 * [0x0 - 0xfffffff] mem PCI: 00:18.3 94 * [0x10000000 - 0x13ffffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 14000000 size: 14000000 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00000000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit dfffffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:0 size:0 align:0 gran:0 limit:ffff PCI_DOMAIN: 0000 allocate_resources_io: next_base: 0 size: 0 align: 0 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:18.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:14000000 align:28 gran:0 limit:dfffffff Assigned: PCI: 00:18.0 10b8 * [0xc0000000 - 0xcfffffff] mem Assigned: PCI: 00:18.3 94 * [0xd0000000 - 0xd3ffffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: d4000000 size: 14000000 align: 28 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:18.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:c0000000 size:10000000 align:28 gran:20 limit:dfffffff Assigned: PCI: 00:00.0 1c * [0xc0000000 - 0xcfffffff] mem PCI: 00:18.0 allocate_resources_mem: next_base: d0000000 size: 10000000 align: 28 gran: 20 done Root Device assign_resources, bus 0 link: 0 split: 64K table at =afff0000 0: mmio_basek=00300000, basek=00400000, limitk=00900000 Adding UMA memory area PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:18.0 10b0 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 prefmem PCI: 00:18.0 10b8 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x14 mem PCI: 00:18.0 10d8 <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c io PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:00.0 1c <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c mem64 PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base c0000000 size 14000000 align 28 gran 0 limit dfffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base 100000000 size 130000000 align 0 gran 0 limit 0 flags e0004200 index 30 PCI_DOMAIN: 0000 resource base b0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081200 index 10b0 PCI: 00:18.0 resource base c0000000 size 10000000 align 28 gran 20 limit dfffffff flags 60080200 index 10b8 PCI: 00:18.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080100 index 10d8 PCI: 00:00.0 PCI: 00:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60000201 index 1c PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base d0000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 PCI: 00:18.4 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/843e PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/843e PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1043/843e PCI: 00:18.4 cmd <- 00 PCI: 00:00.0 subsystem <- 1043/843e PCI: 00:00.0 cmd <- 02 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x0000a000, offset=0x00200000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 00 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole. Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 8704MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #0 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 1. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #1 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 01 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole. Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 8704MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x01 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #1 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 2. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #2 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 02 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole. Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 8704MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x02 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #2 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 3. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #3 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 03 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole. Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 8704MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x03 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #3 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 4. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #4 CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 04 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole. Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 8704MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x04 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #4 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 5. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #5 Waiting for 1 CPUS to stop CPU: vendor AMD device 100fa0 CPU: family 10, model 0a, stepping 00 nodeid = 00, coreid = 05 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole. Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 8704MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 3, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x05 done. POST: 0x9b CPU model: AMD Processor model unknown siblings = 05, CPU #5 initialized All AP CPUs stopped SB900 - Early.c - sb_After_Pci_Init - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_After_Pci_Init - End. SB900 - Early.c - sb_Mid_Post_Init - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_Mid_Post_Init - End. PCI: 00:18.0 init PCI: 00:18.1 init Searching for pci1022,1201.rom Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check Could not find file 'pci1022,1201.rom'. PCI: 00:18.2 init Searching for pci1022,1202.rom Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check Could not find file 'pci1022,1202.rom'. PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init Searching for pci1022,1204.rom Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check Could not find file 'pci1022,1204.rom'. PCI: 00:00.0 init Searching for pci1002,5a14.rom Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check Could not find file 'pci1002,5a14.rom'. Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 APIC: 01: enabled 1 APIC: 02: enabled 1 APIC: 03: enabled 1 APIC: 04: enabled 1 APIC: 05: enabled 1 POST: 0x89 Initializing CBMEM area to 0xafff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to afff0200...ok High Tables Base is afff0000. POST: 0x9a SB900 - Early.c - sb_Late_Post - Start. SB900 - Cfg.c - sb900_cimx_config - Start. SB900 - Cfg.c - sb900_cimx_config - End. SB900 - Early.c - sb_Late_Post - End. Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done. Adding CBMEM entry as no. 2 Writing IRQ routing tables to 0xafff0400...write_pirq_routing_table done. PIRQ table: 48 bytes. POST: 0x9b Wrote the mp table end at: 000f0410 - 000f0554 Adding CBMEM entry as no. 3 Wrote the mp table end at: afff1410 - afff1554 MP table: 340 bytes. POST: 0x9c Adding CBMEM entry as no. 4 ACPI: Writing ACPI tables at afff2400... ACPI: * HPET at afff24c8 ACPI: added table 1/32, length now 40 ACPI: * MADT at afff2500 ACPI: added table 2/32, length now 44 ACPI: * SRAT at afff2580 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00400000, sizek=004c0000 ACPI: added table 3/32, length now 48 ACPI: * SLIT at afff2688 ACPI: added table 4/32, length now 52 ACPI: * SSDT at afff26c0 ACPI: added table 5/32, length now 56 ACPI: * SSDT for PState at afff2cf5 ACPI: * DSDT at afff2cf8 ACPI: * DSDT @ afff2cf8 Length 288b ACPI: * FACS at afff5588 ACPI: * FADT at afff55c8 ACPI_BLK_BASE: 0x0800 ACPI: added table 6/32, length now 60 ACPI: done. ACPI tables: 12988 bytes. Adding CBMEM entry as no. 5 smbios_write_tables: afffd800 Root Device (ASUS M5A99X-EVO Mainboard) APIC_CLUSTER: 0 (AMD FAM10 Root Complex) APIC: 00 (socket AM3) PCI_DOMAIN: 0000 (AMD FAM10 Root Complex) PCI: 00:18.0 (AMD FAM10 Northbridge) PCI: 00:00.0 (ATI RS780) PCI: 00:02.0 (ATI RS780) PCI: 00:03.0 (ATI RS780) PCI: 00:04.0 (ATI RS780) PCI: 00:05.0 (ATI RS780) PCI: 00:06.0 (ATI RS780) PCI: 00:07.0 (ATI RS780) PCI: 00:08.0 (ATI RS780) PCI: 00:09.0 (ATI RS780) PCI: 00:0a.0 (ATI RS780) PCI: 00:11.0 (ATI SB900) PCI: 00:12.0 (ATI SB900) PCI: 00:12.2 (ATI SB900) PCI: 00:13.0 (ATI SB900) PCI: 00:13.2 (ATI SB900) PCI: 00:14.0 (ATI SB900) I2C: 00:50 () I2C: 00:51 () I2C: 00:52 () I2C: 00:53 () PCI: 00:14.1 (ATI SB900) PCI: 00:14.2 (ATI SB900) PCI: 00:14.3 (ATI SB900) PNP: 002e.0 (ITE IT8721F Super I/O) PNP: 002e.1 (ITE IT8721F Super I/O) PNP: 002e.2 (ITE IT8721F Super I/O) PNP: 002e.3 (ITE IT8721F Super I/O) PNP: 002e.5 (ITE IT8721F Super I/O) PNP: 002e.6 (ITE IT8721F Super I/O) PNP: 002e.7 (ITE IT8721F Super I/O) PNP: 002e.8 (ITE IT8721F Super I/O) PNP: 002e.9 (ITE IT8721F Super I/O) PNP: 002e.a (ITE IT8721F Super I/O) PNP: 002e.b (ITE IT8721F Super I/O) PCI: 00:14.4 (ATI SB900) PCI: 00:14.5 (ATI SB900) PCI: 00:14.6 (ATI SB900) PCI: 00:15.0 (ATI SB900) PCI: 00:15.1 (ATI SB900) PCI: 00:15.2 (ATI SB900) PCI: 00:15.3 (ATI SB900) PCI: 00:16.0 (ATI SB900) PCI: 00:16.2 (ATI SB900) PCI: 00:18.1 (AMD FAM10 Northbridge) PCI: 00:18.2 (AMD FAM10 Northbridge) PCI: 00:18.3 (AMD FAM10 Northbridge) PCI: 00:18.4 (AMD FAM10 Northbridge) APIC: 01 () APIC: 02 () APIC: 03 () APIC: 04 () APIC: 05 () SMBIOS tables: 275 bytes. POST: 0x9d Adding CBMEM entry as no. 6 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 6fde New low_table_end: 0x00000518 Now going to write high coreboot table at 0xafffe000 rom_table_end = 0xafffe000 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0xafffe000 to 0xb0000000 Adding high table area uma_memory_start=0xb0000000, uma_memory_size=0x10000000 coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-00000000affeffff: RAM 3. 00000000afff0000-00000000afffffff: CONFIGURATION TABLES 4. 00000000b0000000-00000000bfffffff: RESERVED 5. 00000000e0000000-00000000efffffff: RESERVED 6. 0000000100000000-000000022fffffff: RAM Wrote coreboot table at: afffe000 - afffe1f8 checksum a615 coreboot table: 504 bytes. POST: 0x9e POST: 0x9d Multiboot Information structure has been written. 0. FREE SPACE b0000000 00000000 1. GDT afff0200 00000200 2. IRQ TABLE afff0400 00001000 3. SMP TABLE afff1400 00001000 4. ACPI afff2400 0000b400 5. SMBIOS afffd800 00000800 6. COREBOOT afffe000 00002000 Searching for fallback/payload Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Got a payload Loading segment from rom address 0xffc35378 data (compression=1) New segment dstaddr 0xe7e04 memsize 0x181fc srcaddr 0xffc353b0 filesize 0xc201 (cleaned up) New segment addr 0xe7e04 size 0x181fc offset 0xffc353b0 filesize 0xc201 Loading segment from rom address 0xffc35394 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c201 lb: [0x0000000000200000, 0x0000000000338000) Post relocation: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c201 using LZMA [ 0x000e7e04, 00100000, 0x00100000) <- ffc353b0 dest 000e7e04, end 00100000, bouncebuffer afd80000 Loaded segments Jumping to boot code at fc8c0 POST: 0xf8 entry = 0x000fc8c0 lb_start = 0x00200000 lb_size = 0x00138000 adjust = 0xafcb8000 buffer = 0xafd80000 elf_boot_notes = 0x002350a0 adjusted_boot_notes = 0xafeed0a0 Start bios (version 1.6.3-20120203_035348-oldx86) Found mainboard ASUS M5A99X-EVO Found CBFS header at 0xfffffca0 Ram Size=0xafff0000 (0x0000000130000000 high) Relocating init from 0x000e8450 to 0xaffd57a0 (size 42812) CPU Mhz=800