coreboot-4.0-2002-gee77cf1-dirty Fri Feb 3 03:22:33 CET 2012 starting... BSP Family_Model: 00100fa0 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000 microcode: patch id to apply = 0x010000bf microcode: updated to patch id = 0x010000bf success POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 SB900 - Early.c - get_sbdn - Start. SB900 - Early.c - get_sbdn - End. cpuSetAMDPCI 00 done Prep FID/VID Node:00 P-state info in MSRC001_0064 is invalid !!! P-state info in MSRc0010064 is invalid !!! F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001016 F3xDC: 0000611a POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 POST: 0x37 started ap apicid: PPPOPOPOSOTSSOSST:TT::T: 0 :x00 0x0xxx3333300000 c cc occoorrrooerreeexxexx:x:: : : --- ----------- -{ {{ {{A AAPPPAAPPIIICCIICCCIIIDDIIDD D= === = 0 0013400 25 NNN NNOOODDDOODDEEEIIEEIIDDDI DD = == = =0 0 0000000 0 CC CCOCOORROROEREERIEIEIDDIDI D D= = == =00 004130}25}} }} ------------- -- * AmmmmmiPiiiiccc cc0rrrrroo1ooocccccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000 startmmmemmiiidiiccccc rr rrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff mmmm*m iiiiicccAccrrrrrPoo oooccccc0o2oooodddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss sccccppctppuuuupaSurSSSeeeSteeettttAAAtdA MMMMADDM DDMMMMDSMSSSRRRSRR * AP 0d 3oddddoonoonnnnee eee stiiiiiannnnrinttiiiittte_tf____dff iffdiiii dvdddvvvviidiiiddd_da____aapaa(pppp((s((ssssttatttaaagaeggggee1ee)1111)) )) aapaaapppipciiiicccicdiiiidd:dd:::: 0 000052 413 FFFFF*I IIIIDDDADDPVVVVVIII IIDDDDD0 4 ooooonnnnn AAAAAPPPPP::::: 0000041325 started * AP 05started POST: 0x38 rs780_early_setup() fam10_optimization() rs780_por_init Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 POST: 0x39 FIDVID on BSP, APIC_id: 00 BSP fid = 0 Wait for AP stage 1: ap_apicid = 1 readback = 1000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2 readback = 2000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 3 readback = 3000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 4 readback = 4000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 5 readback = 5000001 common_fid(packed) = 0 common_fid = 0 POST: 0x3a End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 rs780_htinit cpu_ht_freq=b. rs780_htinit: HT3 mode ...WARM RESET... coreboot-4.0-2002-gee77cf1-dirty Fri Feb 3 03:22:33 CET 2012 starting... BSP Family_Model: 00100fa0 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000 microcode: patch id to apply = 0x010000bf microcode: updated to patch id = 0x010000bf success POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 SB900 - Early.c - get_sbdn - Start. SB900 - Early.c - get_sbdn - End. cpuSetAMDPCI 00 done Prep FID/VID Node:00 P-state info in MSRC001_0064 is invalid !!! P-state info in MSRc0010064 is invalid !!! F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001016 F3xDC: 0000611a POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 POST: 0x37 started ap apicid: PPPPPOOOOOSSSSSTTTTT::::: 00000xxxxx3333300000 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000014325 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000035421}}}}} --------------- * AmmmmmiiiPiiccccc r0rrrrooo1oocccccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000 startmemmmmidiiiiccc ccrrrrr ooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff mmmm*m iiiiicAccccrrrPrrooooo 0cccccoo2ooodddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss scccctpppcppauuuSSuurSteeeSSeettteAttdAAMMMAA DDDMMDDMMMMMSSSRRRSS RR * AP 0 ddd3ddooooonnnnneeeee stiiiiinnnnnairiiiitttttt_____edfffffii iiidddd dvvvvviiiiiddddd_____ssssstttttaaaaagggggeeeee22222 aaaaapppppiiiiiccccciiiiiddddd::::: 0000025413 * AP 04started * AP 05started POST: 0x38 rs780_early_setup() fam10_optimization() rs780_por_init Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 POST: 0x39 POST: 0x3a End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 rs780_htinit cpu_ht_freq=b. rs780_htinit: HT3 mode POST: 0x3b fill_mem_ctrl() POST: 0x40 raminit_amdmct() raminit_amdmct begin: DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=c DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=10 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=10 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 1000 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 4 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 1000 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f40000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: c00000 Node: 00 base: 03 limit: 23fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:c00000 CPUMemTyping: Bottom32bIO:c00000 CPUMemTyping: Bottom40bIO:2400000 mctAutoInitMCT_D: DQSTiming_D TrainRcvrEn: Status 1100 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 1100 InterleaveNodes_D: ErrStatus 0 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 1100 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D All Done raminit_amdmct end: POST: 0x41 POST: 0x42 v_esp=000cbef8 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1277952 bytes), entry @ 0x200000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-4.0-2002-gee77cf1-dirty Fri Feb 3 03:22:33 CET 2012 booting... POST: 0x40 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Mainboard ASUS M5A99X-EVO Enable. dev=0x002338dc m5a99x_evo_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000 m5a99x_evo_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000002 m5a99x_evo_enable: uma size 0x10000000, memory start 0xb0000000 m5a99x_evo_enable, w00t?! m5a99x_evo_enable, cya enable?! Enumerating buses... starting with root now scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... cpu_bus_scan: starting... PCI: 00:18.3 siblings=5 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled CPU: APIC: 04 enabled CPU: APIC: 05 enabled cpu_bus_scan: done. PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled POST: 0x25 amdfam10_scan_chains: starting... amdfam10_scan_chains: link: 00233c50 PCI: Using configuration type 1 rs780_enable: dev=00233ea8, VID_DID=0x5a141002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() addr=e0000000,bus=0,devfn=40 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8 NB_PCI_REG04 = 2. NB_PCI_REG84 = 3000095. NB_PCI_REG4C = 52042. rs780_enable: done PCI: 00:00.0 [1002/5a14] enabled Capability: type 0x08 @ 0xf0 flags: 0xa803 Capability: type 0x08 @ 0xf0 Capability: type 0x08 @ 0xc4 flags: 0x0281 PCI: pci_scan_bus for bus 00 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff PCI: pci_scan_bus upper limit too big. Using 0xff. POST: 0x24 rs780_enable: dev=00233ea8, VID_DID=0x5a141002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8 NB_PCI_REG04 = 2. NB_PCI_REG84 = 3000095. NB_PCI_REG4C = 52042. rs780_enable: done PCI: 00:00.0 [1002/5a14] enabled