1 coreboot-4.0-2004-g9ed8bda-dirty Fri Feb 3 18:58:08 CET 2012 starting...
\r
3 BSP Family_Model: 00100fa0
\r
4 *sysinfo range: [000cc000,000cf360]
\r
6 cpu_init_detectedx = 00000000
\r
7 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000
\r
8 microcode: patch id to apply = 0x010000bf
\r
9 microcode: updated to patch id = 0x010000bf success
\r
17 SB900 - Early.c - get_sbdn - Start.
\r
18 SB900 - Early.c - get_sbdn - End.
\r
19 cpuSetAMDPCI 00 done
\r
20 Prep FID/VID Node:00
\r
21 P-state info in MSRC001_0064 is invalid !!!
\r
22 P-state info in MSRc0010064 is invalid !!!
\r
31 init node: 00 cores: 05
\r
32 Start other core - nodeid: 00 cores: 05
\r
34 started ap apicid: PPPPPOOOOOSSSSSTTTTT::::: 00000xxxxx3333300000
\r\r\r\r\r
39 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000014253 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000031245}}}}} ---------------
\r\r\r\r\r
44 * AmmmmmPiiiiicc cccrrrrr0o1oooocccccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000
\r\r\r\r\r
49 startmemmmmiiiidi
\rcccccrr
50 rrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff
\r\r\r\r\r
55 mmmm*miiiii cAccccrrrPrrooooo c0ccccoooo2odddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss
\r\r\r\r\r
65 sccccpctpppuuuupaurSSSSeeSteetttteetdAAAAMMA
\rMMDDDDM
66 DMMMMSSMSSRRRRS R * AP 0 ddddd3ooooonnnnneeeee
\r\r\r\r\r
71 stiiiiinnnnnairiiiitttttt_____effdfffiiii
\ri
72 dddddvvvvviiiiiddddd_____aaaaappppp(((((ssssstttttaaaaagggggeeeee11111))))) aaaaapppppiiiiiccccciiiiiddddd::::: 0000043125
\r\r\r\r\r
77 FFF*FFIIIII DADDDDVVVPVVIIIII D0DDDD 4 ooooonnnnn AAAAAPPPPP::::: 0000054312
\r\r\r\r\r
87 fam10_optimization()
\r
90 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440
\r
92 FIDVID on BSP, APIC_id: 00
\r
94 Wait for AP stage 1: ap_apicid = 1
\r
96 common_fid(packed) = 0
\r
97 Wait for AP stage 1: ap_apicid = 2
\r
99 common_fid(packed) = 0
\r
100 Wait for AP stage 1: ap_apicid = 3
\r
102 common_fid(packed) = 0
\r
103 Wait for AP stage 1: ap_apicid = 4
\r
105 common_fid(packed) = 0
\r
106 Wait for AP stage 1: ap_apicid = 5
\r
108 common_fid(packed) = 0
\r
111 End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440
\r
112 rs780_htinit cpu_ht_freq=b.
\r
113 rs780_htinit: HT3 mode
\r
119 coreboot-4.0-2004-g9ed8bda-dirty Fri Feb 3 18:58:08 CET 2012 starting...
\r
121 BSP Family_Model: 00100fa0
\r
122 *sysinfo range: [000cc000,000cf360]
\r
124 cpu_init_detectedx = 00000000
\r
125 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000
\r
126 microcode: patch id to apply = 0x010000bf
\r
127 microcode: updated to patch id = 0x010000bf success
\r
132 Enter amd_ht_init()
\r
135 SB900 - Early.c - get_sbdn - Start.
\r
136 SB900 - Early.c - get_sbdn - End.
\r
137 cpuSetAMDPCI 00 done
\r
138 Prep FID/VID Node:00
\r
139 P-state info in MSRC001_0064 is invalid !!!
\r
140 P-state info in MSRc0010064 is invalid !!!
\r
148 start_other_cores()
\r
149 init node: 00 cores: 05
\r
150 Start other core - nodeid: 00 cores: 05
\r
152 started ap apicid: PPPPPOOOOOSSSSSTTTTT::::: 00000xxxxx3333300000
\r\r\r\r\r
157 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000041352 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000015342}}}}} ---------------
\r\r\r\r\r
162 * AmmmmmPiiiii cccccrrrrr0oooo1occcccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000
\r\r\r\r\r
167 startmmemmmiiiidiccc
\rccrr
168 rrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff
\r\r\r\r\r
173 mm*mmm iiiiicccccArrrrrPoooo occc0ccooo2oodddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss
\r\r\r\r\r
183 scccctpcpauppprSuuuueSSSStteeeeettttdAAAA
\rMAMMM
184 DMDDMDDMMMSMRSSSSR RRR * AP 0 3dddddooooonnnnneeeee
\r\r\r\r\r
189 stiiiiannnniriiiinttttit___te_ff_dffiif
\riidi
190 ddddvvvviiviidddid____ds_sssttsttaaaataggggeegeee22222 aa aapppapiiiipciccciiciiddddid:::: : 000 023410
\r5
\r\r\r
199 rs780_early_setup()
\r
200 fam10_optimization()
\r
203 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440
\r
206 End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440
\r
207 rs780_htinit cpu_ht_freq=b.
\r
208 rs780_htinit: HT3 mode
\r
213 raminit_amdmct begin:
\r
214 DIMMPresence: DIMMValid=c
\r
215 DIMMPresence: DIMMPresent=c
\r
216 DIMMPresence: RegDIMMPresent=0
\r
217 DIMMPresence: DimmECCPresent=0
\r
218 DIMMPresence: DimmPARPresent=0
\r
219 DIMMPresence: Dimmx4Present=0
\r
220 DIMMPresence: Dimmx8Present=c
\r
221 DIMMPresence: Dimmx16Present=0
\r
222 DIMMPresence: DimmPlPresent=0
\r
223 DIMMPresence: DimmDRPresent=c
\r
224 DIMMPresence: DimmQRPresent=0
\r
225 DIMMPresence: DATAload[0]=2
\r
226 DIMMPresence: MAload[0]=10
\r
227 DIMMPresence: MAdimms[0]=1
\r
228 DIMMPresence: DATAload[1]=2
\r
229 DIMMPresence: MAload[1]=10
\r
230 DIMMPresence: MAdimms[1]=1
\r
231 DIMMPresence: Status 1000
\r
232 DIMMPresence: ErrStatus 0
\r
233 DIMMPresence: ErrCode 0
\r
236 DCTInit_D: mct_DIMMPresence Done
\r
237 SPDCalcWidth: Status 1000
\r
238 SPDCalcWidth: ErrStatus 0
\r
239 SPDCalcWidth: ErrCode 0
\r
241 DCTInit_D: mct_SPDCalcWidth Done
\r
242 SPDGetTCL_D: DIMMCASL 4
\r
243 SPDGetTCL_D: DIMMAutoSpeed 4
\r
244 SPDGetTCL_D: Status 1000
\r
245 SPDGetTCL_D: ErrStatus 0
\r
246 SPDGetTCL_D: ErrCode 0
\r
249 AutoCycTiming: Status 1000
\r
250 AutoCycTiming: ErrStatus 0
\r
251 AutoCycTiming: ErrCode 0
\r
252 AutoCycTiming: Done
\r
254 DCTInit_D: AutoCycTiming_D Done
\r
255 SPDSetBanks: CSPresent c
\r
256 SPDSetBanks: Status 1000
\r
257 SPDSetBanks: ErrStatus 0
\r
258 SPDSetBanks: ErrCode 0
\r
261 AfterStitch pDCTstat->NodeSysBase = 0
\r
262 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff
\r
263 StitchMemory: Status 1000
\r
264 StitchMemory: ErrStatus 0
\r
265 StitchMemory: ErrCode 0
\r
268 InterleaveBanks_D: Status 1000
\r
269 InterleaveBanks_D: ErrStatus 0
\r
270 InterleaveBanks_D: ErrCode 0
\r
271 InterleaveBanks_D: Done
\r
273 AutoConfig_D: DramControl: 2a06
\r
274 AutoConfig_D: DramTimingLo: 90092
\r
275 AutoConfig_D: DramConfigMisc: 0
\r
276 AutoConfig_D: DramConfigMisc2: 0
\r
277 AutoConfig_D: DramConfigLo: 10000
\r
278 AutoConfig_D: DramConfigHi: f40000b
\r
279 AutoConfig: Status 1000
\r
280 AutoConfig: ErrStatus 0
\r
281 AutoConfig: ErrCode 0
\r
284 DCTInit_D: AutoConfig_D Done
\r
285 DCTInit_D: PlatformSpec_D Done
\r
286 DCTInit_D: StartupDCT_D
\r
287 DCTInit_D: mct_DIMMPresence Done
\r
288 SPDCalcWidth: Status 1000
\r
289 SPDCalcWidth: ErrStatus 0
\r
290 SPDCalcWidth: ErrCode 0
\r
292 DCTInit_D: mct_SPDCalcWidth Done
\r
293 AutoCycTiming: Status 1000
\r
294 AutoCycTiming: ErrStatus 0
\r
295 AutoCycTiming: ErrCode 0
\r
296 AutoCycTiming: Done
\r
298 DCTInit_D: AutoCycTiming_D Done
\r
299 SPDSetBanks: CSPresent c
\r
300 SPDSetBanks: Status 1000
\r
301 SPDSetBanks: ErrStatus 0
\r
302 SPDSetBanks: ErrCode 0
\r
305 AfterStitch pDCTstat->NodeSysBase = 0
\r
306 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe
\r
307 StitchMemory: Status 1000
\r
308 StitchMemory: ErrStatus 0
\r
309 StitchMemory: ErrCode 0
\r
312 InterleaveBanks_D: Status 1000
\r
313 InterleaveBanks_D: ErrStatus 0
\r
314 InterleaveBanks_D: ErrCode 0
\r
315 InterleaveBanks_D: Done
\r
317 AutoConfig_D: DramControl: 2a06
\r
318 AutoConfig_D: DramTimingLo: 90092
\r
319 AutoConfig_D: DramConfigMisc: 0
\r
320 AutoConfig_D: DramConfigMisc2: 0
\r
321 AutoConfig_D: DramConfigLo: 10000
\r
322 AutoConfig_D: DramConfigHi: f40000b
\r
323 AutoConfig: Status 1000
\r
324 AutoConfig: ErrStatus 0
\r
325 AutoConfig: ErrCode 0
\r
328 DCTInit_D: AutoConfig_D Done
\r
329 DCTInit_D: PlatformSpec_D Done
\r
330 DCTInit_D: StartupDCT_D
\r
331 mctAutoInitMCT_D: SyncDCTsReady_D
\r
332 mctAutoInitMCT_D: HTMemMapInit_D
\r
333 Node: 00 base: 00 limit: 1ffffff BottomIO: e00000
\r
334 Node: 00 base: 03 limit: 21fffff
\r
335 Node: 01 base: 00 limit: 00
\r
336 Node: 02 base: 00 limit: 00
\r
337 Node: 03 base: 00 limit: 00
\r
338 Node: 04 base: 00 limit: 00
\r
339 Node: 05 base: 00 limit: 00
\r
340 Node: 06 base: 00 limit: 00
\r
341 Node: 07 base: 00 limit: 00
\r
342 mctAutoInitMCT_D: CPUMemTyping_D
\r
343 CPUMemTyping: Cache32bTOP:e00000
\r
344 CPUMemTyping: Bottom32bIO:e00000
\r
345 CPUMemTyping: Bottom40bIO:2200000
\r
346 mctAutoInitMCT_D: DQSTiming_D
\r
347 TrainRcvrEn: Status 1100
\r
348 TrainRcvrEn: ErrStatus 0
\r
349 TrainRcvrEn: ErrCode 0
\r
352 TrainDQSRdWrPos: Status 1100
\r
353 TrainDQSRdWrPos: TrainErrors 0
\r
354 TrainDQSRdWrPos: ErrStatus 0
\r
355 TrainDQSRdWrPos: ErrCode 0
\r
356 TrainDQSRdWrPos: Done
\r
358 TrainDQSRdWrPos: Status 1100
\r
359 TrainDQSRdWrPos: TrainErrors 0
\r
360 TrainDQSRdWrPos: ErrStatus 0
\r
361 TrainDQSRdWrPos: ErrCode 0
\r
362 TrainDQSRdWrPos: Done
\r
364 TrainDQSRdWrPos: Status 1100
\r
365 TrainDQSRdWrPos: TrainErrors 0
\r
366 TrainDQSRdWrPos: ErrStatus 0
\r
367 TrainDQSRdWrPos: ErrCode 0
\r
368 TrainDQSRdWrPos: Done
\r
370 TrainDQSRdWrPos: Status 1100
\r
371 TrainDQSRdWrPos: TrainErrors 0
\r
372 TrainDQSRdWrPos: ErrStatus 0
\r
373 TrainDQSRdWrPos: ErrCode 0
\r
374 TrainDQSRdWrPos: Done
\r
376 mctAutoInitMCT_D: UMAMemTyping_D
\r
377 mctAutoInitMCT_D: :OtherTiming
\r
378 InterleaveNodes_D: Status 1100
\r
379 InterleaveNodes_D: ErrStatus 0
\r
380 InterleaveNodes_D: ErrCode 0
\r
381 InterleaveNodes_D: Done
\r
383 InterleaveChannels_D: Node 0
\r
384 InterleaveChannels_D: Status 1100
\r
385 InterleaveChannels_D: ErrStatus 0
\r
386 InterleaveChannels_D: ErrCode 0
\r
387 InterleaveChannels_D: Node 1
\r
388 InterleaveChannels_D: Status 1000
\r
389 InterleaveChannels_D: ErrStatus 0
\r
390 InterleaveChannels_D: ErrCode 0
\r
391 InterleaveChannels_D: Node 2
\r
392 InterleaveChannels_D: Status 1000
\r
393 InterleaveChannels_D: ErrStatus 0
\r
394 InterleaveChannels_D: ErrCode 0
\r
395 InterleaveChannels_D: Node 3
\r
396 InterleaveChannels_D: Status 1000
\r
397 InterleaveChannels_D: ErrStatus 0
\r
398 InterleaveChannels_D: ErrCode 0
\r
399 InterleaveChannels_D: Node 4
\r
400 InterleaveChannels_D: Status 1000
\r
401 InterleaveChannels_D: ErrStatus 0
\r
402 InterleaveChannels_D: ErrCode 0
\r
403 InterleaveChannels_D: Node 5
\r
404 InterleaveChannels_D: Status 1000
\r
405 InterleaveChannels_D: ErrStatus 0
\r
406 InterleaveChannels_D: ErrCode 0
\r
407 InterleaveChannels_D: Node 6
\r
408 InterleaveChannels_D: Status 1000
\r
409 InterleaveChannels_D: ErrStatus 0
\r
410 InterleaveChannels_D: ErrCode 0
\r
411 InterleaveChannels_D: Node 7
\r
412 InterleaveChannels_D: Status 1000
\r
413 InterleaveChannels_D: ErrStatus 0
\r
414 InterleaveChannels_D: ErrCode 0
\r
415 InterleaveChannels_D: Done
\r
417 mctAutoInitMCT_D: ECCInit_D
\r
419 raminit_amdmct end:
\r
424 Copying data from cache to RAM -- switching to use RAM as stack... Done
\r
426 Disabling cache as ram now
\r
427 Clearing initial memory region: Done
\r
429 Searching for fallback/coreboot_ram
\r
430 Check cmos_layout.bin
\r
431 Check fallback/romstage
\r
432 Check fallback/coreboot_ram
\r
433 Stage: loading fallback/coreboot_ram @ 0x200000 (1277952 bytes), entry @ 0x200000
\r
434 Stage: done loading.
\r
438 coreboot-4.0-2004-g9ed8bda-dirty Fri Feb 3 18:58:08 CET 2012 booting...
\r
440 Enumerating buses...
\r
441 Show all devs...Before device enumeration.
\r
442 Root Device: enabled 1
\r
443 APIC_CLUSTER: 0: enabled 1
\r
444 APIC: 00: enabled 1
\r
445 PCI_DOMAIN: 0000: enabled 1
\r
446 PCI: 00:18.0: enabled 1
\r
447 PCI: 00:00.0: enabled 1
\r
448 PCI: 00:02.0: enabled 1
\r
449 PCI: 00:03.0: enabled 0
\r
450 PCI: 00:04.0: enabled 1
\r
451 PCI: 00:05.0: enabled 0
\r
452 PCI: 00:06.0: enabled 0
\r
453 PCI: 00:07.0: enabled 0
\r
454 PCI: 00:08.0: enabled 0
\r
455 PCI: 00:09.0: enabled 1
\r
456 PCI: 00:0a.0: enabled 1
\r
457 PCI: 00:11.0: enabled 1
\r
458 PCI: 00:12.0: enabled 1
\r
459 PCI: 00:12.2: enabled 1
\r
460 PCI: 00:13.0: enabled 1
\r
461 PCI: 00:13.2: enabled 1
\r
462 PCI: 00:14.0: enabled 1
\r
463 I2C: 00:50: enabled 1
\r
464 I2C: 00:51: enabled 1
\r
465 I2C: 00:52: enabled 1
\r
466 I2C: 00:53: enabled 1
\r
467 PCI: 00:14.1: enabled 1
\r
468 PCI: 00:14.2: enabled 1
\r
469 PCI: 00:14.3: enabled 1
\r
470 PNP: 002e.0: enabled 0
\r
471 PNP: 002e.1: enabled 0
\r
472 PNP: 002e.2: enabled 1
\r
473 PNP: 002e.3: enabled 1
\r
474 PNP: 002e.5: enabled 1
\r
475 PNP: 002e.6: enabled 0
\r
476 PNP: 002e.7: enabled 0
\r
477 PNP: 002e.8: enabled 0
\r
478 PNP: 002e.9: enabled 0
\r
479 PNP: 002e.a: enabled 0
\r
480 PNP: 002e.b: enabled 1
\r
481 PCI: 00:14.4: enabled 0
\r
482 PCI: 00:14.5: enabled 1
\r
483 PCI: 00:14.6: enabled 0
\r
484 PCI: 00:15.0: enabled 1
\r
485 PCI: 00:15.1: enabled 1
\r
486 PCI: 00:15.2: enabled 1
\r
487 PCI: 00:15.3: enabled 1
\r
488 PCI: 00:16.0: enabled 1
\r
489 PCI: 00:16.2: enabled 1
\r
490 PCI: 00:18.1: enabled 1
\r
491 PCI: 00:18.2: enabled 1
\r
492 PCI: 00:18.3: enabled 1
\r
493 PCI: 00:18.4: enabled 1
\r
494 Compare with tree...
\r
495 Root Device: enabled 1
\r
496 APIC_CLUSTER: 0: enabled 1
\r
497 APIC: 00: enabled 1
\r
498 PCI_DOMAIN: 0000: enabled 1
\r
499 PCI: 00:18.0: enabled 1
\r
500 PCI: 00:00.0: enabled 1
\r
501 PCI: 00:02.0: enabled 1
\r
502 PCI: 00:03.0: enabled 0
\r
503 PCI: 00:04.0: enabled 1
\r
504 PCI: 00:05.0: enabled 0
\r
505 PCI: 00:06.0: enabled 0
\r
506 PCI: 00:07.0: enabled 0
\r
507 PCI: 00:08.0: enabled 0
\r
508 PCI: 00:09.0: enabled 1
\r
509 PCI: 00:0a.0: enabled 1
\r
510 PCI: 00:11.0: enabled 1
\r
511 PCI: 00:12.0: enabled 1
\r
512 PCI: 00:12.2: enabled 1
\r
513 PCI: 00:13.0: enabled 1
\r
514 PCI: 00:13.2: enabled 1
\r
515 PCI: 00:14.0: enabled 1
\r
516 I2C: 00:50: enabled 1
\r
517 I2C: 00:51: enabled 1
\r
518 I2C: 00:52: enabled 1
\r
519 I2C: 00:53: enabled 1
\r
520 PCI: 00:14.1: enabled 1
\r
521 PCI: 00:14.2: enabled 1
\r
522 PCI: 00:14.3: enabled 1
\r
523 PNP: 002e.0: enabled 0
\r
524 PNP: 002e.1: enabled 0
\r
525 PNP: 002e.2: enabled 1
\r
526 PNP: 002e.3: enabled 1
\r
527 PNP: 002e.5: enabled 1
\r
528 PNP: 002e.6: enabled 0
\r
529 PNP: 002e.7: enabled 0
\r
530 PNP: 002e.8: enabled 0
\r
531 PNP: 002e.9: enabled 0
\r
532 PNP: 002e.a: enabled 0
\r
533 PNP: 002e.b: enabled 1
\r
534 PCI: 00:14.4: enabled 0
\r
535 PCI: 00:14.5: enabled 1
\r
536 PCI: 00:14.6: enabled 0
\r
537 PCI: 00:15.0: enabled 1
\r
538 PCI: 00:15.1: enabled 1
\r
539 PCI: 00:15.2: enabled 1
\r
540 PCI: 00:15.3: enabled 1
\r
541 PCI: 00:16.0: enabled 1
\r
542 PCI: 00:16.2: enabled 1
\r
543 PCI: 00:18.1: enabled 1
\r
544 PCI: 00:18.2: enabled 1
\r
545 PCI: 00:18.3: enabled 1
\r
546 PCI: 00:18.4: enabled 1
\r
547 Mainboard ASUS M5A99X-EVO Enable. dev=0x00233b5c
\r
548 m5a99x_evo_enable, w00t?!
\r
549 m5a99x_evo_enable, cya enable?!
\r
550 Enumerating buses... starting with root now
\r
551 scan_static_bus for Root Device
\r
552 APIC_CLUSTER: 0 enabled
\r
553 PCI_DOMAIN: 0000 enabled
\r
554 APIC_CLUSTER: 0 scanning...
\r
555 cpu_bus_scan: starting...
\r
556 PCI: 00:18.3 siblings=5
\r
557 CPU: APIC: 00 enabled
\r
558 CPU: APIC: 01 enabled
\r
559 CPU: APIC: 02 enabled
\r
560 CPU: APIC: 03 enabled
\r
561 CPU: APIC: 04 enabled
\r
562 CPU: APIC: 05 enabled
\r
563 cpu_bus_scan: done.
\r
564 PCI_DOMAIN: 0000 scanning...
\r
565 PCI: pci_scan_bus for bus 00
\r
567 pci_scan_bus: before pci_scan_get_dev! devfn: 192
\r
568 pci_scan_bus: after pci_scan_get_dev!
\r
569 pci_scan_bus: before pci_probe_dev!
\r
570 PCI: 00:18.0 [1022/1200] bus ops
\r
571 PCI: 00:18.0 [1022/1200] enabled
\r
572 pci_scan_bus: after pci_probe_dev!
\r
573 pci_scan_bus: before pci_scan_get_dev! devfn: 193
\r
574 pci_scan_bus: after pci_scan_get_dev!
\r
575 pci_scan_bus: before pci_probe_dev!
\r
576 PCI: 00:18.1 [1022/1201] enabled
\r
577 pci_scan_bus: after pci_probe_dev!
\r
578 pci_scan_bus: before pci_scan_get_dev! devfn: 194
\r
579 pci_scan_bus: after pci_scan_get_dev!
\r
580 pci_scan_bus: before pci_probe_dev!
\r
581 PCI: 00:18.2 [1022/1202] enabled
\r
582 pci_scan_bus: after pci_probe_dev!
\r
583 pci_scan_bus: before pci_scan_get_dev! devfn: 195
\r
584 pci_scan_bus: after pci_scan_get_dev!
\r
585 pci_scan_bus: before pci_probe_dev!
\r
586 PCI: 00:18.3 [1022/1203] ops
\r
587 PCI: 00:18.3 [1022/1203] enabled
\r
588 pci_scan_bus: after pci_probe_dev!
\r
589 pci_scan_bus: before pci_scan_get_dev! devfn: 196
\r
590 pci_scan_bus: after pci_scan_get_dev!
\r
591 pci_scan_bus: before pci_probe_dev!
\r
592 PCI: 00:18.4 [1022/1204] enabled
\r
593 pci_scan_bus: after pci_probe_dev!
\r
594 pci_scan_bus: before pci_scan_get_dev! devfn: 197
\r
595 pci_scan_bus: after pci_scan_get_dev!
\r
596 pci_scan_bus: before pci_probe_dev!
\r
597 pci_scan_bus: after pci_probe_dev!
\r
598 pci_scan_bus: before pci_scan_get_dev! devfn: 198
\r
599 pci_scan_bus: after pci_scan_get_dev!
\r
600 pci_scan_bus: before pci_probe_dev!
\r
601 pci_scan_bus: after pci_probe_dev!
\r
602 pci_scan_bus: before pci_scan_get_dev! devfn: 199
\r
603 pci_scan_bus: after pci_scan_get_dev!
\r
604 pci_scan_bus: before pci_probe_dev!
\r
605 pci_scan_bus: after pci_probe_dev!
\r
606 pci_scan_bus: before pci_scan_get_dev! devfn: 200
\r
607 pci_scan_bus: after pci_scan_get_dev!
\r
608 pci_scan_bus: before pci_probe_dev!
\r
609 pci_scan_bus: after pci_probe_dev!
\r
610 pci_scan_bus: before pci_scan_get_dev! devfn: 208
\r
611 pci_scan_bus: after pci_scan_get_dev!
\r
612 pci_scan_bus: before pci_probe_dev!
\r
613 pci_scan_bus: after pci_probe_dev!
\r
614 pci_scan_bus: before pci_scan_get_dev! devfn: 216
\r
615 pci_scan_bus: after pci_scan_get_dev!
\r
616 pci_scan_bus: before pci_probe_dev!
\r
617 pci_scan_bus: after pci_probe_dev!
\r
618 pci_scan_bus: before pci_scan_get_dev! devfn: 224
\r
619 pci_scan_bus: after pci_scan_get_dev!
\r
620 pci_scan_bus: before pci_probe_dev!
\r
621 pci_scan_bus: after pci_probe_dev!
\r
622 pci_scan_bus: before pci_scan_get_dev! devfn: 232
\r
623 pci_scan_bus: after pci_scan_get_dev!
\r
624 pci_scan_bus: before pci_probe_dev!
\r
625 pci_scan_bus: after pci_probe_dev!
\r
626 pci_scan_bus: before pci_scan_get_dev! devfn: 240
\r
627 pci_scan_bus: after pci_scan_get_dev!
\r
628 pci_scan_bus: before pci_probe_dev!
\r
629 pci_scan_bus: after pci_probe_dev!
\r
630 pci_scan_bus: before pci_scan_get_dev! devfn: 248
\r
631 pci_scan_bus: after pci_scan_get_dev!
\r
632 pci_scan_bus: before pci_probe_dev!
\r
633 pci_scan_bus: after pci_probe_dev!
\r
635 amdfam10_scan_chains: starting...
\r
636 amdfam10_scan_chains: link: 00233ed0
\r
637 amdfam10_scan_chain: starting...
\r
638 amdfam10_scan_chain: link_type: 0x00000007
\r
639 amdfam10_scan_chain: link_type: 0x00000007
\r
640 amdfam10_scan_chain: before get_ht_c_index
\r
641 amdfam10_scan_chain: after get_ht_c_index
\r
642 amdfam10_scan_chain: before set_config_map_reg
\r
643 amdfam10_scan_chain: after set_config_map_reg
\r
644 amdfam10_scan_chain: before hypertransport_scan_chain
\r
645 hypertransport_scan_chain: before ht_collapse_early_enumeration
\r
646 hypertransport_scan_chain: after ht_collapse_early_enumeration
\r
647 hypertransport_scan_chain: before ht_scan_get_devs
\r
648 hypertransport_scan_chain: after ht_scan_get_devs
\r
649 hypertransport_scan_chain: before pci_probe_dev
\r
650 PCI: Using configuration type 1
\r
651 rs780_enable: dev=00234128, VID_DID=0x5a141002
\r
652 Bus-0, Dev-0, Fun-0.
\r
654 addr=e0000000,bus=0,devfn=40
\r
655 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
\r
657 NB_PCI_REG84 = 3000095.
\r
658 NB_PCI_REG4C = 52042.
\r
660 PCI: 00:00.0 [1002/5a14] enabled
\r
661 hypertransport_scan_chain: after pci_probe_dev
\r
662 hypertransport_scan_chain: before ht_lookup_slave_capability
\r
663 Capability: type 0x08 @ 0xf0
\r
665 Capability: type 0x08 @ 0xf0
\r
666 Capability: type 0x08 @ 0xc4
\r
668 hypertransport_scan_chain: after ht_lookup_slave_capability
\r
669 hypertransport_scan_chain: end_of_chain. w00t!
\r
670 hypertransport_scan_chain: before pci_scan_bus!
\r
671 PCI: pci_scan_bus for bus 00
\r
672 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff
\r
673 PCI: pci_scan_bus upper limit too big. Using 0xff.
\r
675 pci_scan_bus: before pci_scan_get_dev! devfn: 0
\r
676 pci_scan_bus: after pci_scan_get_dev!
\r
677 pci_scan_bus: before pci_probe_dev!
\r
678 rs780_enable: dev=00234128, VID_DID=0x5a141002
\r
679 Bus-0, Dev-0, Fun-0.
\r
681 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
\r
683 NB_PCI_REG84 = 3000095.
\r
684 NB_PCI_REG4C = 52042.
\r
686 PCI: 00:00.0 [1002/5a14] enabled
\r
687 pci_scan_bus: after pci_probe_dev!
\r
688 pci_scan_bus: before pci_scan_get_dev! devfn: 1
\r
689 pci_scan_bus: after pci_scan_get_dev!
\r
690 pci_scan_bus: before pci_probe_dev!
\r
691 pci_scan_bus: after pci_probe_dev!
\r
692 pci_scan_bus: before pci_scan_get_dev! devfn: 2
\r
693 pci_scan_bus: after pci_scan_get_dev!
\r
694 pci_scan_bus: before pci_probe_dev!
\r
695 pci_scan_bus: after pci_probe_dev!
\r
696 pci_scan_bus: before pci_scan_get_dev! devfn: 3
\r
697 pci_scan_bus: after pci_scan_get_dev!
\r
698 pci_scan_bus: before pci_probe_dev!
\r
699 pci_scan_bus: after pci_probe_dev!
\r
700 pci_scan_bus: before pci_scan_get_dev! devfn: 4
\r
701 pci_scan_bus: after pci_scan_get_dev!
\r
702 pci_scan_bus: before pci_probe_dev!
\r
703 pci_scan_bus: after pci_probe_dev!
\r
704 pci_scan_bus: before pci_scan_get_dev! devfn: 5
\r
705 pci_scan_bus: after pci_scan_get_dev!
\r
706 pci_scan_bus: before pci_probe_dev!
\r
707 pci_scan_bus: after pci_probe_dev!
\r
708 pci_scan_bus: before pci_scan_get_dev! devfn: 6
\r
709 pci_scan_bus: after pci_scan_get_dev!
\r
710 pci_scan_bus: before pci_probe_dev!
\r
711 pci_scan_bus: after pci_probe_dev!
\r
712 pci_scan_bus: before pci_scan_get_dev! devfn: 7
\r
713 pci_scan_bus: after pci_scan_get_dev!
\r
714 pci_scan_bus: before pci_probe_dev!
\r
715 pci_scan_bus: after pci_probe_dev!
\r
716 pci_scan_bus: before pci_scan_get_dev! devfn: 8
\r
717 pci_scan_bus: after pci_scan_get_dev!
\r
718 pci_scan_bus: before pci_probe_dev!
\r
719 pci_scan_bus: after pci_probe_dev!
\r
721 PCI: Left over static devices:
\r
749 PCI: Check your devicetree.cb.
\r
750 PCI: pci_scan_bus returning with max=000
\r
752 hypertransport_scan_chain: after pci_scan_bus!
\r
753 amdfam10_scan_chain: after hypertransport_scan_chain
\r
754 amdfam10_scan_chain: before set_config_map_reg
\r
755 amdfam10_scan_chain: after set_config_map_reg
\r
756 amdfam10_scan_chain: before store_ht_c_conf_bus
\r
757 amdfam10_scan_chain: after store_ht_c_conf_bus
\r
758 amdfam10_scan_chain: done.
\r
759 amdfam10_scan_chains: link: 00278000
\r
760 amdfam10_scan_chains: link: 00278018
\r
761 amdfam10_scan_chains: link: 00278030
\r
762 amdfam10_scan_chains: link: 00278048
\r
763 amdfam10_scan_chains: link: 00278060
\r
764 amdfam10_scan_chains: link: 00278078
\r
765 amdfam10_scan_chains: link: 00278090
\r
766 amdfam10_scan_chains: link2: 00233ed0
\r
767 amdfam10_scan_chains: link2: 00278000
\r
768 amdfam10_scan_chain: starting...
\r
769 amdfam10_scan_chain: link_type: 0x00000000
\r
770 amdfam10_scan_chains: link2: 00278018
\r
771 amdfam10_scan_chain: starting...
\r
772 amdfam10_scan_chain: link_type: 0x00000000
\r
773 amdfam10_scan_chains: link2: 00278030
\r
774 amdfam10_scan_chain: starting...
\r
775 amdfam10_scan_chain: link_type: 0x00000000
\r
776 amdfam10_scan_chains: link2: 00278048
\r
777 amdfam10_scan_chain: starting...
\r
778 amdfam10_scan_chains: link2: 00278060
\r
779 amdfam10_scan_chain: starting...
\r
780 amdfam10_scan_chain: link_type: 0x00000000
\r
781 amdfam10_scan_chains: link2: 00278078
\r
782 amdfam10_scan_chain: starting...
\r
783 amdfam10_scan_chain: link_type: 0x00000000
\r
784 amdfam10_scan_chains: link2: 00278090
\r
785 amdfam10_scan_chain: starting...
\r
786 amdfam10_scan_chain: link_type: 0x00000000
\r
787 amdfam10_scan_chains: done.
\r
788 PCI: pci_scan_bus returning with max=000
\r
790 PCI_DOMAIN: 0000 passpw: enabled
\r
791 scan_static_bus for Root Device done
\r
794 ===============Enumeration done!========
\r
795 Allocating resources...
\r
796 Reading resources...
\r
797 Root Device read_resources bus 0 link: 0
\r
798 APIC_CLUSTER: 0 read_resources bus 0 link: 0
\r
799 APIC: 00 missing read_resources
\r
800 APIC: 01 missing read_resources
\r
801 APIC: 02 missing read_resources
\r
802 APIC: 03 missing read_resources
\r
803 APIC: 04 missing read_resources
\r
804 APIC: 05 missing read_resources
\r
805 APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
\r
806 PCI_DOMAIN: 0000 read_resources bus 0 link: 0
\r
807 PCI: 00:18.0 read_resources bus 0 link: 0
\r
808 PCI: 00:18.0 read_resources bus 0 link: 0 done
\r
809 PCI: 00:18.0 read_resources bus 0 link: 1
\r
810 PCI: 00:18.0 read_resources bus 0 link: 1 done
\r
811 PCI: 00:18.0 read_resources bus 0 link: 2
\r
812 PCI: 00:18.0 read_resources bus 0 link: 2 done
\r
813 PCI: 00:18.0 read_resources bus 0 link: 3
\r
814 PCI: 00:18.0 read_resources bus 0 link: 3 done
\r
815 PCI: 00:18.0 read_resources bus 0 link: 4
\r
816 PCI: 00:18.0 read_resources bus 0 link: 4 done
\r
817 PCI: 00:18.0 read_resources bus 0 link: 5
\r
818 PCI: 00:18.0 read_resources bus 0 link: 5 done
\r
819 PCI: 00:18.0 read_resources bus 0 link: 6
\r
820 PCI: 00:18.0 read_resources bus 0 link: 6 done
\r
821 PCI: 00:18.0 read_resources bus 0 link: 7
\r
822 PCI: 00:18.0 read_resources bus 0 link: 7 done
\r
823 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
\r
824 Root Device read_resources bus 0 link: 0 done
\r
825 Done reading resources.
\r
826 Show resources in subtree (Root Device)...After reading.
\r
827 Root Device child on link 0 APIC_CLUSTER: 0
\r
828 APIC_CLUSTER: 0 child on link 0 APIC: 00
\r
835 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
\r
836 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
\r
837 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
\r
838 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
\r
839 PCI: 00:18.0 child on link 0 PCI: 00:00.0
\r
840 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b0
\r
841 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b8
\r
842 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8
\r
844 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 201 index 1c
\r
848 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
\r
850 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
\r
851 PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
\r
852 PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
\r
853 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
\r
854 PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
\r
855 PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
\r
856 PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done
\r
857 PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
\r
858 PCI: 00:00.0 1c * [0x0 - 0xfffffff] mem
\r
859 PCI: 00:18.0 compute_resources_mem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffffff done
\r
860 PCI: 00:18.0 10b8 * [0x0 - 0xfffffff] mem
\r
861 PCI: 00:18.3 94 * [0x10000000 - 0x13ffffff] mem
\r
862 PCI_DOMAIN: 0000 compute_resources_mem: base: 14000000 size: 14000000 align: 28 gran: 0 limit: ffffffff done
\r
863 avoid_fixed_resources: PCI_DOMAIN: 0000
\r
864 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
\r
865 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
\r
866 constrain_resources: PCI_DOMAIN: 0000
\r
867 constrain_resources: PCI: 00:18.0
\r
868 constrain_resources: PCI: 00:00.0
\r
869 constrain_resources: PCI: 00:18.1
\r
870 constrain_resources: PCI: 00:18.2
\r
871 constrain_resources: PCI: 00:18.3
\r
872 constrain_resources: PCI: 00:18.4
\r
873 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
\r
874 lim->base 00000000 lim->limit 0000ffff
\r
875 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
\r
876 lim->base 00000000 lim->limit dfffffff
\r
877 Setting resources...
\r
878 PCI_DOMAIN: 0000 allocate_resources_io: base:0 size:0 align:0 gran:0 limit:ffff
\r
879 PCI_DOMAIN: 0000 allocate_resources_io: next_base: 0 size: 0 align: 0 gran: 0 done
\r
880 PCI: 00:18.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
\r
881 PCI: 00:18.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
\r
882 PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:14000000 align:28 gran:0 limit:dfffffff
\r
883 Assigned: PCI: 00:18.0 10b8 * [0xc0000000 - 0xcfffffff] mem
\r
884 Assigned: PCI: 00:18.3 94 * [0xd0000000 - 0xd3ffffff] mem
\r
885 PCI_DOMAIN: 0000 allocate_resources_mem: next_base: d4000000 size: 14000000 align: 28 gran: 0 done
\r
886 PCI: 00:18.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
\r
887 PCI: 00:18.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
\r
888 PCI: 00:18.0 allocate_resources_mem: base:c0000000 size:10000000 align:28 gran:20 limit:dfffffff
\r
889 Assigned: PCI: 00:00.0 1c * [0xc0000000 - 0xcfffffff] mem
\r
890 PCI: 00:18.0 allocate_resources_mem: next_base: d0000000 size: 10000000 align: 28 gran: 20 done
\r
891 Root Device assign_resources, bus 0 link: 0
\r
892 split: 64K table at =bfff0000
\r
893 0: mmio_basek=00300000, basek=00400000, limitk=00880000
\r
894 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
\r
895 PCI: 00:18.0 10b0 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 prefmem <node 0 link 0>
\r
896 PCI: 00:18.0 10b8 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x14 mem <node 0 link 0>
\r
897 PCI: 00:18.0 10d8 <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c io <node 0 link 0>
\r
898 PCI: 00:18.0 assign_resources, bus 0 link: 0
\r
899 PCI: 00:00.0 1c <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c mem64
\r
900 PCI: 00:18.0 assign_resources, bus 0 link: 0
\r
901 PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem <gart>
\r
902 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
\r
903 Root Device assign_resources, bus 0 link: 0
\r
904 Done setting resources.
\r
905 Show resources in subtree (Root Device)...After assigning values.
\r
906 Root Device child on link 0 APIC_CLUSTER: 0
\r
907 APIC_CLUSTER: 0 child on link 0 APIC: 00
\r
914 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
\r
915 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
\r
916 PCI_DOMAIN: 0000 resource base c0000000 size 14000000 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
\r
917 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
\r
918 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
\r
919 PCI_DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20
\r
920 PCI_DOMAIN: 0000 resource base 100000000 size 120000000 align 0 gran 0 limit 0 flags e0004200 index 30
\r
921 PCI: 00:18.0 child on link 0 PCI: 00:00.0
\r
922 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081200 index 10b0
\r
923 PCI: 00:18.0 resource base c0000000 size 10000000 align 28 gran 20 limit dfffffff flags 60080200 index 10b8
\r
924 PCI: 00:18.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080100 index 10d8
\r
926 PCI: 00:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60000201 index 1c
\r
930 PCI: 00:18.3 resource base d0000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94
\r
932 Done allocating resources.
\r
934 Enabling resources...
\r
935 PCI: 00:18.0 cmd <- 00
\r
936 PCI: 00:18.1 subsystem <- 1043/843e
\r
937 PCI: 00:18.1 cmd <- 00
\r
938 PCI: 00:18.2 subsystem <- 1043/843e
\r
939 PCI: 00:18.2 cmd <- 00
\r
940 PCI: 00:18.3 cmd <- 00
\r
941 PCI: 00:18.4 subsystem <- 1043/843e
\r
942 PCI: 00:18.4 cmd <- 00
\r
943 PCI: 00:00.0 subsystem <- 1043/843e
\r
944 PCI: 00:00.0 cmd <- 02
\r
946 Initializing devices...
\r
948 APIC_CLUSTER: 0 init
\r
949 start_eip=0x0000a000, offset=0x00200000, code_size=0x0000005b
\r
950 Initializing CPU #0
\r
951 CPU: vendor AMD device 100fa0
\r
952 CPU: family 10, model 0a, stepping 00
\r
953 nodeid = 00, coreid = 00
\r
957 Setting fixed MTRRs(0-88) type: UC
\r
958 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
\r
959 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
\r
965 INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} ---
\r
967 Issuing SOFT_RESET...
\r
970 coreboot-4.0-2004-g9ed8bda-dirty Fri Feb 3 18:58:08 CET 2012 starting...
\r
972 BSP Family_Model: 00100fa0
\r
973 *sysinfo range: [000cc000,000cf360]
\r
975 cpu_init_detectedx = 00000000
\r
976 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000
\r
977 microcode: patch id to apply = 0x010000bf
\r
978 microcode: updated to patch id = 0x010000bf success
\r
983 Enter amd_ht_init()
\r
986 SB900 - Early.c - get_sbdn - Start.
\r
987 SB900 - Early.c - get_sbdn - End.
\r
988 cpuSetAMDPCI 00 done
\r
989 Prep FID/VID Node:00
\r
990 P-state info in MSRC001_0064 is invalid !!!
\r
991 P-state info in MSRc0010064 is invalid !!!
\r
999 start_other_cores()
\r
1000 init node: 00 cores: 05
\r
1001 Start other core - nodeid: 00 cores: 05
\r
1003 started ap apicid: PPPPPOOOOOSSSSSTTTTT::::: 00000xxxxx3333300000
\r\r\r\r\r
1008 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000035421 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000024351}}}}} ---------------
\r\r\r\r\r
1013 * AmmmmmPiiiiiccccc rrrr0roooo1occcccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000
\r\r\r\r\r
1018 startmmemmmiiidiiccc
\rccrr
1019 rrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff
\r\r\r\r\r
1024 m*mmmm iiiiicccccArrrrProooo occc0ccoo2ooodddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss
\r\r\r\r\r
1034 scccctpcpauppprSuuuueSSSStteeeeettttdAAAA
\rMAMMM
1035 DMDDMDDMMMSMRSSSSR RRR * AP 0 3dddddooooonnnnneeeee
\r\r\r\r\r
1040 stiiiiannnniiiiinrttttit___te_ff_dffiif
\riidi
1041 ddddvvvviiviidddid____ds_sssttsttaaataaggggegeeee22222 a aaapppapiiiipciccciiciidddidd:::: : 000 0514203
\r\r\r\r
1050 rs780_early_setup()
\r
1051 fam10_optimization()
\r
1054 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440
\r
1057 End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440
\r
1058 rs780_htinit cpu_ht_freq=b.
\r
1059 rs780_htinit: HT3 mode
\r
1064 raminit_amdmct begin:
\r
1065 DIMMPresence: DIMMValid=c
\r
1066 DIMMPresence: DIMMPresent=c
\r
1067 DIMMPresence: RegDIMMPresent=0
\r
1068 DIMMPresence: DimmECCPresent=0
\r
1069 DIMMPresence: DimmPARPresent=0
\r
1070 DIMMPresence: Dimmx4Present=0
\r
1071 DIMMPresence: Dimmx8Present=c
\r
1072 DIMMPresence: Dimmx16Present=0
\r
1073 DIMMPresence: DimmPlPresent=0
\r
1074 DIMMPresence: DimmDRPresent=c
\r
1075 DIMMPresence: DimmQRPresent=0
\r
1076 DIMMPresence: DATAload[0]=2
\r
1077 DIMMPresence: MAload[0]=10
\r
1078 DIMMPresence: MAdimms[0]=1
\r
1079 DIMMPresence: DATAload[1]=2
\r
1080 DIMMPresence: MAload[1]=10
\r
1081 DIMMPresence: MAdimms[1]=1
\r
1082 DIMMPresence: Status 1000
\r
1083 DIMMPresence: ErrStatus 0
\r
1084 DIMMPresence: ErrCode 0
\r
1085 DIMMPresence: Done
\r
1087 DCTInit_D: mct_DIMMPresence Done
\r
1088 SPDCalcWidth: Status 1000
\r
1089 SPDCalcWidth: ErrStatus 0
\r
1090 SPDCalcWidth: ErrCode 0
\r
1091 SPDCalcWidth: Done
\r
1092 DCTInit_D: mct_SPDCalcWidth Done
\r
1093 SPDGetTCL_D: DIMMCASL 4
\r
1094 SPDGetTCL_D: DIMMAutoSpeed 4
\r
1095 SPDGetTCL_D: Status 1000
\r
1096 SPDGetTCL_D: ErrStatus 0
\r
1097 SPDGetTCL_D: ErrCode 0
\r
1100 AutoCycTiming: Status 1000
\r
1101 AutoCycTiming: ErrStatus 0
\r
1102 AutoCycTiming: ErrCode 0
\r
1103 AutoCycTiming: Done
\r
1105 DCTInit_D: AutoCycTiming_D Done
\r
1106 SPDSetBanks: CSPresent c
\r
1107 SPDSetBanks: Status 1000
\r
1108 SPDSetBanks: ErrStatus 0
\r
1109 SPDSetBanks: ErrCode 0
\r
1112 AfterStitch pDCTstat->NodeSysBase = 0
\r
1113 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff
\r
1114 StitchMemory: Status 1000
\r
1115 StitchMemory: ErrStatus 0
\r
1116 StitchMemory: ErrCode 0
\r
1117 StitchMemory: Done
\r
1119 InterleaveBanks_D: Status 1000
\r
1120 InterleaveBanks_D: ErrStatus 0
\r
1121 InterleaveBanks_D: ErrCode 0
\r
1122 InterleaveBanks_D: Done
\r
1124 AutoConfig_D: DramControl: 2a06
\r
1125 AutoConfig_D: DramTimingLo: 90092
\r
1126 AutoConfig_D: DramConfigMisc: 0
\r
1127 AutoConfig_D: DramConfigMisc2: 0
\r
1128 AutoConfig_D: DramConfigLo: 10000
\r
1129 AutoConfig_D: DramConfigHi: f40000b
\r
1130 AutoConfig: Status 1000
\r
1131 AutoConfig: ErrStatus 0
\r
1132 AutoConfig: ErrCode 0
\r
1135 DCTInit_D: AutoConfig_D Done
\r
1136 DCTInit_D: PlatformSpec_D Done
\r
1137 DCTInit_D: StartupDCT_D
\r
1138 DCTInit_D: mct_DIMMPresence Done
\r
1139 SPDCalcWidth: Status 1000
\r
1140 SPDCalcWidth: ErrStatus 0
\r
1141 SPDCalcWidth: ErrCode 0
\r
1142 SPDCalcWidth: Done
\r
1143 DCTInit_D: mct_SPDCalcWidth Done
\r
1144 AutoCycTiming: Status 1000
\r
1145 AutoCycTiming: ErrStatus 0
\r
1146 AutoCycTiming: ErrCode 0
\r
1147 AutoCycTiming: Done
\r
1149 DCTInit_D: AutoCycTiming_D Done
\r
1150 SPDSetBanks: CSPresent c
\r
1151 SPDSetBanks: Status 1000
\r
1152 SPDSetBanks: ErrStatus 0
\r
1153 SPDSetBanks: ErrCode 0
\r
1156 AfterStitch pDCTstat->NodeSysBase = 0
\r
1157 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe
\r
1158 StitchMemory: Status 1000
\r
1159 StitchMemory: ErrStatus 0
\r
1160 StitchMemory: ErrCode 0
\r
1161 StitchMemory: Done
\r
1163 InterleaveBanks_D: Status 1000
\r
1164 InterleaveBanks_D: ErrStatus 0
\r
1165 InterleaveBanks_D: ErrCode 0
\r
1166 InterleaveBanks_D: Done
\r
1168 AutoConfig_D: DramControl: 2a06
\r
1169 AutoConfig_D: DramTimingLo: 90092
\r
1170 AutoConfig_D: DramConfigMisc: 0
\r
1171 AutoConfig_D: DramConfigMisc2: 0
\r
1172 AutoConfig_D: DramConfigLo: 10000
\r
1173 AutoConfig_D: DramConfigHi: f40000b
\r
1174 AutoConfig: Status 1000
\r
1175 AutoConfig: ErrStatus 0
\r
1176 AutoConfig: ErrCode 0
\r
1179 DCTInit_D: AutoConfig_D Done
\r
1180 DCTInit_D: PlatformSpec_D Done
\r
1181 DCTInit_D: StartupDCT_D
\r
1182 mctAutoInitMCT_D: SyncDCTsReady_D
\r
1183 mctAutoInitMCT_D: HTMemMapInit_D
\r
1184 Node: 00 base: 00 limit: 1ffffff BottomIO: e00000
\r
1185 Node: 00 base: 03 limit: 21fffff
\r
1186 Node: 01 base: 00 limit: 00
\r
1187 Node: 02 base: 00 limit: 00
\r
1188 Node: 03 base: 00 limit: 00
\r
1189 Node: 04 base: 00 limit: 00
\r
1190 Node: 05 base: 00 limit: 00
\r
1191 Node: 06 base: 00 limit: 00
\r
1192 Node: 07 base: 00 limit: 00
\r
1193 mctAutoInitMCT_D: CPUMemTyping_D
\r
1194 CPUMemTyping: Cache32bTOP:e00000
\r
1195 CPUMemTyping: Bottom32bIO:e00000
\r
1196 CPUMemTyping: Bottom40bIO:2200000
\r
1197 mctAutoInitMCT_D: DQSTiming_D
\r
1198 TrainRcvrEn: Status 1100
\r
1199 TrainRcvrEn: ErrStatus 0
\r
1200 TrainRcvrEn: ErrCode 0
\r
1203 TrainDQSRdWrPos: Status 1100
\r
1204 TrainDQSRdWrPos: TrainErrors 0
\r
1205 TrainDQSRdWrPos: ErrStatus 0
\r
1206 TrainDQSRdWrPos: ErrCode 0
\r
1207 TrainDQSRdWrPos: Done
\r
1209 TrainDQSRdWrPos: Status 1100
\r
1210 TrainDQSRdWrPos: TrainErrors 0
\r
1211 TrainDQSRdWrPos: ErrStatus 0
\r
1212 TrainDQSRdWrPos: ErrCode 0
\r
1213 TrainDQSRdWrPos: Done
\r
1215 TrainDQSRdWrPos: Status 1100
\r
1216 TrainDQSRdWrPos: TrainErrors 0
\r
1217 TrainDQSRdWrPos: ErrStatus 0
\r
1218 TrainDQSRdWrPos: ErrCode 0
\r
1219 TrainDQSRdWrPos: Done
\r
1221 TrainDQSRdWrPos: Status 1100
\r
1222 TrainDQSRdWrPos: TrainErrors 0
\r
1223 TrainDQSRdWrPos: ErrStatus 0
\r
1224 TrainDQSRdWrPos: ErrCode 0
\r
1225 TrainDQSRdWrPos: Done
\r
1227 mctAutoInitMCT_D: UMAMemTyping_D
\r
1228 mctAutoInitMCT_D: :OtherTiming
\r
1229 InterleaveNodes_D: Status 1100
\r
1230 InterleaveNodes_D: ErrStatus 0
\r
1231 InterleaveNodes_D: ErrCode 0
\r
1232 InterleaveNodes_D: Done
\r
1234 InterleaveChannels_D: Node 0
\r
1235 InterleaveChannels_D: Status 1100
\r
1236 InterleaveChannels_D: ErrStatus 0
\r
1237 InterleaveChannels_D: ErrCode 0
\r
1238 InterleaveChannels_D: Node 1
\r
1239 InterleaveChannels_D: Status 1000
\r
1240 InterleaveChannels_D: ErrStatus 0
\r
1241 InterleaveChannels_D: ErrCode 0
\r
1242 InterleaveChannels_D: Node 2
\r
1243 InterleaveChannels_D: Status 1000
\r
1244 InterleaveChannels_D: ErrStatus 0
\r
1245 InterleaveChannels_D: ErrCode 0
\r
1246 InterleaveChannels_D: Node 3
\r
1247 InterleaveChannels_D: Status 1000
\r
1248 InterleaveChannels_D: ErrStatus 0
\r
1249 InterleaveChannels_D: ErrCode 0
\r
1250 InterleaveChannels_D: Node 4
\r
1251 InterleaveChannels_D: Status 1000
\r
1252 InterleaveChannels_D: ErrStatus 0
\r
1253 InterleaveChannels_D: ErrCode 0
\r
1254 InterleaveChannels_D: Node 5
\r
1255 InterleaveChannels_D: Status 1000
\r
1256 InterleaveChannels_D: ErrStatus 0
\r
1257 InterleaveChannels_D: ErrCode 0
\r
1258 InterleaveChannels_D: Node 6
\r
1259 InterleaveChannels_D: Status 1000
\r
1260 InterleaveChannels_D: ErrStatus 0
\r
1261 InterleaveChannels_D: ErrCode 0
\r
1262 InterleaveChannels_D: Node 7
\r
1263 InterleaveChannels_D: Status 1000
\r
1264 InterleaveChannels_D: ErrStatus 0
\r
1265 InterleaveChannels_D: ErrCode 0
\r
1266 InterleaveChannels_D: Done
\r
1268 mctAutoInitMCT_D: ECCInit_D
\r
1270 raminit_amdmct end:
\r
1275 Copying data from cache to RAM -- switching to use RAM as stack... Done
\r
1277 Disabling cache as ram now
\r
1278 Clearing initial memory region: Done
\r
1280 Searching for fallback/coreboot_ram
\r
1281 Check cmos_layout.bin
\r
1282 Check fallback/romstage
\r
1283 Check fallback/coreboot_ram
\r
1284 Stage: loading fallback/coreboot_ram @ 0x200000 (1277952 bytes), entry @ 0x200000
\r
1285 Stage: done loading.
\r
1289 coreboot-4.0-2004-g9ed8bda-dirty Fri Feb 3 18:58:08 CET 2012 booting...
\r
1291 Enumerating buses...
\r
1292 Show all devs...Before device enumeration.
\r
1293 Root Device: enabled 1
\r
1294 APIC_CLUSTER: 0: enabled 1
\r
1295 APIC: 00: enabled 1
\r
1296 PCI_DOMAIN: 0000: enabled 1
\r
1297 PCI: 00:18.0: enabled 1
\r
1298 PCI: 00:00.0: enabled 1
\r
1299 PCI: 00:02.0: enabled 1
\r
1300 PCI: 00:03.0: enabled 0
\r
1301 PCI: 00:04.0: enabled 1
\r
1302 PCI: 00:05.0: enabled 0
\r
1303 PCI: 00:06.0: enabled 0
\r
1304 PCI: 00:07.0: enabled 0
\r
1305 PCI: 00:08.0: enabled 0
\r
1306 PCI: 00:09.0: enabled 1
\r
1307 PCI: 00:0a.0: enabled 1
\r
1308 PCI: 00:11.0: enabled 1
\r
1309 PCI: 00:12.0: enabled 1
\r
1310 PCI: 00:12.2: enabled 1
\r
1311 PCI: 00:13.0: enabled 1
\r
1312 PCI: 00:13.2: enabled 1
\r
1313 PCI: 00:14.0: enabled 1
\r
1314 I2C: 00:50: enabled 1
\r
1315 I2C: 00:51: enabled 1
\r
1316 I2C: 00:52: enabled 1
\r
1317 I2C: 00:53: enabled 1
\r
1318 PCI: 00:14.1: enabled 1
\r
1319 PCI: 00:14.2: enabled 1
\r
1320 PCI: 00:14.3: enabled 1
\r
1321 PNP: 002e.0: enabled 0
\r
1322 PNP: 002e.1: enabled 0
\r
1323 PNP: 002e.2: enabled 1
\r
1324 PNP: 002e.3: enabled 1
\r
1325 PNP: 002e.5: enabled 1
\r
1326 PNP: 002e.6: enabled 0
\r
1327 PNP: 002e.7: enabled 0
\r
1328 PNP: 002e.8: enabled 0
\r
1329 PNP: 002e.9: enabled 0
\r
1330 PNP: 002e.a: enabled 0
\r
1331 PNP: 002e.b: enabled 1
\r
1332 PCI: 00:14.4: enabled 0
\r
1333 PCI: 00:14.5: enabled 1
\r
1334 PCI: 00:14.6: enabled 0
\r
1335 PCI: 00:15.0: enabled 1
\r
1336 PCI: 00:15.1: enabled 1
\r
1337 PCI: 00:15.2: enabled 1
\r
1338 PCI: 00:15.3: enabled 1
\r
1339 PCI: 00:16.0: enabled 1
\r
1340 PCI: 00:16.2: enabled 1
\r
1341 PCI: 00:18.1: enabled 1
\r
1342 PCI: 00:18.2: enabled 1
\r
1343 PCI: 00:18.3: enabled 1
\r
1344 PCI: 00:18.4: enabled 1
\r
1345 Compare with tree...
\r
1346 Root Device: enabled 1
\r
1347 APIC_CLUSTER: 0: enabled 1
\r
1348 APIC: 00: enabled 1
\r
1349 PCI_DOMAIN: 0000: enabled 1
\r
1350 PCI: 00:18.0: enabled 1
\r
1351 PCI: 00:00.0: enabled 1
\r
1352 PCI: 00:02.0: enabled 1
\r
1353 PCI: 00:03.0: enabled 0
\r
1354 PCI: 00:04.0: enabled 1
\r
1355 PCI: 00:05.0: enabled 0
\r
1356 PCI: 00:06.0: enabled 0
\r
1357 PCI: 00:07.0: enabled 0
\r
1358 PCI: 00:08.0: enabled 0
\r
1359 PCI: 00:09.0: enabled 1
\r
1360 PCI: 00:0a.0: enabled 1
\r
1361 PCI: 00:11.0: enabled 1
\r
1362 PCI: 00:12.0: enabled 1
\r
1363 PCI: 00:12.2: enabled 1
\r
1364 PCI: 00:13.0: enabled 1
\r
1365 PCI: 00:13.2: enabled 1
\r
1366 PCI: 00:14.0: enabled 1
\r
1367 I2C: 00:50: enabled 1
\r
1368 I2C: 00:51: enabled 1
\r
1369 I2C: 00:52: enabled 1
\r
1370 I2C: 00:53: enabled 1
\r
1371 PCI: 00:14.1: enabled 1
\r
1372 PCI: 00:14.2: enabled 1
\r
1373 PCI: 00:14.3: enabled 1
\r
1374 PNP: 002e.0: enabled 0
\r
1375 PNP: 002e.1: enabled 0
\r
1376 PNP: 002e.2: enabled 1
\r
1377 PNP: 002e.3: enabled 1
\r
1378 PNP: 002e.5: enabled 1
\r
1379 PNP: 002e.6: enabled 0
\r
1380 PNP: 002e.7: enabled 0
\r
1381 PNP: 002e.8: enabled 0
\r
1382 PNP: 002e.9: enabled 0
\r
1383 PNP: 002e.a: enabled 0
\r
1384 PNP: 002e.b: enabled 1
\r
1385 PCI: 00:14.4: enabled 0
\r
1386 PCI: 00:14.5: enabled 1
\r
1387 PCI: 00:14.6: enabled 0
\r
1388 PCI: 00:15.0: enabled 1
\r
1389 PCI: 00:15.1: enabled 1
\r
1390 PCI: 00:15.2: enabled 1
\r
1391 PCI: 00:15.3: enabled 1
\r
1392 PCI: 00:16.0: enabled 1
\r
1393 PCI: 00:16.2: enabled 1
\r
1394 PCI: 00:18.1: enabled 1
\r
1395 PCI: 00:18.2: enabled 1
\r
1396 PCI: 00:18.3: enabled 1
\r
1397 PCI: 00:18.4: enabled 1
\r
1398 Mainboard ASUS M5A99X-EVO Enable. dev=0x00233b5c
\r
1399 m5a99x_evo_enable, w00t?!
\r
1400 m5a99x_evo_enable, cya enable?!
\r
1401 Enumerating buses... starting with root now
\r
1402 scan_static_bus for Root Device
\r
1403 APIC_CLUSTER: 0 enabled
\r
1404 PCI_DOMAIN: 0000 enabled
\r
1405 APIC_CLUSTER: 0 scanning...
\r
1406 cpu_bus_scan: starting...
\r
1407 PCI: 00:18.3 siblings=5
\r
1408 CPU: APIC: 00 enabled
\r
1409 CPU: APIC: 01 enabled
\r
1410 CPU: APIC: 02 enabled
\r
1411 CPU: APIC: 03 enabled
\r
1412 CPU: APIC: 04 enabled
\r
1413 CPU: APIC: 05 enabled
\r
1414 cpu_bus_scan: done.
\r
1415 PCI_DOMAIN: 0000 scanning...
\r
1416 PCI: pci_scan_bus for bus 00
\r
1418 pci_scan_bus: before pci_scan_get_dev! devfn: 192
\r
1419 pci_scan_bus: after pci_scan_get_dev!
\r
1420 pci_scan_bus: before pci_probe_dev!
\r
1421 PCI: 00:18.0 [1022/1200] bus ops
\r
1422 PCI: 00:18.0 [1022/1200] enabled
\r
1423 pci_scan_bus: after pci_probe_dev!
\r
1424 pci_scan_bus: before pci_scan_get_dev! devfn: 193
\r
1425 pci_scan_bus: after pci_scan_get_dev!
\r
1426 pci_scan_bus: before pci_probe_dev!
\r
1427 PCI: 00:18.1 [1022/1201] enabled
\r
1428 pci_scan_bus: after pci_probe_dev!
\r
1429 pci_scan_bus: before pci_scan_get_dev! devfn: 194
\r
1430 pci_scan_bus: after pci_scan_get_dev!
\r
1431 pci_scan_bus: before pci_probe_dev!
\r
1432 PCI: 00:18.2 [1022/1202] enabled
\r
1433 pci_scan_bus: after pci_probe_dev!
\r
1434 pci_scan_bus: before pci_scan_get_dev! devfn: 195
\r
1435 pci_scan_bus: after pci_scan_get_dev!
\r
1436 pci_scan_bus: before pci_probe_dev!
\r
1437 PCI: 00:18.3 [1022/1203] ops
\r
1438 PCI: 00:18.3 [1022/1203] enabled
\r
1439 pci_scan_bus: after pci_probe_dev!
\r
1440 pci_scan_bus: before pci_scan_get_dev! devfn: 196
\r
1441 pci_scan_bus: after pci_scan_get_dev!
\r
1442 pci_scan_bus: before pci_probe_dev!
\r
1443 PCI: 00:18.4 [1022/1204] enabled
\r
1444 pci_scan_bus: after pci_probe_dev!
\r
1445 pci_scan_bus: before pci_scan_get_dev! devfn: 197
\r
1446 pci_scan_bus: after pci_scan_get_dev!
\r
1447 pci_scan_bus: before pci_probe_dev!
\r
1448 pci_scan_bus: after pci_probe_dev!
\r
1449 pci_scan_bus: before pci_scan_get_dev! devfn: 198
\r
1450 pci_scan_bus: after pci_scan_get_dev!
\r
1451 pci_scan_bus: before pci_probe_dev!
\r
1452 pci_scan_bus: after pci_probe_dev!
\r
1453 pci_scan_bus: before pci_scan_get_dev! devfn: 199
\r
1454 pci_scan_bus: after pci_scan_get_dev!
\r
1455 pci_scan_bus: before pci_probe_dev!
\r
1456 pci_scan_bus: after pci_probe_dev!
\r
1457 pci_scan_bus: before pci_scan_get_dev! devfn: 200
\r
1458 pci_scan_bus: after pci_scan_get_dev!
\r
1459 pci_scan_bus: before pci_probe_dev!
\r
1460 pci_scan_bus: after pci_probe_dev!
\r
1461 pci_scan_bus: before pci_scan_get_dev! devfn: 208
\r
1462 pci_scan_bus: after pci_scan_get_dev!
\r
1463 pci_scan_bus: before pci_probe_dev!
\r
1464 pci_scan_bus: after pci_probe_dev!
\r
1465 pci_scan_bus: before pci_scan_get_dev! devfn: 216
\r
1466 pci_scan_bus: after pci_scan_get_dev!
\r
1467 pci_scan_bus: before pci_probe_dev!
\r
1468 pci_scan_bus: after pci_probe_dev!
\r
1469 pci_scan_bus: before pci_scan_get_dev! devfn: 224
\r
1470 pci_scan_bus: after pci_scan_get_dev!
\r
1471 pci_scan_bus: before pci_probe_dev!
\r
1472 pci_scan_bus: after pci_probe_dev!
\r
1473 pci_scan_bus: before pci_scan_get_dev! devfn: 232
\r
1474 pci_scan_bus: after pci_scan_get_dev!
\r
1475 pci_scan_bus: before pci_probe_dev!
\r
1476 pci_scan_bus: after pci_probe_dev!
\r
1477 pci_scan_bus: before pci_scan_get_dev! devfn: 240
\r
1478 pci_scan_bus: after pci_scan_get_dev!
\r
1479 pci_scan_bus: before pci_probe_dev!
\r
1480 pci_scan_bus: after pci_probe_dev!
\r
1481 pci_scan_bus: before pci_scan_get_dev! devfn: 248
\r
1482 pci_scan_bus: after pci_scan_get_dev!
\r
1483 pci_scan_bus: before pci_probe_dev!
\r
1484 pci_scan_bus: after pci_probe_dev!
\r
1486 amdfam10_scan_chains: starting...
\r
1487 amdfam10_scan_chains: link: 00233ed0
\r
1488 amdfam10_scan_chain: starting...
\r
1489 amdfam10_scan_chain: link_type: 0x00000007
\r
1490 amdfam10_scan_chain: link_type: 0x00000007
\r
1491 amdfam10_scan_chain: before get_ht_c_index
\r
1492 amdfam10_scan_chain: after get_ht_c_index
\r
1493 amdfam10_scan_chain: before set_config_map_reg
\r
1494 amdfam10_scan_chain: after set_config_map_reg
\r
1495 amdfam10_scan_chain: before hypertransport_scan_chain
\r
1496 hypertransport_scan_chain: before ht_collapse_early_enumeration
\r
1497 hypertransport_scan_chain: after ht_collapse_early_enumeration
\r
1498 hypertransport_scan_chain: before ht_scan_get_devs
\r
1499 hypertransport_scan_chain: after ht_scan_get_devs
\r
1500 hypertransport_scan_chain: before pci_probe_dev
\r
1501 PCI: Using configuration type 1
\r
1502 rs780_enable: dev=00234128, VID_DID=0x5a141002
\r
1503 Bus-0, Dev-0, Fun-0.
\r
1504 enable_pcie_bar3()
\r
1505 addr=e0000000,bus=0,devfn=40
\r
1506 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
\r
1508 NB_PCI_REG84 = 3000095.
\r
1509 NB_PCI_REG4C = 52042.
\r
1510 rs780_enable: done
\r
1511 PCI: 00:00.0 [1002/5a14] enabled
\r
1512 hypertransport_scan_chain: after pci_probe_dev
\r
1513 hypertransport_scan_chain: before ht_lookup_slave_capability
\r
1514 Capability: type 0x08 @ 0xf0
\r
1516 Capability: type 0x08 @ 0xf0
\r
1517 Capability: type 0x08 @ 0xc4
\r
1519 hypertransport_scan_chain: after ht_lookup_slave_capability
\r
1520 hypertransport_scan_chain: end_of_chain. w00t!
\r
1521 hypertransport_scan_chain: before pci_scan_bus!
\r
1522 PCI: pci_scan_bus for bus 00
\r
1523 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff
\r
1524 PCI: pci_scan_bus upper limit too big. Using 0xff.
\r
1526 pci_scan_bus: before pci_scan_get_dev! devfn: 0
\r
1527 pci_scan_bus: after pci_scan_get_dev!
\r
1528 pci_scan_bus: before pci_probe_dev!
\r
1529 rs780_enable: dev=00234128, VID_DID=0x5a141002
\r
1530 Bus-0, Dev-0, Fun-0.
\r
1531 enable_pcie_bar3()
\r
1532 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
\r
1534 NB_PCI_REG84 = 3000095.
\r
1535 NB_PCI_REG4C = 52042.
\r
1536 rs780_enable: done
\r
1537 PCI: 00:00.0 [1002/5a14] enabled
\r
1538 pci_scan_bus: after pci_probe_dev!
\r
1539 pci_scan_bus: before pci_scan_get_dev! devfn: 1
\r
1540 pci_scan_bus: after pci_scan_get_dev!
\r
1541 pci_scan_bus: before pci_probe_dev!
\r
1542 pci_scan_bus: after pci_probe_dev!
\r
1543 pci_scan_bus: before pci_scan_get_dev! devfn: 2
\r
1544 pci_scan_bus: after pci_scan_get_dev!
\r
1545 pci_scan_bus: before pci_probe_dev!
\r
1546 pci_scan_bus: after pci_probe_dev!
\r
1547 pci_scan_bus: before pci_scan_get_dev! devfn: 3
\r
1548 pci_scan_bus: after pci_scan_get_dev!
\r
1549 pci_scan_bus: before pci_probe_dev!
\r
1550 pci_scan_bus: after pci_probe_dev!
\r
1551 pci_scan_bus: before pci_scan_get_dev! devfn: 4
\r
1552 pci_scan_bus: after pci_scan_get_dev!
\r
1553 pci_scan_bus: before pci_probe_dev!
\r
1554 pci_scan_bus: after pci_probe_dev!
\r
1555 pci_scan_bus: before pci_scan_get_dev! devfn: 5
\r
1556 pci_scan_bus: after pci_scan_get_dev!
\r
1557 pci_scan_bus: before pci_probe_dev!
\r
1558 pci_scan_bus: after pci_probe_dev!
\r
1559 pci_scan_bus: before pci_scan_get_dev! devfn: 6
\r
1560 pci_scan_bus: after pci_scan_get_dev!
\r
1561 pci_scan_bus: before pci_probe_dev!
\r
1562 pci_scan_bus: after pci_probe_dev!
\r
1563 pci_scan_bus: before pci_scan_get_dev! devfn: 7
\r
1564 pci_scan_bus: after pci_scan_get_dev!
\r
1565 pci_scan_bus: before pci_probe_dev!
\r
1566 pci_scan_bus: after pci_probe_dev!
\r
1567 pci_scan_bus: before pci_scan_get_dev! devfn: 8
\r
1568 pci_scan_bus: after pci_scan_get_dev!
\r
1569 pci_scan_bus: before pci_probe_dev!
\r
1570 pci_scan_bus: after pci_probe_dev!
\r
1572 PCI: Left over static devices:
\r
1600 PCI: Check your devicetree.cb.
\r
1601 PCI: pci_scan_bus returning with max=000
\r
1603 hypertransport_scan_chain: after pci_scan_bus!
\r
1604 amdfam10_scan_chain: after hypertransport_scan_chain
\r
1605 amdfam10_scan_chain: before set_config_map_reg
\r
1606 amdfam10_scan_chain: after set_config_map_reg
\r
1607 amdfam10_scan_chain: before store_ht_c_conf_bus
\r
1608 amdfam10_scan_chain: after store_ht_c_conf_bus
\r
1609 amdfam10_scan_chain: done.
\r
1610 amdfam10_scan_chains: link: 00278000
\r
1611 amdfam10_scan_chains: link: 00278018
\r
1612 amdfam10_scan_chains: link: 00278030
\r
1613 amdfam10_scan_chains: link: 00278048
\r
1614 amdfam10_scan_chains: link: 00278060
\r
1615 amdfam10_scan_chains: link: 00278078
\r
1616 amdfam10_scan_chains: link: 00278090
\r
1617 amdfam10_scan_chains: link2: 00233ed0
\r
1618 amdfam10_scan_chains: link2: 00278000
\r
1619 amdfam10_scan_chain: starting...
\r
1620 amdfam10_scan_chain: link_type: 0x00000000
\r
1621 amdfam10_scan_chains: link2: 00278018
\r
1622 amdfam10_scan_chain: starting...
\r
1623 amdfam10_scan_chain: link_type: 0x00000000
\r
1624 amdfam10_scan_chains: link2: 00278030
\r
1625 amdfam10_scan_chain: starting...
\r
1626 amdfam10_scan_chain: link_type: 0x00000000
\r
1627 amdfam10_scan_chains: link2: 00278048
\r
1628 amdfam10_scan_chain: starting...
\r
1629 amdfam10_scan_chains: link2: 00278060
\r
1630 amdfam10_scan_chain: starting...
\r
1631 amdfam10_scan_chain: link_type: 0x00000000
\r
1632 amdfam10_scan_chains: link2: 00278078
\r
1633 amdfam10_scan_chain: starting...
\r
1634 amdfam10_scan_chain: link_type: 0x00000000
\r
1635 amdfam10_scan_chains: link2: 00278090
\r
1636 amdfam10_scan_chain: starting...
\r
1637 amdfam10_scan_chain: link_type: 0x00000000
\r
1638 amdfam10_scan_chains: done.
\r
1639 PCI: pci_scan_bus returning with max=000
\r
1641 PCI_DOMAIN: 0000 passpw: enabled
\r
1642 scan_static_bus for Root Device done
\r
1645 ===============Enumeration done!========
\r
1646 Allocating resources...
\r
1647 Reading resources...
\r
1648 Root Device read_resources bus 0 link: 0
\r
1649 APIC_CLUSTER: 0 read_resources bus 0 link: 0
\r
1650 APIC: 00 missing read_resources
\r
1651 APIC: 01 missing read_resources
\r
1652 APIC: 02 missing read_resources
\r
1653 APIC: 03 missing read_resources
\r
1654 APIC: 04 missing read_resources
\r
1655 APIC: 05 missing read_resources
\r
1656 APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
\r
1657 PCI_DOMAIN: 0000 read_resources bus 0 link: 0
\r
1658 PCI: 00:18.0 read_resources bus 0 link: 0
\r
1659 PCI: 00:18.0 read_resources bus 0 link: 0 done
\r
1660 PCI: 00:18.0 read_resources bus 0 link: 1
\r
1661 PCI: 00:18.0 read_resources bus 0 link: 1 done
\r
1662 PCI: 00:18.0 read_resources bus 0 link: 2
\r
1663 PCI: 00:18.0 read_resources bus 0 link: 2 done
\r
1664 PCI: 00:18.0 read_resources bus 0 link: 3
\r
1665 PCI: 00:18.0 read_resources bus 0 link: 3 done
\r
1666 PCI: 00:18.0 read_resources bus 0 link: 4
\r
1667 PCI: 00:18.0 read_resources bus 0 link: 4 done
\r
1668 PCI: 00:18.0 read_resources bus 0 link: 5
\r
1669 PCI: 00:18.0 read_resources bus 0 link: 5 done
\r
1670 PCI: 00:18.0 read_resources bus 0 link: 6
\r
1671 PCI: 00:18.0 read_resources bus 0 link: 6 done
\r
1672 PCI: 00:18.0 read_resources bus 0 link: 7
\r
1673 PCI: 00:18.0 read_resources bus 0 link: 7 done
\r
1674 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
\r
1675 Root Device read_resources bus 0 link: 0 done
\r
1676 Done reading resources.
\r
1677 Show resources in subtree (Root Device)...After reading.
\r
1678 Root Device child on link 0 APIC_CLUSTER: 0
\r
1679 APIC_CLUSTER: 0 child on link 0 APIC: 00
\r
1686 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
\r
1687 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
\r
1688 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
\r
1689 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
\r
1690 PCI: 00:18.0 child on link 0 PCI: 00:00.0
\r
1691 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b0
\r
1692 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b8
\r
1693 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8
\r
1695 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 201 index 1c
\r
1699 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
\r
1701 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
\r
1702 PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
\r
1703 PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
\r
1704 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
\r
1705 PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
\r
1706 PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
\r
1707 PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done
\r
1708 PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
\r
1709 PCI: 00:00.0 1c * [0x0 - 0xfffffff] mem
\r
1710 PCI: 00:18.0 compute_resources_mem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffffff done
\r
1711 PCI: 00:18.0 10b8 * [0x0 - 0xfffffff] mem
\r
1712 PCI: 00:18.3 94 * [0x10000000 - 0x13ffffff] mem
\r
1713 PCI_DOMAIN: 0000 compute_resources_mem: base: 14000000 size: 14000000 align: 28 gran: 0 limit: ffffffff done
\r
1714 avoid_fixed_resources: PCI_DOMAIN: 0000
\r
1715 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
\r
1716 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
\r
1717 constrain_resources: PCI_DOMAIN: 0000
\r
1718 constrain_resources: PCI: 00:18.0
\r
1719 constrain_resources: PCI: 00:00.0
\r
1720 constrain_resources: PCI: 00:18.1
\r
1721 constrain_resources: PCI: 00:18.2
\r
1722 constrain_resources: PCI: 00:18.3
\r
1723 constrain_resources: PCI: 00:18.4
\r
1724 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
\r
1725 lim->base 00000000 lim->limit 0000ffff
\r
1726 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
\r
1727 lim->base 00000000 lim->limit dfffffff
\r
1728 Setting resources...
\r
1729 PCI_DOMAIN: 0000 allocate_resources_io: base:0 size:0 align:0 gran:0 limit:ffff
\r
1730 PCI_DOMAIN: 0000 allocate_resources_io: next_base: 0 size: 0 align: 0 gran: 0 done
\r
1731 PCI: 00:18.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
\r
1732 PCI: 00:18.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
\r
1733 PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:14000000 align:28 gran:0 limit:dfffffff
\r
1734 Assigned: PCI: 00:18.0 10b8 * [0xc0000000 - 0xcfffffff] mem
\r
1735 Assigned: PCI: 00:18.3 94 * [0xd0000000 - 0xd3ffffff] mem
\r
1736 PCI_DOMAIN: 0000 allocate_resources_mem: next_base: d4000000 size: 14000000 align: 28 gran: 0 done
\r
1737 PCI: 00:18.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
\r
1738 PCI: 00:18.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
\r
1739 PCI: 00:18.0 allocate_resources_mem: base:c0000000 size:10000000 align:28 gran:20 limit:dfffffff
\r
1740 Assigned: PCI: 00:00.0 1c * [0xc0000000 - 0xcfffffff] mem
\r
1741 PCI: 00:18.0 allocate_resources_mem: next_base: d0000000 size: 10000000 align: 28 gran: 20 done
\r
1742 Root Device assign_resources, bus 0 link: 0
\r
1743 split: 64K table at =bfff0000
\r
1744 0: mmio_basek=00300000, basek=00400000, limitk=00880000
\r
1745 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
\r
1746 PCI: 00:18.0 10b0 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 prefmem <node 0 link 0>
\r
1747 PCI: 00:18.0 10b8 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x14 mem <node 0 link 0>
\r
1748 PCI: 00:18.0 10d8 <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c io <node 0 link 0>
\r
1749 PCI: 00:18.0 assign_resources, bus 0 link: 0
\r
1750 PCI: 00:00.0 1c <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c mem64
\r
1751 PCI: 00:18.0 assign_resources, bus 0 link: 0
\r
1752 PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem <gart>
\r
1753 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
\r
1754 Root Device assign_resources, bus 0 link: 0
\r
1755 Done setting resources.
\r
1756 Show resources in subtree (Root Device)...After assigning values.
\r
1757 Root Device child on link 0 APIC_CLUSTER: 0
\r
1758 APIC_CLUSTER: 0 child on link 0 APIC: 00
\r
1765 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
\r
1766 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
\r
1767 PCI_DOMAIN: 0000 resource base c0000000 size 14000000 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
\r
1768 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
\r
1769 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
\r
1770 PCI_DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20
\r
1771 PCI_DOMAIN: 0000 resource base 100000000 size 120000000 align 0 gran 0 limit 0 flags e0004200 index 30
\r
1772 PCI: 00:18.0 child on link 0 PCI: 00:00.0
\r
1773 PCI: 00:18.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081200 index 10b0
\r
1774 PCI: 00:18.0 resource base c0000000 size 10000000 align 28 gran 20 limit dfffffff flags 60080200 index 10b8
\r
1775 PCI: 00:18.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080100 index 10d8
\r
1777 PCI: 00:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60000201 index 1c
\r
1781 PCI: 00:18.3 resource base d0000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94
\r
1783 Done allocating resources.
\r
1785 Enabling resources...
\r
1786 PCI: 00:18.0 cmd <- 00
\r
1787 PCI: 00:18.1 subsystem <- 1043/843e
\r
1788 PCI: 00:18.1 cmd <- 00
\r
1789 PCI: 00:18.2 subsystem <- 1043/843e
\r
1790 PCI: 00:18.2 cmd <- 00
\r
1791 PCI: 00:18.3 cmd <- 00
\r
1792 PCI: 00:18.4 subsystem <- 1043/843e
\r
1793 PCI: 00:18.4 cmd <- 00
\r
1794 PCI: 00:00.0 subsystem <- 1043/843e
\r
1795 PCI: 00:00.0 cmd <- 02
\r
1797 Initializing devices...
\r
1799 APIC_CLUSTER: 0 init
\r
1800 start_eip=0x0000a000, offset=0x00200000, code_size=0x0000005b
\r
1801 Initializing CPU #0
\r
1802 CPU: vendor AMD device 100fa0
\r
1803 CPU: family 10, model 0a, stepping 00
\r
1804 nodeid = 00, coreid = 00
\r
1808 Setting fixed MTRRs(0-88) type: UC
\r
1809 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
\r
1810 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
\r
1812 Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB
\r
1813 ADDRESS_MASK_HIGH=0xffff
\r
1814 Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB
\r
1815 ADDRESS_MASK_HIGH=0xffff
\r
1816 Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC
\r
1817 ADDRESS_MASK_HIGH=0xffff
\r
1818 DONE variable MTRRs
\r
1819 Clear out the extra MTRR's
\r
1820 call enable_var_mtrr()
\r
1821 Leave x86_setup_var_mtrrs
\r
1825 Fixed MTRRs : Enabled
\r
1826 Variable MTRRs: Enabled
\r
1829 Setting up local apic... apic_id: 0x00 done.
\r
1831 CPU model: AMD Processor model unknown
\r
1832 siblings = 05, CPU #0 initialized
\r
1834 Waiting for send to finish...
\r
1835 +Deasserting INIT.
\r
1836 Waiting for send to finish...
\r
1837 +#startup loops: 1.
\r
1838 Sending STARTUP #1 to 1.
\r
1841 Waiting for send to finish...
\r
1843 Initializing CPU #1
\r
1844 CPU: vendor AMD device 100fa0
\r
1845 CPU: family 10, model 0a, stepping 00
\r
1846 nodeid = 00, coreid = 01
\r
1850 Setting fixed MTRRs(0-88) type: UC
\r
1851 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
\r
1852 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
\r
1854 Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB
\r
1855 ADDRESS_MASK_HIGH=0xffff
\r
1856 Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB
\r
1857 ADDRESS_MASK_HIGH=0xffff
\r
1858 Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC
\r
1859 ADDRESS_MASK_HIGH=0xffff
\r
1860 DONE variable MTRRs
\r
1861 Clear out the extra MTRR's
\r
1862 call enable_var_mtrr()
\r
1863 Leave x86_setup_var_mtrrs
\r
1867 Fixed MTRRs : Enabled
\r
1868 Variable MTRRs: Enabled
\r
1871 Setting up local apic... apic_id: 0x01 done.
\r
1873 CPU model: AMD Processor model unknown
\r
1874 siblings = 05, CPU #1 initialized
\r
1876 Waiting for send to finish...
\r
1877 +Deasserting INIT.
\r
1878 Waiting for send to finish...
\r
1879 +#startup loops: 1.
\r
1880 Sending STARTUP #1 to 2.
\r
1883 Waiting for send to finish...
\r
1885 Initializing CPU #2
\r
1886 CPU: vendor AMD device 100fa0
\r
1887 CPU: family 10, model 0a, stepping 00
\r
1888 nodeid = 00, coreid = 02
\r
1892 Setting fixed MTRRs(0-88) type: UC
\r
1893 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
\r
1894 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
\r
1896 Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB
\r
1897 ADDRESS_MASK_HIGH=0xffff
\r
1898 Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB
\r
1899 ADDRESS_MASK_HIGH=0xffff
\r
1900 Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC
\r
1901 ADDRESS_MASK_HIGH=0xffff
\r
1902 DONE variable MTRRs
\r
1903 Clear out the extra MTRR's
\r
1904 call enable_var_mtrr()
\r
1905 Leave x86_setup_var_mtrrs
\r
1909 Fixed MTRRs : Enabled
\r
1910 Variable MTRRs: Enabled
\r
1913 Setting up local apic... apic_id: 0x02 done.
\r
1915 CPU model: AMD Processor model unknown
\r
1916 siblings = 05, CPU #2 initialized
\r
1918 Waiting for send to finish...
\r
1919 +Deasserting INIT.
\r
1920 Waiting for send to finish...
\r
1921 +#startup loops: 1.
\r
1922 Sending STARTUP #1 to 3.
\r
1925 Waiting for send to finish...
\r
1927 Initializing CPU #3
\r
1928 CPU: vendor AMD device 100fa0
\r
1929 CPU: family 10, model 0a, stepping 00
\r
1930 nodeid = 00, coreid = 03
\r
1934 Setting fixed MTRRs(0-88) type: UC
\r
1935 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
\r
1936 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
\r
1938 Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB
\r
1939 ADDRESS_MASK_HIGH=0xffff
\r
1940 Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB
\r
1941 ADDRESS_MASK_HIGH=0xffff
\r
1942 Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC
\r
1943 ADDRESS_MASK_HIGH=0xffff
\r
1944 DONE variable MTRRs
\r
1945 Clear out the extra MTRR's
\r
1946 call enable_var_mtrr()
\r
1947 Leave x86_setup_var_mtrrs
\r
1951 Fixed MTRRs : Enabled
\r
1952 Variable MTRRs: Enabled
\r
1955 Setting up local apic... apic_id: 0x03 done.
\r
1957 CPU model: AMD Processor model unknown
\r
1958 siblings = 05, CPU #3 initialized
\r
1960 Waiting for send to finish...
\r
1961 +Deasserting INIT.
\r
1962 Waiting for send to finish...
\r
1963 +#startup loops: 1.
\r
1964 Sending STARTUP #1 to 4.
\r
1967 Waiting for send to finish...
\r
1969 Initializing CPU #4
\r
1970 CPU: vendor AMD device 100fa0
\r
1971 CPU: family 10, model 0a, stepping 00
\r
1972 nodeid = 00, coreid = 04
\r
1976 Setting fixed MTRRs(0-88) type: UC
\r
1977 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
\r
1978 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
\r
1980 Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB
\r
1981 ADDRESS_MASK_HIGH=0xffff
\r
1982 Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB
\r
1983 ADDRESS_MASK_HIGH=0xffff
\r
1984 Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC
\r
1985 ADDRESS_MASK_HIGH=0xffff
\r
1986 DONE variable MTRRs
\r
1987 Clear out the extra MTRR's
\r
1988 call enable_var_mtrr()
\r
1989 Leave x86_setup_var_mtrrs
\r
1993 Fixed MTRRs : Enabled
\r
1994 Variable MTRRs: Enabled
\r
1997 Setting up local apic... apic_id: 0x04 done.
\r
1999 CPU model: AMD Processor model unknown
\r
2000 siblings = 05, CPU #4 initialized
\r
2002 Waiting for send to finish...
\r
2003 +Deasserting INIT.
\r
2004 Waiting for send to finish...
\r
2005 +#startup loops: 1.
\r
2006 Sending STARTUP #1 to 5.
\r
2009 Waiting for send to finish...
\r
2011 Initializing CPU #5
\r
2012 Waiting for 1 CPUS to stop
\r
2013 CPU: vendor AMD device 100fa0
\r
2014 CPU: family 10, model 0a, stepping 00
\r
2015 nodeid = 00, coreid = 05
\r
2019 Setting fixed MTRRs(0-88) type: UC
\r
2020 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
\r
2021 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
\r
2023 Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB
\r
2024 ADDRESS_MASK_HIGH=0xffff
\r
2025 Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB
\r
2026 ADDRESS_MASK_HIGH=0xffff
\r
2027 Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC
\r
2028 ADDRESS_MASK_HIGH=0xffff
\r
2029 DONE variable MTRRs
\r
2030 Clear out the extra MTRR's
\r
2031 call enable_var_mtrr()
\r
2032 Leave x86_setup_var_mtrrs
\r
2036 Fixed MTRRs : Enabled
\r
2037 Variable MTRRs: Enabled
\r
2040 Setting up local apic... apic_id: 0x05 done.
\r
2042 CPU model: AMD Processor model unknown
\r
2043 siblings = 05, CPU #5 initialized
\r
2044 All AP CPUs stopped
\r
2045 SB900 - Early.c - sb_After_Pci_Init - Start.
\r
2046 SB900 - Cfg.c - sb900_cimx_config - Start.
\r
2047 SB900 - Cfg.c - sb900_cimx_config - End.
\r
2048 SB900 - Early.c - sb_After_Pci_Init - End.
\r
2049 SB900 - Early.c - sb_Mid_Post_Init - Start.
\r
2050 SB900 - Cfg.c - sb900_cimx_config - Start.
\r
2051 SB900 - Cfg.c - sb900_cimx_config - End.
\r
2052 SB900 - Early.c - sb_Mid_Post_Init - End.
\r
2055 Searching for pci1022,1201.rom
\r
2056 Check cmos_layout.bin
\r
2057 Check fallback/romstage
\r
2058 Check fallback/coreboot_ram
\r
2059 Check fallback/payload
\r
2062 Could not find file 'pci1022,1201.rom'.
\r
2064 Searching for pci1022,1202.rom
\r
2065 Check cmos_layout.bin
\r
2066 Check fallback/romstage
\r
2067 Check fallback/coreboot_ram
\r
2068 Check fallback/payload
\r
2071 Could not find file 'pci1022,1202.rom'.
\r
2073 NB: Function 3 Misc Control.. done.
\r
2075 Searching for pci1022,1204.rom
\r
2076 Check cmos_layout.bin
\r
2077 Check fallback/romstage
\r
2078 Check fallback/coreboot_ram
\r
2079 Check fallback/payload
\r
2082 Could not find file 'pci1022,1204.rom'.
\r
2084 Searching for pci1002,5a14.rom
\r
2085 Check cmos_layout.bin
\r
2086 Check fallback/romstage
\r
2087 Check fallback/coreboot_ram
\r
2088 Check fallback/payload
\r
2091 Could not find file 'pci1002,5a14.rom'.
\r
2092 Devices initialized
\r
2093 Show all devs...After init.
\r
2094 Root Device: enabled 1
\r
2095 APIC_CLUSTER: 0: enabled 1
\r
2096 APIC: 00: enabled 1
\r
2097 PCI_DOMAIN: 0000: enabled 1
\r
2098 PCI: 00:18.0: enabled 1
\r
2099 PCI: 00:00.0: enabled 1
\r
2100 PCI: 00:02.0: enabled 1
\r
2101 PCI: 00:03.0: enabled 0
\r
2102 PCI: 00:04.0: enabled 1
\r
2103 PCI: 00:05.0: enabled 0
\r
2104 PCI: 00:06.0: enabled 0
\r
2105 PCI: 00:07.0: enabled 0
\r
2106 PCI: 00:08.0: enabled 0
\r
2107 PCI: 00:09.0: enabled 1
\r
2108 PCI: 00:0a.0: enabled 1
\r
2109 PCI: 00:11.0: enabled 1
\r
2110 PCI: 00:12.0: enabled 1
\r
2111 PCI: 00:12.2: enabled 1
\r
2112 PCI: 00:13.0: enabled 1
\r
2113 PCI: 00:13.2: enabled 1
\r
2114 PCI: 00:14.0: enabled 1
\r
2115 I2C: 00:50: enabled 1
\r
2116 I2C: 00:51: enabled 1
\r
2117 I2C: 00:52: enabled 1
\r
2118 I2C: 00:53: enabled 1
\r
2119 PCI: 00:14.1: enabled 1
\r
2120 PCI: 00:14.2: enabled 1
\r
2121 PCI: 00:14.3: enabled 1
\r
2122 PNP: 002e.0: enabled 0
\r
2123 PNP: 002e.1: enabled 0
\r
2124 PNP: 002e.2: enabled 1
\r
2125 PNP: 002e.3: enabled 1
\r
2126 PNP: 002e.5: enabled 1
\r
2127 PNP: 002e.6: enabled 0
\r
2128 PNP: 002e.7: enabled 0
\r
2129 PNP: 002e.8: enabled 0
\r
2130 PNP: 002e.9: enabled 0
\r
2131 PNP: 002e.a: enabled 0
\r
2132 PNP: 002e.b: enabled 1
\r
2133 PCI: 00:14.4: enabled 0
\r
2134 PCI: 00:14.5: enabled 1
\r
2135 PCI: 00:14.6: enabled 0
\r
2136 PCI: 00:15.0: enabled 1
\r
2137 PCI: 00:15.1: enabled 1
\r
2138 PCI: 00:15.2: enabled 1
\r
2139 PCI: 00:15.3: enabled 1
\r
2140 PCI: 00:16.0: enabled 1
\r
2141 PCI: 00:16.2: enabled 1
\r
2142 PCI: 00:18.1: enabled 1
\r
2143 PCI: 00:18.2: enabled 1
\r
2144 PCI: 00:18.3: enabled 1
\r
2145 PCI: 00:18.4: enabled 1
\r
2146 APIC: 01: enabled 1
\r
2147 APIC: 02: enabled 1
\r
2148 APIC: 03: enabled 1
\r
2149 APIC: 04: enabled 1
\r
2150 APIC: 05: enabled 1
\r
2152 Initializing CBMEM area to 0xbfff0000 (65536 bytes)
\r
2153 Adding CBMEM entry as no. 1
\r
2154 Moving GDT to bfff0200...ok
\r
2155 High Tables Base is bfff0000.
\r
2157 SB900 - Early.c - sb_Late_Post - Start.
\r
2158 SB900 - Cfg.c - sb900_cimx_config - Start.
\r
2159 SB900 - Cfg.c - sb900_cimx_config - End.
\r
2160 SB900 - Early.c - sb_Late_Post - End.
\r
2161 Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
\r
2162 Adding CBMEM entry as no. 2
\r
2163 Writing IRQ routing tables to 0xbfff0400...write_pirq_routing_table done.
\r
2164 PIRQ table: 48 bytes.
\r
2166 Wrote the mp table end at: 000f0410 - 000f0554
\r
2167 Adding CBMEM entry as no. 3
\r
2168 Wrote the mp table end at: bfff1410 - bfff1554
\r
2169 MP table: 340 bytes.
\r
2171 Adding CBMEM entry as no. 4
\r
2172 ACPI: Writing ACPI tables at bfff2400...
\r
2173 ACPI: * HPET at bfff24c8
\r
2174 ACPI: added table 1/32, length now 40
\r
2175 ACPI: * MADT at bfff2500
\r
2176 ACPI: added table 2/32, length now 44
\r
2177 ACPI: * SRAT at bfff2580
\r
2178 SRAT: lapic cpu_index=00, node_id=00, apic_id=00
\r
2179 SRAT: lapic cpu_index=01, node_id=00, apic_id=01
\r
2180 SRAT: lapic cpu_index=02, node_id=00, apic_id=02
\r
2181 SRAT: lapic cpu_index=03, node_id=00, apic_id=03
\r
2182 SRAT: lapic cpu_index=04, node_id=00, apic_id=04
\r
2183 SRAT: lapic cpu_index=05, node_id=00, apic_id=05
\r
2184 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
\r
2185 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
\r
2186 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00480000
\r
2187 ACPI: added table 3/32, length now 48
\r
2188 ACPI: * SLIT at bfff2688
\r
2189 ACPI: added table 4/32, length now 52
\r
2190 ACPI: * SSDT at bfff26c0
\r
2191 ACPI: added table 5/32, length now 56
\r
2192 ACPI: * SSDT for PState at bfff2cf5
\r
2193 ACPI: * DSDT at bfff2cf8
\r
2194 ACPI: * DSDT @ bfff2cf8 Length 288b
\r
2195 ACPI: * FACS at bfff5588
\r
2196 ACPI: * FADT at bfff55c8
\r
2197 ACPI_BLK_BASE: 0x0800
\r
2198 ACPI: added table 6/32, length now 60
\r
2200 ACPI tables: 12988 bytes.
\r
2201 Adding CBMEM entry as no. 5
\r
2202 smbios_write_tables: bfffd800
\r
2203 Root Device (ASUS M5A99X-EVO Mainboard)
\r
2204 APIC_CLUSTER: 0 (AMD FAM10 Root Complex)
\r
2205 APIC: 00 (socket AM3)
\r
2206 PCI_DOMAIN: 0000 (AMD FAM10 Root Complex)
\r
2207 PCI: 00:18.0 (AMD FAM10 Northbridge)
\r
2208 PCI: 00:00.0 (ATI RS780)
\r
2209 PCI: 00:02.0 (ATI RS780)
\r
2210 PCI: 00:03.0 (ATI RS780)
\r
2211 PCI: 00:04.0 (ATI RS780)
\r
2212 PCI: 00:05.0 (ATI RS780)
\r
2213 PCI: 00:06.0 (ATI RS780)
\r
2214 PCI: 00:07.0 (ATI RS780)
\r
2215 PCI: 00:08.0 (ATI RS780)
\r
2216 PCI: 00:09.0 (ATI RS780)
\r
2217 PCI: 00:0a.0 (ATI RS780)
\r
2218 PCI: 00:11.0 (ATI SB900)
\r
2219 PCI: 00:12.0 (ATI SB900)
\r
2220 PCI: 00:12.2 (ATI SB900)
\r
2221 PCI: 00:13.0 (ATI SB900)
\r
2222 PCI: 00:13.2 (ATI SB900)
\r
2223 PCI: 00:14.0 (ATI SB900)
\r
2228 PCI: 00:14.1 (ATI SB900)
\r
2229 PCI: 00:14.2 (ATI SB900)
\r
2230 PCI: 00:14.3 (ATI SB900)
\r
2231 PNP: 002e.0 (ITE IT8721F Super I/O)
\r
2232 PNP: 002e.1 (ITE IT8721F Super I/O)
\r
2233 PNP: 002e.2 (ITE IT8721F Super I/O)
\r
2234 PNP: 002e.3 (ITE IT8721F Super I/O)
\r
2235 PNP: 002e.5 (ITE IT8721F Super I/O)
\r
2236 PNP: 002e.6 (ITE IT8721F Super I/O)
\r
2237 PNP: 002e.7 (ITE IT8721F Super I/O)
\r
2238 PNP: 002e.8 (ITE IT8721F Super I/O)
\r
2239 PNP: 002e.9 (ITE IT8721F Super I/O)
\r
2240 PNP: 002e.a (ITE IT8721F Super I/O)
\r
2241 PNP: 002e.b (ITE IT8721F Super I/O)
\r
2242 PCI: 00:14.4 (ATI SB900)
\r
2243 PCI: 00:14.5 (ATI SB900)
\r
2244 PCI: 00:14.6 (ATI SB900)
\r
2245 PCI: 00:15.0 (ATI SB900)
\r
2246 PCI: 00:15.1 (ATI SB900)
\r
2247 PCI: 00:15.2 (ATI SB900)
\r
2248 PCI: 00:15.3 (ATI SB900)
\r
2249 PCI: 00:16.0 (ATI SB900)
\r
2250 PCI: 00:16.2 (ATI SB900)
\r
2251 PCI: 00:18.1 (AMD FAM10 Northbridge)
\r
2252 PCI: 00:18.2 (AMD FAM10 Northbridge)
\r
2253 PCI: 00:18.3 (AMD FAM10 Northbridge)
\r
2254 PCI: 00:18.4 (AMD FAM10 Northbridge)
\r
2260 SMBIOS tables: 275 bytes.
\r
2262 Adding CBMEM entry as no. 6
\r
2263 Writing high table forward entry at 0x00000500
\r
2264 Wrote coreboot table at: 00000500 - 00000518 checksum 5fde
\r
2265 New low_table_end: 0x00000518
\r
2266 Now going to write high coreboot table at 0xbfffe000
\r
2267 rom_table_end = 0xbfffe000
\r
2268 Adjust low_table_end from 0x00000518 to 0x00001000
\r
2269 Adjust rom_table_end from 0xbfffe000 to 0xc0000000
\r
2270 Adding high table area
\r
2271 coreboot memory table:
\r
2272 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
\r
2273 1. 0000000000001000-000000000009ffff: RAM
\r
2274 2. 00000000000c0000-00000000bffeffff: RAM
\r
2275 3. 00000000bfff0000-00000000bfffffff: CONFIGURATION TABLES
\r
2276 4. 00000000e0000000-00000000efffffff: RESERVED
\r
2277 5. 0000000100000000-000000021fffffff: RAM
\r
2278 Wrote coreboot table at: bfffe000 - bfffe1e4 checksum 45ed
\r
2279 coreboot table: 484 bytes.
\r
2282 Multiboot Information structure has been written.
\r
2283 0. FREE SPACE c0000000 00000000
\r
2284 1. GDT bfff0200 00000200
\r
2285 2. IRQ TABLE bfff0400 00001000
\r
2286 3. SMP TABLE bfff1400 00001000
\r
2287 4. ACPI bfff2400 0000b400
\r
2288 5. SMBIOS bfffd800 00000800
\r
2289 6. COREBOOT bfffe000 00002000
\r
2290 Searching for fallback/payload
\r
2291 Check cmos_layout.bin
\r
2292 Check fallback/romstage
\r
2293 Check fallback/coreboot_ram
\r
2294 Check fallback/payload
\r
2296 Loading segment from rom address 0xffc353b8
\r
2297 data (compression=1)
\r
2298 New segment dstaddr 0xe4760 memsize 0x1b8a0 srcaddr 0xffc353f0 filesize 0xd4c7
\r
2299 (cleaned up) New segment addr 0xe4760 size 0x1b8a0 offset 0xffc353f0 filesize 0xd4c7
\r
2300 Loading segment from rom address 0xffc353d4
\r
2301 Entry Point 0x00000000
\r
2302 Loading Segment: addr: 0x00000000000e4760 memsz: 0x000000000001b8a0 filesz: 0x000000000000d4c7
\r
2303 lb: [0x0000000000200000, 0x0000000000338000)
\r
2304 Post relocation: addr: 0x00000000000e4760 memsz: 0x000000000001b8a0 filesz: 0x000000000000d4c7
\r
2306 [ 0x000e4760, 00100000, 0x00100000) <- ffc353f0
\r
2307 dest 000e4760, end 00100000, bouncebuffer bfd80000
\r
2309 Jumping to boot code at fbfe4
\r
2311 entry = 0x000fbfe4
\r
2312 lb_start = 0x00200000
\r
2313 lb_size = 0x00138000
\r
2314 adjust = 0xbfcb8000
\r
2315 buffer = 0xbfd80000
\r
2316 elf_boot_notes = 0x00234dbc
\r
2317 adjusted_boot_notes = 0xbfeecdbc
\r
2318 Start bios (version 1.6.3-20120203_185825-oldx86)
\r
2320 Attempting to find coreboot table
\r
2321 Found coreboot table forwarder.
\r
2322 Now attempting to find coreboot memory map
\r
2323 Add to e820 map: 00000000 00001000 2
\r
2324 Add to e820 map: 00001000 0009f000 1
\r
2325 Add to e820 map: 000c0000 bff30000 1
\r
2326 Add to e820 map: bfff0000 00010000 2
\r
2327 Add to e820 map: e0000000 10000000 2
\r
2328 Add to e820 map: 00000000 20000000 1
\r
2329 Add to e820 map: 00000000 00004000 1
\r
2330 Found mainboard ASUS M5A99X-EVO
\r
2331 Found CBFS header at 0xfffffca0
\r
2332 Add to e820 map: 000a0000 00050000 -1
\r
2333 Add to e820 map: 000f0000 00010000 2
\r
2334 Ram Size=0xbfff0000 (0x0000000120000000 high)
\r
2336 Add to e820 map: bffe0000 00010000 2
\r
2337 pmm_malloc zone=0x000f0158 handle=ffffffff size=45564 align=10 ret=0xbffd4ce0 (detail=0xbffdfee0)
\r
2338 Relocating init from 0x000e4fd0 to 0xbffd4ce0 (size 45564)
\r
2339 malloc fixup reloc
\r
2342 Add to e820 map: 0009fc00 00000400 2
\r
2345 tsc calibrate start=565406097 end=566780804 diff=1374707
\r
2349 Searching CBFS for prefix etc/extra-pci-roots
\r
2350 Found CBFS file cmos_layout.bin
\r
2351 Found CBFS file fallback/romstage
\r
2352 Found CBFS file fallback/coreboot_ram
\r
2353 Found CBFS file fallback/payload
\r
2354 Found CBFS file config
\r
2356 pmm_malloc zone=0xbffdfe68 handle=ffffffff size=112 align=10 ret=0xbffd4c10 (detail=0xbffd4c80)
\r
2357 PCI device 00:00.0 (vd=1002:5a14 c=0600)
\r