From ea11b8a1f00f62aed7584f257f0a8a90e982a707 Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Wed, 12 Jan 2011 19:51:45 +0100 Subject: [PATCH] default baudrate setting now in top level entity --- cpu/src/core_pkg.vhd | 3 ++- cpu/src/core_top.vhd | 2 +- cpu/src/core_top_c2de1.vhd | 2 +- cpu/src/extension_uart.vhd | 3 ++- cpu/src/extension_uart_pkg.vhd | 5 +++-- cpu/src/writeback_stage.vhd | 3 ++- cpu/src/writeback_stage_b.vhd | 3 ++- 7 files changed, 13 insertions(+), 8 deletions(-) diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd index 87cfcc6..9731f37 100644 --- a/cpu/src/core_pkg.vhd +++ b/cpu/src/core_pkg.vhd @@ -127,7 +127,8 @@ package core_pkg is RESET_VALUE : std_logic; -- active logic value LOGIC_ACT : std_logic; - FPGATYPE : string + FPGATYPE : string; + CLK_BAUD : integer ); port( --System inputs diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd index 452db69..6815be1 100644 --- a/cpu/src/core_top.vhd +++ b/cpu/src/core_top.vhd @@ -156,7 +156,7 @@ begin -- writeback_st : writeback_stage - generic map('0', '1', "altera") + generic map('0', '1', "altera", 2083) port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, diff --git a/cpu/src/core_top_c2de1.vhd b/cpu/src/core_top_c2de1.vhd index adecfee..0d149c1 100644 --- a/cpu/src/core_top_c2de1.vhd +++ b/cpu/src/core_top_c2de1.vhd @@ -138,7 +138,7 @@ begin writeback_st : writeback_stage - generic map(RESET_VALUE, '1', "altera") + generic map(RESET_VALUE, '1', "altera", 434) port map(sys_clk, sys_res_n and soft_res_n, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, diff --git a/cpu/src/extension_uart.vhd b/cpu/src/extension_uart.vhd index f593164..07d6bda 100644 --- a/cpu/src/extension_uart.vhd +++ b/cpu/src/extension_uart.vhd @@ -11,7 +11,8 @@ entity extension_uart is generic ( -- active reset value - RESET_VALUE : std_logic + RESET_VALUE : std_logic; + CLK_PER_BAUD : integer ); port( --System inputs diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd index 6f6580b..1bbe2b8 100644 --- a/cpu/src/extension_uart_pkg.vhd +++ b/cpu/src/extension_uart_pkg.vhd @@ -22,7 +22,7 @@ subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0); --constant CLK_FREQ_MHZ : real := 33.33; --constant BAUD_RATE : integer := 115200; --constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5); - constant CLK_PER_BAUD : integer := 434; +-- constant CLK_PER_BAUD : integer := 434; -- constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud -- constant CLK_PER_BAUD : integer := 50; -- @modelsim @@ -30,7 +30,8 @@ subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0); --some modules won't need all inputs/outputs generic ( -- active reset value - RESET_VALUE : std_logic + RESET_VALUE : std_logic; + CLK_PER_BAUD : integer ); port( --System inputs diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd index 9ec5986..ea82a1e 100644 --- a/cpu/src/writeback_stage.vhd +++ b/cpu/src/writeback_stage.vhd @@ -11,7 +11,8 @@ entity writeback_stage is RESET_VALUE : std_logic; -- active logic value LOGIC_ACT : std_logic; - FPGATYPE : string + FPGATYPE : string; + CLK_BAUD : integer ); port( --System inputs diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd index a031207..78a17a4 100755 --- a/cpu/src/writeback_stage_b.vhd +++ b/cpu/src/writeback_stage_b.vhd @@ -69,7 +69,8 @@ begin uart : extension_uart generic map( - RESET_VALUE + RESET_VALUE, + CLK_BAUD ) port map( clk , -- 2.25.1