From df2e395c56679967ad89ffb2911f760cf4c125e5 Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Sat, 11 Dec 2010 13:54:19 +0100 Subject: [PATCH] fib --- cpu/src/decoder_b.vhd | 17 +++++++++--- cpu/src/r_w_ram_b.vhd | 61 +++++++++++++++++++++++++++++-------------- 2 files changed, 55 insertions(+), 23 deletions(-) diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd index 6537555..01c11f0 100644 --- a/cpu/src/decoder_b.vhd +++ b/cpu/src/decoder_b.vhd @@ -215,19 +215,28 @@ begin -- when "01110" => --ldw instr_s.reg_dest_addr := instruction(22 downto 19); instr_s.reg_src1_addr := instruction(18 downto 15); - instr_s.immediate(15 downto 0) := instruction(18 downto 3); instr_s.signext := instruction(2); instr_s.high_low := instruction(1); instr_s.op_group := LDST_OP; instr_s.op_detail(NO_PSW_OPT) := '1'; - if (instr_s.opcode = "11010") then + if (instr_s.opcode = "11010") then --ldi + if (instr_s.high_low = '1') then + instr_s.immediate(31 downto 16) := instruction(18 downto 3); + instr_s.immediate(15 downto 0) := (others => '0'); + else + instr_s.immediate(15 downto 0) := instruction(18 downto 3); + instr_s.immediate(31 downto 16) := (others => '0'); + + --instr_s.immediate(11 downto 0) := instruction(14 downto 3); + --instr_s.immediate(WORD_WIDTH-1 downto 12) := (others => '0'); + end if; + if (instr_s.signext = '1' and instr_s.immediate(11) = '1') then instr_s.immediate(31 downto 16) := (others => '1'); end if; - instr_s.immediate(11 downto 0) := instruction(14 downto 3); - instr_s.immediate(WORD_WIDTH-1 downto 12) := (others => '0'); + instr_s.op_detail(IMM_OPT) := '1'; end if; end if; diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd index 14cc3be..204479e 100644 --- a/cpu/src/r_w_ram_b.vhd +++ b/cpu/src/r_w_ram_b.vhd @@ -12,25 +12,48 @@ architecture behaviour of r_w_ram is -- r0 = 0, r1 = 1, r2 = 3, r3 = A - signal ram : RAM_TYPE := ( 0 => "11101011000000000000000010000101", -- call +1 - - 1 => "11101101000010000000000000111000", -- r1 = 7 - 2 => "11101101000100000000000000101000", -- r2 = 5 - 3 => "11101101000110000000000000100000", -- r3 = 4 - 4 => "11100000001000010001100000000000", -- r4 = r2 + r3 - 5 => "11100010001010100000100000000000", -- r5 = r4 and r1 - - 6 => "11101011000000000000000000001011", -- r0 = r0 + 1 --- 7 => "11101100100000000000000000011000", -- cmpi r0 , 2 - - 7 => "00001011011111111111110010000111", -- jump -7 - 8 => "11101011000000000000000010000010", -- jump +1 - --10 => "11101011000000000000000010000010", -- jump +1 - - 9 => "11100111101010100000000000000001", -- stw r5,r4,1 - 10 => "11101100001000100000000000000000", -- cmp r4 , r4 => 2-2 => 1001 - - 11 => "11101011000000000000000000000010", -- jump +0 + signal ram : RAM_TYPE := ( +0 => x"ed080048", --;ldi r1, 9;; +1 => x"ed500080", --;ldil r10, list@lo ;; global pointer +2 => x"fd500002", --;ldih r10, list@hi;; +3 => x"eb000107", --;call+ fibcall;; +4 => x"eb7ffe03", --;br+ main;; + --2; fib(n) { + --2; if (list[n] > 0) { + --2; return list[n] + --2; } + --2; a = fib(n-1) + --2; list[n] = a + list[n-2] + --2; return list[n] + --2; } + --3;fibcall; + --2;update counter for aligned access +5 => x"e5088800", --;lls r1, r1, 2 ;; *4 + --2;calculate adress of top element +6 => x"e0150800", --;add r2, r10, r1;; + --3;fibmem; + --2;load top element +7 => x"e7010000", --;ldw r0, 0(r2);; + --2;compare if set +8 => x"ec800000", --;cmpi r0, 0;; + --2;return if set +9 => x"0b000008", --;retnz-;; + --2;decrement adress for next lopp +10 => x"e1910020", --;subi r2, r2, 4;; + --2;iterative call for n-1 element +11 => x"eb7ffe07", --;call+ fibmem;; + --2;load n-2 element +12 => x"e7197ffc", --;ldw r3, 0-4(r2);; + --2;add n-1 and n-2 element +13 => x"e0018000", --;add r0, r3, r0;; + --2;increment address for n element + --2;is needed because after return + --2;we need r2 to be set to the address + --2;of element n +14 => x"e1110020", --;addi r2, r2, 4;; + --2;store fib n +15 => x"e7810000", --;stw r0, 0(r2);; +16 => x"eb00000a", --;ret+;; -- 2.25.1