From d1e680464f7b7147dc4b435a27973621fd69f065 Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Wed, 1 Dec 2010 20:38:48 +0100 Subject: [PATCH] static branch incl prediction rc1 --- cpu/sim/testcore.do | 6 ++- cpu/src/alu.vhd | 9 ++-- cpu/src/alu_b.vhd | 83 +++++++++++++++++++---------------- cpu/src/alu_pkg.vhd | 1 + cpu/src/common_pkg.vhd | 1 + cpu/src/decode_stage_b.vhd | 8 +++- cpu/src/execute_stage_b.vhd | 4 +- cpu/src/extension.vhd | 2 +- cpu/src/extension_pkg.vhd | 2 +- cpu/src/fetch_stage_b.vhd | 6 ++- cpu/src/pipeline_tb.vhd | 2 +- cpu/src/r_w_ram_b.vhd | 25 ++++++++--- cpu/src/writeback_stage_b.vhd | 7 ++- 13 files changed, 96 insertions(+), 60 deletions(-) diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do index b79d4c3..c1a219c 100644 --- a/cpu/sim/testcore.do +++ b/cpu/sim/testcore.do @@ -28,9 +28,11 @@ vcom -work work ../src/exec_op/shift_op_b.vhd vcom -work work ../src/alu.vhd vcom -work work ../src/alu_b.vhd +vcom -work work ../src/extension_pkg.vhd +vcom -work work ../src/gpm_pkg.vhd -vcom -work work ../src/gpm.vhd -vcom -work work ../src/gpm_b.vhd +#vcom -work work ../src/gpm.vhd +#vcom -work work ../src/gpm_b.vhd vcom -work work ../src/extension_pkg.vhd vcom -work work ../src/extension.vhd diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd index 82656ab..e59d268 100755 --- a/cpu/src/alu.vhd +++ b/cpu/src/alu.vhd @@ -16,13 +16,14 @@ entity alu is cond : in condition_t; op_group : in op_info_t; left_operand : in gp_register_t; - right_operand : in gp_register_t; - displacement : in gp_register_t; + right_operand : in gp_register_t; + displacement : in gp_register_t; prog_cnt : in instr_addr_t; + brpr : in std_logic; op_detail : in op_opt_t; alu_state : in alu_result_rec; - alu_result : out alu_result_rec; - addr : out word_t; --memaddr + alu_result : out alu_result_rec; + addr : out word_t; --memaddr data : out gp_register_t --mem data --ureg ); diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd index 8399d60..696e0f7 100755 --- a/cpu/src/alu_b.vhd +++ b/cpu/src/alu_b.vhd @@ -21,7 +21,7 @@ architecture behaviour of alu is ); end component exec_op; - signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec; + signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec; signal left, right : gp_register_t; begin @@ -41,28 +41,29 @@ begin shift_inst : entity work.exec_op(shift_op) port map(clk,reset,left, right, op_detail, alu_state, shift_result); -calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result) +calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr) variable result_v : alu_result_rec; variable res_prod : std_logic; variable cond_met : std_logic; - variable mem_en : std_logic; - variable mem_op : std_logic; - variable alu_jmp : std_logic; + variable mem_en : std_logic; + variable mem_op : std_logic; + variable alu_jump : std_logic; + variable nop : std_logic; begin result_v := alu_state; res_prod := '1'; - mem_en := '0'; - mem_op := '0'; + mem_en := '0'; + mem_op := '0'; alu_jump := '0'; - - left <= left_operand; - right <= right_operand; - - addr <= add_result.result; + + left <= left_operand; + right <= right_operand; + + addr <= add_result.result; data <= right_operand; - - result_v.result := add_result.result; + + result_v.result := add_result.result; case cond is when COND_NZERO => @@ -99,8 +100,9 @@ begin cond_met := '0'; when others => null; end case; - - cond_met := cond_met and (alu_state.alu_jmp xnor alu_state.brpr); + + nop := (alu_state.alu_jump xnor alu_state.brpr); + cond_met := cond_met and nop; case op_group is when ADDSUB_OP => @@ -112,24 +114,24 @@ begin when XOR_OP => result_v := xor_result; when SHIFT_OP => - result_v := shift_result; - when LDST_OP => - res_prod := '0'; - mem_op := '1'; - if op_detail(IMM_OPT) = '1' then - result_v.result := right_operand; - res_prod := '1'; - mem_op := '0'; - end if; - if op_detail(ST_OPT) = '1' then - right <= displacement; - mem_en := '1'; - end if; - when JMP_OP => - if op_detail(JMP_REG_OPT) = '0' then - left <= prog_cnt; - end if; - result_v.alu_jmp := '1'; + result_v := shift_result; + when LDST_OP => + res_prod := '0'; + mem_op := '1'; + if op_detail(IMM_OPT) = '1' then + result_v.result := right_operand; + res_prod := '1'; + mem_op := '0'; + end if; + if op_detail(ST_OPT) = '1' then + right <= displacement; + mem_en := '1'; + end if; + when JMP_OP => + if op_detail(JMP_REG_OPT) = '0' then + left <= prog_cnt; + end if; + alu_jump := '1'; when JMP_ST_OP => null; end case; @@ -146,10 +148,17 @@ begin end if; result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met; - result_v.mem_en := mem_en and cond_met; - result_v.mem_op := mem_op and cond_met; - result_v.alu_jmp := alu_jmp and cond_met; + result_v.mem_en := mem_en and cond_met; + result_v.mem_op := mem_op and cond_met; + result_v.alu_jump := alu_jump and cond_met; + result_v.brpr := brpr and nop; + if (result_v.alu_jump = '0') and (brpr = '1') then + result_v.result := (others => '0'); + result_v.result(prog_cnt'range) := std_logic_vector(unsigned(prog_cnt)+1); + --result_v.reg_op := '1'; + end if; + alu_result <= result_v; end process calc; diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd index f1c99dc..bb15c6a 100755 --- a/cpu/src/alu_pkg.vhd +++ b/cpu/src/alu_pkg.vhd @@ -86,6 +86,7 @@ package alu_pkg is right_operand : in gp_register_t; displacement : in gp_register_t; prog_cnt : in instr_addr_t; + brpr : in std_logic; op_detail : in op_opt_t; alu_state : in alu_result_rec; alu_result : out alu_result_rec; diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd index 03e61cd..2379165 100755 --- a/cpu/src/common_pkg.vhd +++ b/cpu/src/common_pkg.vhd @@ -34,6 +34,7 @@ package common_pkg is subtype instruction_word_t is std_logic_vector(WORD_WIDTH-1 downto 0); subtype instruction_addr_t is std_logic_vector(INSTR_ADDR_WIDTH-1 downto 0); + subtype instr_addr_t is instruction_addr_t; subtype gp_addr_t is std_logic_vector(REG_ADDR_WIDTH-1 downto 0); subtype data_ram_word_t is std_logic_vector(WORD_WIDTH-1 downto 0); diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd index c8075a1..dc5e389 100644 --- a/cpu/src/decode_stage_b.vhd +++ b/cpu/src/decode_stage_b.vhd @@ -93,7 +93,7 @@ end process; -- end record; -- output logic incl. bypassing reg-file -output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data) +output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data, nop) begin @@ -101,6 +101,10 @@ begin to_next_stage.src1 <= reg1_rd_data; to_next_stage.src2 <= reg2_rd_data; + if (nop = '1') then + to_next_stage.condition <= "1111"; + end if; + end process; @@ -184,7 +188,7 @@ begin branch_prediction_bit <= '0'; if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then - branch_prediction_res <= instr_spl.immediate; --both 32 bit + branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt)); --both 32 bit branch_prediction_bit <= '1'; end if; diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd index 88d3541..a7809e5 100644 --- a/cpu/src/execute_stage_b.vhd +++ b/cpu/src/execute_stage_b.vhd @@ -35,7 +35,7 @@ begin alu_inst : alu port map(clk, reset, condition, op_group, - left_operand, right_operand, dec_instr.displacement, op_detail, alu_state, alu_nxt,addr,data); + left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, alu_nxt,addr,data); @@ -78,7 +78,7 @@ begin - alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0'); + alu_state <= (reg.result,dec_instr.daddr,psw,reg.alu_jump,reg.brpr,'0','0','0','0','0','0'); if reset = RESET_VALUE then diff --git a/cpu/src/extension.vhd b/cpu/src/extension.vhd index 9ddb33e..ab53a3c 100644 --- a/cpu/src/extension.vhd +++ b/cpu/src/extension.vhd @@ -5,7 +5,7 @@ use IEEE.numeric_std.all; use work.common_pkg.all; use work.extension_pkg.all; use work.alu_pkg.all; -use work.gpm_pkg.all; +--use work.gpm_pkg.all; entity extension_gpm is diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd index 49d5cdb..14253d6 100644 --- a/cpu/src/extension_pkg.vhd +++ b/cpu/src/extension_pkg.vhd @@ -5,7 +5,7 @@ use IEEE.numeric_std.all; use work.common_pkg.all; use work.alu_pkg.all; -use work.gpm_pkg.all; +--use work.gpm_pkg.all; package extension_pkg is diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd index a73ab05..7409e42 100644 --- a/cpu/src/fetch_stage_b.vhd +++ b/cpu/src/fetch_stage_b.vhd @@ -57,14 +57,16 @@ begin end if; if (alu_jump_bit = LOGIC_ACT) then - instr_r_addr_nxt <= jump_result; + instr_r_addr_nxt <= jump_result; + instruction(31 downto 28) <= "1111"; elsif (branch_prediction_bit = LOGIC_ACT) then instr_r_addr_nxt <= prediction_result; end if; end process; -prog_cnt <= std_logic_vector(unsigned(instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0)) + 1; +prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0))); +prog_cnt(31 downto 11) <= (others => '0'); end behav; diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd index 3315344..aafbd4c 100644 --- a/cpu/src/pipeline_tb.vhd +++ b/cpu/src/pipeline_tb.vhd @@ -133,7 +133,7 @@ begin - nop_pin <= (alu_jump_bit_pin xor brpr_pin); + nop_pin <= (alu_jump_bit_pin);-- xor brpr_pin); ------------------------------------------------------------------------------- -- generate simulation clock diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd index 94362f7..585dc92 100644 --- a/cpu/src/r_w_ram_b.vhd +++ b/cpu/src/r_w_ram_b.vhd @@ -12,13 +12,24 @@ architecture behaviour of r_w_ram is -- r0 = 0, r1 = 1, r2 = 3, r3 = A - signal ram : RAM_TYPE := ( 0 => "11101101000010000000000000111000", -- r1 = 7 - 1 => "11101101000100000000000000101000", -- r2 = 5 - 2 => "11101101000110000000000000100000", -- r3 = 4 - 3 => "11100000001000010001100000000000", -- r4 = r2 + r3 - 4 => "11100010001010100000100000000000", -- r5 = r4 and r1 - 5 => "11100111101010100000000000000001", -- stw r5,r4,1 - 6 => "11101100001000100000000000000000", --cmp r4 , r4 => 2-2 => 1001 + signal ram : RAM_TYPE := ( + 1 => "11101101000010000000000000111000", -- r1 = 7 + 2 => "11101101000100000000000000101000", -- r2 = 5 + 3 => "11101101000110000000000000100000", -- r3 = 4 + 4 => "11100000001000010001100000000000", -- r4 = r2 + r3 + 5 => "11100010001010100000100000000000", -- r5 = r4 and r1 + + 6 => "11100001000000000000000000001000", -- r0 = r0 + 1 + 7 => "11101100100000000000000000010000", -- cmpi r0 , 2 => 2-2 => 1001 + + 8 => "00001011011111111111110010000011", -- jump -7 + 9 => "11101011000000000000000010000010", -- jump +1 + + 10 => "11100111101010100000000000000001", -- stw r5,r4,1 + 11 => "11101100001000100000000000000000", --cmp r4 , r4 => 2-2 => 1001 + + 0 => "11101101000000000000000000000000", -- r0 = 0 + others => x"F0000000"); diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd index eca8412..3573680 100644 --- a/cpu/src/writeback_stage_b.vhd +++ b/cpu/src/writeback_stage_b.vhd @@ -95,7 +95,12 @@ begin end if; end if; - jump <= alu_jmp xor br_pred; + jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en); + + if alu_jmp = '0' and br_pred = '1' and write_en = '0' then + jump <= '1'; + end if; + jump_addr <= result; if ((alu_jmp and wb_reg.dmem_en) = '1') then jump_addr <= data_ram_read; -- 2.25.1