From c6058efc1e0d3571611da8472cbaf55aed799586 Mon Sep 17 00:00:00 2001 From: Martin Perner Date: Sun, 16 Jan 2011 12:31:16 +0100 Subject: [PATCH] added de2-115 top --- cpu/src/core_top_c4de2_115.vhd | 207 +++++++++++++++++++++++++++++++++ 1 file changed, 207 insertions(+) create mode 100644 cpu/src/core_top_c4de2_115.vhd diff --git a/cpu/src/core_top_c4de2_115.vhd b/cpu/src/core_top_c4de2_115.vhd new file mode 100644 index 0000000..ed88a26 --- /dev/null +++ b/cpu/src/core_top_c4de2_115.vhd @@ -0,0 +1,207 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.common_pkg.all; +use work.core_pkg.all; +use work.extension_pkg.all; + +entity core_top_c4de2_115 is + + port( + --System input pins + CLOCK_50 : in std_logic; + --Reset buttons + KEY : in std_logic_vector(0 to 3); + + -- uart + UART_TXD : out std_logic; + UART_RXD : in std_logic; + -- bootrom led + LEDR : out std_logic_vector(0 to 17); + LEDG : out std_logic_vector(0 to 8); + + HEX0 : out std_logic_vector(0 to 6); + HEX1 : out std_logic_vector(0 to 6); + HEX2 : out std_logic_vector(0 to 6); + HEX3 : out std_logic_vector(0 to 6); + + + LCD_DATA_8 : out std_logic_vector(7 downto 0); + LCD_BLON : out std_logic; + LCD_RW : out std_logic; + LCD_EN : out std_logic; + LCD_RS : out std_logic; + LCD_ON : out std_logic + + + ); + +end core_top_c4de2_115; + +architecture behav of core_top_c4de2_115 is + + constant SYNC_STAGES : integer := 2; + constant RESET_VALUE : std_logic := '0'; + + signal sys_clk, sys_res, soft_res : std_logic; + signal bus_tx, bus_rx : std_logic; + signal led2 : std_logic; + signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6); + + signal jump_result : instruction_addr_t; + signal jump_result_pin : instruction_addr_t; + signal prediction_result_pin : instruction_addr_t; + signal branch_prediction_bit_pin : std_logic; + signal alu_jump_bit_pin : std_logic; + signal instruction_pin : instruction_word_t; + signal prog_cnt_pin : instruction_addr_t; + + signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0); + signal reg_wr_data_pin : gp_register_t; + signal reg_we_pin : std_logic; + signal to_next_stage : dec_op; + + signal result_pin : gp_register_t;--reg + signal result_addr_pin : gp_addr_t;--reg + signal addr_pin : word_t; --memaddr + signal data_pin : gp_register_t; --mem data --ureg + signal alu_jump_pin : std_logic;--reg + signal brpr_pin : std_logic; --reg + signal wr_en_pin : std_logic;--regop --reg + signal dmem_pin : std_logic;--memop + signal dmem_wr_en_pin : std_logic; + signal hword_pin : std_logic; + signal byte_s_pin : std_logic; + + signal gpm_in_pin : extmod_rec; + signal gpm_out_pin : gp_register_t; + signal nop_pin : std_logic; + + signal sync : std_logic_vector(1 to SYNC_STAGES); + signal sync2 : std_logic_vector(1 to SYNC_STAGES); + signal sys_res_n, soft_res_n : std_logic; + + signal int_req : interrupt_t; + + signal new_im_data : std_logic; + signal im_addr, im_data : gp_register_t; +-- signal led2 : std_logic; + + signal vers, vers_nxt : exec2wb_rec; +begin + sys_clk <= CLOCK_50; + sys_res <= KEY(0); + soft_res <= KEY(1); + + UART_TXD <= bus_tx; + bus_rx <= UART_RXD; + + --bootrom status + LEDR(0) <= led2; + LEDR(1 to 17) <= (others => '0'); + LEDG <= (others => '0'); + + HEX0 <= sseg0; + HEX1 <= sseg1; + HEX2 <= sseg2; + HEX3 <= sseg3; + + fetch_st : fetch_stage + generic map ( + + RESET_VALUE, + '1' + ) + + port map ( + --System inputs + clk => sys_clk, --: in std_logic; + reset => sys_res_n, --: in std_logic; + s_reset => soft_res_n, + + --Data inputs + jump_result => jump_result_pin, --: in instruction_addr_t; + prediction_result => prediction_result_pin, --: in instruction_addr_t; + branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic; + alu_jump_bit => alu_jump_bit_pin, --: in std_logic; + int_req => int_req, + -- instruction memory program port :D + new_im_data_in => new_im_data, + im_addr => im_addr, + im_data => im_data, + --Data outputs + instruction => instruction_pin, --: out instruction_word_t + prog_cnt => prog_cnt_pin, + led2 => led2 + ); + + decode_st : decode_stage + generic map ( + -- active reset value + RESET_VALUE, + -- active logic value + '1' + ) + port map ( + --System inputs + clk => sys_clk, --: in std_logic; + reset => sys_res_n and soft_res_n, -- : in std_logic; + + --Data inputs + instruction => instruction_pin, --: in instruction_word_t; + prog_cnt => prog_cnt_pin, + reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0); + reg_wr_data => reg_wr_data_pin, --: in gp_register_t; + reg_we => reg_we_pin, --: in std_logic; + nop => nop_pin, + + --Data outputs + branch_prediction_res => prediction_result_pin, --: instruction_word_t; + branch_prediction_bit => branch_prediction_bit_pin, --: std_logic + to_next_stage => to_next_stage + ); + + exec_st : execute_stage + generic map(RESET_VALUE) + port map(sys_clk, sys_res_n and soft_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, + data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin); + + writeback_st : writeback_stage + generic map(RESET_VALUE, '1', "altera", 434) + port map(sys_clk, sys_res_n and soft_res_n, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, + wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, + reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, + new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req); + + + +syn: process(sys_clk, sys_res) + +begin + + if sys_res = RESET_VALUE then + + sync <= (others => RESET_VALUE); + + elsif rising_edge(sys_clk) then + sync(1) <= sys_res; + for i in 2 to SYNC_STAGES loop + sync(i) <= sync(i - 1); + end loop; + + sync2(1) <= soft_res; + for i in 2 to SYNC_STAGES loop + sync2(i) <= sync2(i - 1); + end loop; + + end if; + +end process; + +sys_res_n <= sync(SYNC_STAGES); +soft_res_n <= sync2(SYNC_STAGES); +nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin); +jump_result <= prog_cnt_pin; --jump_result_pin; + +end behav; -- 2.25.1