From a70afaae294cdb93b51ca938ddf18e2ce88f0451 Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Sun, 9 Jan 2011 11:51:58 +0100 Subject: [PATCH] cyclone: pinmapping und reset angepasst @stefan: reset ist nun high aktiv in der core_top.vhd bitte fuer dein fpga anpassen, am besten in einem eigenen top-file! --- cpu/src/core_top.vhd | 8 +++++--- cpu/src/extension_uart_pkg.vhd | 3 ++- cpu/src/fetch_stage_b.vhd | 4 ++-- cpu/src/rom_b.vhd | 2 +- dt/dt.qsf | 8 +++++--- 5 files changed, 15 insertions(+), 10 deletions(-) diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd index 242683e..13d8263 100644 --- a/cpu/src/core_top.vhd +++ b/cpu/src/core_top.vhd @@ -17,6 +17,7 @@ entity core_top is -- uart bus_tx : out std_logic; bus_rx : in std_logic; + led2 : out std_logic; sseg0 : out std_logic_vector(0 to 6); sseg1 : out std_logic_vector(0 to 6); @@ -98,7 +99,8 @@ begin im_data => im_data, --Data outputs instruction => instruction_pin, --: out instruction_word_t - prog_cnt => prog_cnt_pin + prog_cnt => prog_cnt_pin, + led2 => led2 ); decode_st : decode_stage @@ -167,7 +169,7 @@ syn: process(sys_clk, sys_res) begin - if sys_res = '0' then + if sys_res = '1' then -- vers.result <= (others => '0'); -- vers.result_addr <= (others => '0'); -- vers.address <= (others => '0'); @@ -184,7 +186,7 @@ begin elsif rising_edge(sys_clk) then -- vers <= vers_nxt; - sync(1) <= sys_res; + sync(1) <= not sys_res; for i in 2 to SYNC_STAGES loop sync(i) <= sync(i - 1); end loop; diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd index 2a4ca4b..49b46ec 100644 --- a/cpu/src/extension_uart_pkg.vhd +++ b/cpu/src/extension_uart_pkg.vhd @@ -22,7 +22,8 @@ subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0); --constant CLK_FREQ_MHZ : real := 33.33; --constant BAUD_RATE : integer := 115200; --constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5); -constant CLK_PER_BAUD : integer := 434; +-- constant CLK_PER_BAUD : integer := 434; +constant CLK_PER_BAUD : integer := 173; -- @uni, bei 20MHz und 115200 Baud component extension_uart is --some modules won't need all inputs/outputs diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd index 23d8ecf..6ad9157 100644 --- a/cpu/src/fetch_stage_b.vhd +++ b/cpu/src/fetch_stage_b.vhd @@ -53,9 +53,11 @@ begin if (reset = RESET_VALUE) then instr_r_addr <= (others => '0'); rom_ram <= ROM_USE; + led2 <= '0'; elsif rising_edge(clk) then instr_r_addr <= instr_r_addr_nxt; rom_ram <= rom_ram_nxt; + led2 <= rom_ram_nxt; end if; end process; @@ -121,7 +123,5 @@ begin end process; -led2 <= rom_ram; - end behav; diff --git a/cpu/src/rom_b.vhd b/cpu/src/rom_b.vhd index 492c5a6..9af8d82 100644 --- a/cpu/src/rom_b.vhd +++ b/cpu/src/rom_b.vhd @@ -132,7 +132,7 @@ begin when "0000110" => data_out <= x"ed210120"; -- ldi r4, 0x2024 when "0000111" => data_out <= x"ed280018"; -- ldi r5, 3 when "0001000" => data_out <= x"e7aa0000"; -- stw r5, 0(r4) - -- when "0001001" => data_out <= x"eb7ffb83"; -- br+ start + when "0001001" => data_out <= x"eb7ffb83"; -- br+ start when "0001010" => data_out <= x"ed4101a0"; -- ldi r8, 0x2034 when "0001011" => data_out <= x"ed4901c0"; -- ldi r9, 0x2038 when "0001100" => data_out <= x"e4555000"; -- xor r10, r10, r10 diff --git a/dt/dt.qsf b/dt/dt.qsf index 5916bb3..aed8015 100644 --- a/dt/dt.qsf +++ b/dt/dt.qsf @@ -44,7 +44,6 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:08:54 DECEMBER 16, 2 set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1" set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name GENERATE_RBF_FILE ON set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" @@ -57,6 +56,9 @@ set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" set_location_assignment PIN_178 -to bus_tx set_location_assignment PIN_152 -to sys_clk +set_location_assignment PIN_153 -to bus_rx +set_location_assignment PIN_166 -to led2 +set_location_assignment PIN_42 -to sys_res set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" @@ -75,8 +77,6 @@ set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON set_global_assignment -name MUX_RESTRUCTURE OFF set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_location_assignment PIN_153 -to bus_rx -set_location_assignment PIN_42 -to sys_res_unsync set_global_assignment -name FMAX_REQUIREMENT "50 MHz" set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be_b.vhd set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be.vhd @@ -133,4 +133,6 @@ set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd + + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file -- 2.25.1