From 83b7ca00d6632a98db8b465f4d504650b9ba199c Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Mon, 15 Nov 2010 18:32:14 +0100 Subject: [PATCH] pipe v1 --- cpu/sim/testcore.do | 2 +- cpu/src/alu_b.vhd | 10 +++++----- cpu/src/exec_op/add_op_b.vhd | 3 ++- cpu/src/r2_w_ram_b.vhd | 8 ++++---- cpu/src/r_w_ram_b.vhd | 2 +- 5 files changed, 13 insertions(+), 12 deletions(-) diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do index 6f5b7c8..4f66a62 100644 --- a/cpu/sim/testcore.do +++ b/cpu/sim/testcore.do @@ -60,4 +60,4 @@ add wave -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr add wave -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data add wave -radix hexadecimal /pipeline_tb/decode_st/reg_we -run 500000 ns +run 5000 ns diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd index 3fb3434..f3a25ee 100755 --- a/cpu/src/alu_b.vhd +++ b/cpu/src/alu_b.vhd @@ -38,7 +38,7 @@ begin shift_inst : exec_op port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result); -calc: process(cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result) +calc: process(left_operand, right_operand, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result) variable result_v : alu_result_rec; variable res_prod : std_logic; variable cond_met : std_logic; @@ -48,7 +48,7 @@ begin result_v.result := add_result.result; res_prod := '1'; - mem_en := '0'; + mem_en := '0'; addr <= add_result.result; case cond is @@ -83,7 +83,7 @@ begin when COND_ALWAYS => cond_met := '1'; when COND_NEVER => - cond_met := '0'; + cond_met := '0'; when others => null; end case; @@ -111,8 +111,8 @@ begin end if; result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met; - result_v.mem_en := mem_en and cond_met; - + result_v.mem_en := mem_en and cond_met; + data <= add_result.result; alu_result <= result_v; diff --git a/cpu/src/exec_op/add_op_b.vhd b/cpu/src/exec_op/add_op_b.vhd index 88e34d4..0e28af8 100644 --- a/cpu/src/exec_op/add_op_b.vhd +++ b/cpu/src/exec_op/add_op_b.vhd @@ -30,7 +30,8 @@ begin complement := inc(not(right_operand)); l_neg := left_operand(gp_register_t'high); - carry_res := unsigned('0' & left_operand)+addcarry; + --carry_res := unsigned('0' & left_operand)+addcarry; + carry_res := unsigned('0' & left_operand); oflo1 := add_oflo(l_neg,'0',carry_res(gp_register_t'high)); if sub = '1' then diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd index 3c71ade..d067ad3 100644 --- a/cpu/src/r2_w_ram_b.vhd +++ b/cpu/src/r2_w_ram_b.vhd @@ -11,10 +11,10 @@ architecture behaviour of r2_w_ram is type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE; signal ram : RAM_TYPE := ( - 0 => x"00000010", - 1 => x"00110010", - 2 => x"000000FF", - 3 => x"00AB00BA", + 0 => x"00000000", + 1 => x"00000001", + 2 => x"00000002", + 3 => x"00000003", others=> x"00000000"); begin diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd index f033885..c9de81a 100644 --- a/cpu/src/r_w_ram_b.vhd +++ b/cpu/src/r_w_ram_b.vhd @@ -11,7 +11,7 @@ architecture behaviour of r_w_ram is type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE; signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000", - 1 => "11100000000000001001000000000000", + 1 => "11110000000000001001000000000000", 2 => "11100000000010001001000000000000", 3 => "11100001000110010111011001101100", others => x"00000000"); -- 2.25.1