From 5d59b3cc12c9e042cdc1c5b3b538f589e94d34c8 Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Sun, 19 Dec 2010 17:46:48 +0100 Subject: [PATCH] =?utf8?q?modelsim=20lauff=C3=A4hig?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit --- cpu/sim/testcore.do | 2 +- cpu/src/writeback_stage_b.vhd | 10 +++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do index 0b2647e..a6f7143 100644 --- a/cpu/sim/testcore.do +++ b/cpu/sim/testcore.do @@ -8,9 +8,9 @@ vcom -work work ../src/r2_w_ram.vhd vcom -work work ../src/r2_w_ram_b.vhd vcom -work work ../src/rom.vhd vcom -work work ../src/rom_b.vhd +vcom -work work ../src/extension_pkg.vhd vcom -work work ../src/common_pkg.vhd vcom -work work ../src/core_pkg.vhd -vcom -work work ../src/extension_pkg.vhd vcom -work work ../src/extension_uart_pkg.vhd vcom -work work ../src/extension_uart.vhd vcom -work work ../src/extension_uart_b.vhd diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd index 1a59b1e..a1b08b8 100755 --- a/cpu/src/writeback_stage_b.vhd +++ b/cpu/src/writeback_stage_b.vhd @@ -103,6 +103,7 @@ end process; shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred, write_en, ram_data) variable byte_en : byte_en_t; +variable address_val : std_logic_vector(1 downto 0); begin wb_reg_nxt.address <= address; wb_reg_nxt.dmem_en <= dmem_en; @@ -114,15 +115,18 @@ begin wb_reg_nxt.data <= ram_data; byte_en := (others => '0'); + address_val := address(BYTEADDR-1 downto 0); if dmem_en = '1' then if hword = '1' then - case address(BYTEADDR-1 downto 0) is +-- case address(BYTEADDR-1 downto 0) is + case address_val is when "00" => byte_en(1 downto 0) := "11"; when "10" => byte_en(3 downto 2) := "11"; when others => null; end case; elsif byte_s = '1' then - case address(BYTEADDR-1 downto 0) is +-- case address(BYTEADDR-1 downto 0) is + case address_val is when "00" => byte_en(0) := '1'; when "01" => byte_en(1) := '1'; when "10" => byte_en(2) := '1'; @@ -236,7 +240,7 @@ addr_de_mult: process(wb_reg, wb_reg_nxt, ram_data, sel_nxt, ext_uart_out, ext_g variable wr_en, enable : std_logic; -- these are all registered variable byte_en : byte_en_t; -- if a module needs the nxt signals it has to manually select them variable addr : ext_addr_t; -- for example the data memory, because it already has input registers -variable addrid : ext_addrid_t; +variable addrid : std_logic_vector(27 downto 0);--ext_addrid_t; variable data : gp_register_t; begin -- 2.25.1