From 5a4ac62bf9b6861c8098e4fb9d28e19016766d04 Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Wed, 12 Jan 2011 19:41:37 +0100 Subject: [PATCH] soft reset --- cpu/src/core_pkg.vhd | 1 + cpu/src/core_top.vhd | 2 +- cpu/src/core_top_c2de1.vhd | 38 ++++++++++++---------------------- cpu/src/extension_uart_pkg.vhd | 4 ++-- cpu/src/fetch_stage.vhd | 1 + cpu/src/fetch_stage_b.vhd | 13 ++++++++---- progs/Makefile | 5 +++++ 7 files changed, 32 insertions(+), 32 deletions(-) diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd index bc45ecd..87cfcc6 100644 --- a/cpu/src/core_pkg.vhd +++ b/cpu/src/core_pkg.vhd @@ -20,6 +20,7 @@ package core_pkg is --System inputs clk : in std_logic; reset : in std_logic; + s_reset : in std_logic; --Data inputs jump_result : in instruction_addr_t; diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd index 13d8263..452db69 100644 --- a/cpu/src/core_top.vhd +++ b/cpu/src/core_top.vhd @@ -86,7 +86,7 @@ begin --System inputs clk => sys_clk, --: in std_logic; reset => sys_res_n, --: in std_logic; - + s_reset => '1', --Data inputs jump_result => jump_result_pin, --: in instruction_addr_t; prediction_result => prediction_result_pin, --: in instruction_addr_t; diff --git a/cpu/src/core_top_c2de1.vhd b/cpu/src/core_top_c2de1.vhd index b741001..adecfee 100644 --- a/cpu/src/core_top_c2de1.vhd +++ b/cpu/src/core_top_c2de1.vhd @@ -11,6 +11,7 @@ entity core_top_c2de1 is port( --System input pins sys_res : in std_logic; + soft_res : in std_logic; sys_clk : in std_logic; -- result : out gp_register_t; -- reg_wr_data : out gp_register_t @@ -62,7 +63,8 @@ architecture behav of core_top_c2de1 is signal nop_pin : std_logic; signal sync : std_logic_vector(1 to SYNC_STAGES); - signal sys_res_n : std_logic; + signal sync2 : std_logic_vector(1 to SYNC_STAGES); + signal sys_res_n, soft_res_n : std_logic; signal int_req : interrupt_t; @@ -84,6 +86,7 @@ begin --System inputs clk => sys_clk, --: in std_logic; reset => sys_res_n, --: in std_logic; + s_reset => soft_res_n, --Data inputs jump_result => jump_result_pin, --: in instruction_addr_t; @@ -112,7 +115,7 @@ begin port map ( --System inputs clk => sys_clk, --: in std_logic; - reset => sys_res_n, -- : in std_logic; + reset => sys_res_n and soft_res_n, -- : in std_logic; --Data inputs instruction => instruction_pin, --: in instruction_word_t; @@ -130,39 +133,18 @@ begin exec_st : execute_stage generic map(RESET_VALUE) - port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, + port map(sys_clk, sys_res_n and soft_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin); - --- vers_nxt.result <= result_pin; --- vers_nxt.result_addr <= result_addr_pin; --- vers_nxt.address <= addr_pin; --- vers_nxt.ram_data <= data_pin; --- vers_nxt.alu_jmp <= alu_jump_pin; --- vers_nxt.br_pred <= brpr_pin; --- vers_nxt.write_en <= wr_en_pin; --- vers_nxt.dmem_en <= dmem_pin; --- vers_nxt.dmem_write_en <= dmem_wr_en_pin; --- vers_nxt.hword <= hword_pin; --- vers_nxt.byte_s <= byte_s_pin; writeback_st : writeback_stage generic map(RESET_VALUE, '1', "altera") - port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, + port map(sys_clk, sys_res_n and soft_res_n, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req); --- writeback_st : writeback_stage --- generic map(RESET_VALUE, '1', "altera") --- port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, --- vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s, --- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, --- -- instruction memory program port :D --- new_im_data, im_addr, im_data, --- sseg0, sseg1, sseg2, sseg3, int_req); --- syn: process(sys_clk, sys_res) @@ -177,12 +159,18 @@ begin for i in 2 to SYNC_STAGES loop sync(i) <= sync(i - 1); end loop; + + sync2(1) <= soft_res; + for i in 2 to SYNC_STAGES loop + sync2(i) <= sync2(i - 1); + end loop; end if; end process; sys_res_n <= sync(SYNC_STAGES); +soft_res_n <= sync2(SYNC_STAGES); nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin); jump_result <= prog_cnt_pin; --jump_result_pin; diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd index a7f14d9..6f6580b 100644 --- a/cpu/src/extension_uart_pkg.vhd +++ b/cpu/src/extension_uart_pkg.vhd @@ -22,8 +22,8 @@ subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0); --constant CLK_FREQ_MHZ : real := 33.33; --constant BAUD_RATE : integer := 115200; --constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5); --- constant CLK_PER_BAUD : integer := 434; -constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud + constant CLK_PER_BAUD : integer := 434; +-- constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud -- constant CLK_PER_BAUD : integer := 50; -- @modelsim component extension_uart is diff --git a/cpu/src/fetch_stage.vhd b/cpu/src/fetch_stage.vhd index cefd8e9..c23189c 100644 --- a/cpu/src/fetch_stage.vhd +++ b/cpu/src/fetch_stage.vhd @@ -18,6 +18,7 @@ entity fetch_stage is --System inputs clk : in std_logic; reset : in std_logic; + s_reset : in std_logic; --Data inputs jump_result : in instruction_addr_t; diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd index fb0e7fd..f01bad8 100644 --- a/cpu/src/fetch_stage_b.vhd +++ b/cpu/src/fetch_stage_b.vhd @@ -52,22 +52,27 @@ begin if (reset = RESET_VALUE) then instr_r_addr <= (others => '0'); - rom_ram <= ROM_USE; + rom_ram <= ROM_USE; led2 <= '0'; elsif rising_edge(clk) then instr_r_addr <= instr_r_addr_nxt; rom_ram <= rom_ram_nxt; - led2 <= rom_ram_nxt; + led2 <= rom_ram; --rom_ram_nxt; end if; end process; -asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req) +asyn: process(reset, s_reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req) variable instr_pc : instruction_addr_t; begin rom_ram_nxt <= rom_ram; - + + if (s_reset = RESET_VALUE) then + rom_ram_nxt <= RAM_USE; + instr_r_addr_nxt <= (others => '0'); + end if; + case rom_ram is when ROM_USE => instruction <= instr_rd_data_rom; diff --git a/progs/Makefile b/progs/Makefile index 8053fc5..92c3c9e 100644 --- a/progs/Makefile +++ b/progs/Makefile @@ -2,13 +2,18 @@ SHELL := bash HN := $(shell hostname) TILABHOSTS := $(shell echo ti{1..41}) apps1 +STEFANHOST := $(shell echo ubuntu) apps1 ifeq ($(findstring $(HN), $(TILABHOSTS)), $(HN)) DPROGFLAGS := -d /dev/ttyS0 -b 9600 +else +ifeq ($(findstring $(HN), $(STEFANHOST)), $(HN)) +DPROGFLAGS := -d /dev/ttyS0 -b 115200 else # TODO: passt das fuern stefan auch? DPROGFLAGS := -d /dev/ttyUSB0 -b 115200 endif +endif all: fibmmem.prog -- 2.25.1