From 59b64378e94e8db6225a30c8d62e7472c66f675b Mon Sep 17 00:00:00 2001 From: Manfred Date: Thu, 6 Jan 2011 16:22:32 +0100 Subject: [PATCH] instruction memory progammer: is in and works in simulations --- cpu/sim/testcore1.do | 31 ++---- cpu/src/core_pkg.vhd | 6 + cpu/src/extension_imp.vhd | 31 ++++++ cpu/src/extension_imp_b.vhd | 204 ++++++++++++++++++++++++++++++++++ cpu/src/extension_imp_pkg.vhd | 34 ++++++ cpu/src/extension_pkg.vhd | 1 + cpu/src/fetch_stage.vhd | 4 + cpu/src/fetch_stage_b.vhd | 6 +- cpu/src/pipeline_tb.vhd | 8 +- cpu/src/rom_b.vhd | 40 ++++--- cpu/src/writeback_stage.vhd | 4 + cpu/src/writeback_stage_b.vhd | 43 ++++++- 12 files changed, 371 insertions(+), 41 deletions(-) create mode 100644 cpu/src/extension_imp.vhd create mode 100644 cpu/src/extension_imp_b.vhd create mode 100644 cpu/src/extension_imp_pkg.vhd diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do index f6b51b9..c781ad4 100644 --- a/cpu/sim/testcore1.do +++ b/cpu/sim/testcore1.do @@ -39,7 +39,13 @@ vcom -work work ../src/extension.vhd vcom -work work ../src/extension_b.vhd +vcom -work work ../src/extension_imp_pkg.vhd +vcom -work work ../src/extension_imp.vhd +vcom -work work ../src/extension_imp_b.vhd +vcom -work work ../src/extension_7seg_pkg.vhd +vcom -work work ../src/extension_7seg.vhd +vcom -work work ../src/extension_7seg_b.vhd vcom -work work ../src/extension_uart_pkg.vhd vcom -work work ../src/rs232_tx.vhd @@ -124,25 +130,12 @@ add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writebac add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/ram_data -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_uart -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg_nxt -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co_nxt -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w2_uart_config -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w3_uart_send -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w4_uart_receive -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/data_out -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/new_tx_data -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/bus_tx -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/tx_data -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/tx_rdy -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/tx_rdy_int -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/sys_clk -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/cnt -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/stop_bit -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bd_rate +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/im_addr +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/im_data +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/new_im_data_out +add wave -group test -radix hexadecimal /pipeline_tb/fetch_st/im_addr +add wave -group test -radix hexadecimal /pipeline_tb/fetch_st/im_data +add wave -group test -radix hexadecimal /pipeline_tb/fetch_st/new_im_data_in run 5000 ns diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd index b9f9eca..dc6f8ce 100644 --- a/cpu/src/core_pkg.vhd +++ b/cpu/src/core_pkg.vhd @@ -27,6 +27,9 @@ package core_pkg is branch_prediction_bit : in std_logic; alu_jump_bit : in std_logic; int_req : in interrupt_t; + new_im_data_in : in std_logic; + im_addr : in gp_register_t; + im_data : in gp_register_t; --Data outputs instruction : out instruction_word_t; @@ -148,6 +151,9 @@ package core_pkg is -- same here bus_tx : out std_logic; bus_rx : in std_logic; + new_im_data_out : out std_logic; + im_addr : out gp_register_t; + im_data : out gp_register_t; sseg0 : out std_logic_vector(0 to 6); sseg1 : out std_logic_vector(0 to 6); diff --git a/cpu/src/extension_imp.vhd b/cpu/src/extension_imp.vhd new file mode 100644 index 0000000..b6840e7 --- /dev/null +++ b/cpu/src/extension_imp.vhd @@ -0,0 +1,31 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.common_pkg.all; +use work.extension_pkg.all; +use work.extension_imp_pkg.all; + + +entity extension_imp is + + generic ( + -- active reset value + RESET_VALUE : std_logic + ); + port( + --System inputs + clk : in std_logic; + reset : in std_logic; + -- general extension interface + ext_reg : in extmod_rec; + data_out : out gp_register_t; + -- Input + + -- Ouput + im_addr : out gp_register_t; + im_data : out gp_register_t; + new_im_data_out : out std_logic + ); + +end extension_imp; diff --git a/cpu/src/extension_imp_b.vhd b/cpu/src/extension_imp_b.vhd new file mode 100644 index 0000000..28a2a7a --- /dev/null +++ b/cpu/src/extension_imp_b.vhd @@ -0,0 +1,204 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use work.common_pkg.all; +use work.core_pkg.all; + + +use work.mem_pkg.all; +use work.extension_pkg.all; +use work.extension_imp_pkg.all; + +architecture behav of extension_imp is + +signal w1_st_co, w1_st_co_nxt, w2_im_addr, w2_im_addr_nxt, w3_im_data, w3_im_data_nxt, w4_im_notused, w4_im_notused_nxt : gp_register_t; +signal new_im_data, new_im_data_nxt: std_logic; + +begin + + +syn : process (clk, reset) +begin + if (reset = RESET_VALUE) then + w1_st_co <= (others=>'0'); + w2_im_addr(31 downto 16) <= (others=>'0'); + -- todo mit einer konstante versehen + w2_im_addr(15 downto 0) <= x"0004"; + w3_im_data <= (others=>'0'); + w4_im_notused <= (others=>'0'); + --im only + new_im_data <= '0'; + + + elsif rising_edge(clk) then + w1_st_co <= w1_st_co_nxt; + w2_im_addr <= w2_im_addr_nxt; + w3_im_data <= w3_im_data_nxt; + w4_im_notused <= w4_im_notused_nxt; + --im only + new_im_data <= new_im_data_nxt; + + end if; +end process syn; + +-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------ + +gwriten : process (ext_reg,w1_st_co,w2_im_addr,w3_im_data,w4_im_notused) + +variable tmp_data : gp_register_t; + +begin + + w1_st_co_nxt <= w1_st_co; + w2_im_addr_nxt <= w2_im_addr; + w3_im_data_nxt <= w3_im_data; + w4_im_notused_nxt <= w4_im_notused; + + if ext_reg.sel = '1' and ext_reg.wr_en = '1' then + tmp_data := (others =>'0'); + if ext_reg.byte_en(0) = '1' then + tmp_data(byte_t'range) :=ext_reg.data(byte_t'range); + end if; + if ext_reg.byte_en(1) = '1' then + tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length); + end if; + if ext_reg.byte_en(2) = '1' then + tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length); + end if; + if ext_reg.byte_en(3) = '1' then + tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length); + end if; + + case ext_reg.addr(1 downto 0) is + when "00" => + w1_st_co_nxt <= tmp_data; + when "01" => + -- -1 wegen increment des addr registers + tmp_data := tmp_data - '1'; + w2_im_addr_nxt <= tmp_data; + when "10" => + w1_st_co_nxt(16) <= '1'; -- busy flag set + w2_im_addr_nxt <= w2_im_addr + '1'; + w3_im_data_nxt <= tmp_data; + when "11" => + --w4_im_notused_nxt <= tmp_data; sollte nur gelesen werden + when others => null; + end case; + end if; + +end process gwriten; + +gread : process (clk,ext_reg,w1_st_co,w2_im_addr,w3_im_data,w4_im_notused) + +variable tmp_data : gp_register_t; + +begin + if ext_reg.sel = '1' and ext_reg.wr_en = '0' then + case ext_reg.addr(1 downto 0) is + when "00" => + tmp_data := (others =>'0'); + if ext_reg.byte_en(0) = '1' then + tmp_data(byte_t'range) := w1_st_co(byte_t'range); + end if; + if ext_reg.byte_en(1) = '1' then + tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length); + end if; + if ext_reg.byte_en(2) = '1' then + tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length); + end if; + if ext_reg.byte_en(3) = '1' then + tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length); + end if; + data_out <= tmp_data; + when "01" => + tmp_data := (others =>'0'); + if ext_reg.byte_en(0) = '1' then + tmp_data(byte_t'range) := w2_im_addr(byte_t'range); + end if; + if ext_reg.byte_en(1) = '1' then + tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_im_addr((2*byte_t'length-1) downto byte_t'length); + end if; + if ext_reg.byte_en(2) = '1' then + tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_im_addr((3*byte_t'length-1) downto 2*byte_t'length); + end if; + if ext_reg.byte_en(3) = '1' then + tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_im_addr((4*byte_t'length-1) downto 3*byte_t'length); + end if; + data_out <= tmp_data; + when "10" => + tmp_data := (others =>'0'); + if ext_reg.byte_en(0) = '1' then + tmp_data(byte_t'range) := w3_im_data(byte_t'range); + end if; + if ext_reg.byte_en(1) = '1' then + tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_im_data((2*byte_t'length-1) downto byte_t'length); + end if; + if ext_reg.byte_en(2) = '1' then + tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_im_data((3*byte_t'length-1) downto 2*byte_t'length); + end if; + if ext_reg.byte_en(3) = '1' then + tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_im_data((4*byte_t'length-1) downto 3*byte_t'length); + end if; + data_out <= tmp_data; + when "11" => + tmp_data := (others =>'0'); + if ext_reg.byte_en(0) = '1' then + tmp_data(byte_t'range) := w4_im_notused(byte_t'range); + end if; + if ext_reg.byte_en(1) = '1' then + tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_im_notused((2*byte_t'length-1) downto byte_t'length); + end if; + if ext_reg.byte_en(2) = '1' then + tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_im_notused((3*byte_t'length-1) downto 2*byte_t'length); + end if; + if ext_reg.byte_en(3) = '1' then + tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_im_notused((4*byte_t'length-1) downto 3*byte_t'length); + end if; + data_out <= tmp_data; + when others => null; + end case; + else + data_out <= (others=>'0'); + end if; +end process gread; + + +-------------------------- LESEN UND SCHREIBEN ENDE --------------------------------------------------------------- + +-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------ + +dataprocess : process (ext_reg) + + +begin +new_im_data_nxt <= '0'; +if ext_reg.sel = '1' and ext_reg.wr_en = '1' then + case ext_reg.addr(1 downto 0) is + when "00" => + + when "01" => + + when "10" => + new_im_data_nxt <= '1'; + when "11" => + + when others => null; + end case; + end if; + +end process dataprocess; +-- asyncrone verarbeitung +im_addr <= w2_im_addr; +im_data <= w3_im_data; +new_im_data_out <= new_im_data; + + + + +-------------------------- INTERNE VERARBEITUNG ENDE -------------------------------------------------------------- + +end behav; + diff --git a/cpu/src/extension_imp_pkg.vhd b/cpu/src/extension_imp_pkg.vhd new file mode 100644 index 0000000..e58ce67 --- /dev/null +++ b/cpu/src/extension_imp_pkg.vhd @@ -0,0 +1,34 @@ +library IEEE; + +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.common_pkg.all; +use work.extension_pkg.all; + +package extension_imp_pkg is + + component extension_imp is + --some modules won't need all inputs/outputs + generic ( + -- active reset value + RESET_VALUE : std_logic + ); + port( + --System inputs + clk : in std_logic; + reset : in std_logic; + -- general extension interface + ext_reg : in extmod_rec; + data_out : out gp_register_t; + -- Input + + -- Ouput + im_addr : out gp_register_t; + im_data : out gp_register_t; + new_im_data_out : out std_logic + ); + end component extension_imp; + + +end package extension_imp_pkg; diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd index ba3921f..102a181 100644 --- a/cpu/src/extension_pkg.vhd +++ b/cpu/src/extension_pkg.vhd @@ -41,6 +41,7 @@ constant EXT_AC97_ADDR: ext_addrid_t := x"FFFFFFD"; -- constant EXT_UART_ADDR: ext_addrid_t := x"FFFFFFE"; constant EXT_UART_ADDR: ext_addrid_t := x"0000200"; constant EXT_INT_ADDR: ext_addrid_t := x"0000202"; +constant EXT_IMP_ADDR: ext_addrid_t := x"0000203"; constant EXT_GPMP_ADDR: ext_addrid_t := x"FFFFFFF"; component extension_gpm is diff --git a/cpu/src/fetch_stage.vhd b/cpu/src/fetch_stage.vhd index 3165d93..d472d53 100644 --- a/cpu/src/fetch_stage.vhd +++ b/cpu/src/fetch_stage.vhd @@ -25,6 +25,10 @@ entity fetch_stage is branch_prediction_bit : in std_logic; alu_jump_bit : in std_logic; int_req : in interrupt_t; + -- instruction memory program port :D + new_im_data_in : in std_logic; + im_addr : in gp_register_t; + im_data : in gp_register_t; --Data outputs instruction : out instruction_word_t; diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd index 3e30cda..1836f3a 100644 --- a/cpu/src/fetch_stage_b.vhd +++ b/cpu/src/fetch_stage_b.vhd @@ -26,10 +26,10 @@ begin port map ( clk, - instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0), + im_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0), instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0), - instr_we, - instr_wr_data, + new_im_data_in, + im_data, instr_rd_data ); diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd index de276a8..0bdcaca 100644 --- a/cpu/src/pipeline_tb.vhd +++ b/cpu/src/pipeline_tb.vhd @@ -61,6 +61,9 @@ architecture behavior of pipeline_tb is signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6); signal int_req_pin : interrupt_t; + signal new_im_data :std_logic; + signal im_addr, im_data : gp_register_t; + begin -- instruction_ram : r_w_ram @@ -95,6 +98,9 @@ begin prediction_result => prediction_result_pin, --: in instruction_addr_t; branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic; alu_jump_bit => alu_jump_bit_pin, --: in std_logic; + new_im_data_in => new_im_data, + im_addr => im_addr, + im_data => im_data, --Data outputs instruction => instruction_pin, --: out instruction_word_t @@ -138,7 +144,7 @@ begin generic map('0', '1') port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, - reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, sseg0, sseg1, sseg2, sseg3, int_req_pin); + reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin); diff --git a/cpu/src/rom_b.vhd b/cpu/src/rom_b.vhd index d7b5da1..d57a959 100644 --- a/cpu/src/rom_b.vhd +++ b/cpu/src/rom_b.vhd @@ -124,23 +124,35 @@ begin -- when "00000001000" => data_out <= x"e7280004"; -- -- when "00000001001" => data_out <= x"eb7ffb81"; - when "0000000" => data_out <= "11101011000000000000010000000010"; - when "0000001" => data_out <= "11101011000000000001000000000110"; - when "0000010" => data_out <= x"eb000008"; + -- when "0000000" => data_out <= "11101011000000000000010000000010"; + -- when "0000001" => data_out <= "11101011000000000001000000000110"; + -- when "0000010" => data_out <= x"eb000008"; - when "0001000" => data_out <= x"ed090058"; - when "0001001" => data_out <= x"ed110060"; - when "0001010" => data_out <= x"ed190080"; - when "0001011" => data_out <= x"ed210120"; - when "0001100" => data_out <= x"ed280018"; - when "0001101" => data_out <= x"e7aa0000"; + -- when "0001000" => data_out <= x"ed090058"; + -- when "0001001" => data_out <= x"ed110060"; + -- when "0001010" => data_out <= x"ed190080"; + -- when "0001011" => data_out <= x"ed210120"; + -- when "0001100" => data_out <= x"ed280018"; + -- when "0001101" => data_out <= x"e7aa0000"; -- when "0100000" => data_out <= x"f7aa0000"; - when "0100001" => data_out <= x"e7390000"; - when "0100010" => data_out <= x"e13b8008"; - when "0100011" => data_out <= x"e7b98000"; - when "0100100" => data_out <= x"e7b88000"; - when "0100101" => data_out <= x"eb000008"; + -- when "0100001" => data_out <= x"e7390000"; + -- when "0100010" => data_out <= x"e13b8008"; + -- when "0100011" => data_out <= x"e7b98000"; + -- when "0100100" => data_out <= x"e7b88000"; + -- when "0100101" => data_out <= x"eb000008"; + + when "0000000" => data_out <= x"eb000281";--br 5;; + when "0000001" => data_out <= "11101011000000000001000000000110"; + when "0000010" => data_out <= x"eb000008"; + +when "0000101" => data_out <= x"ed0101b8";--ldi r0, 0x2037;; +when "0000110" => data_out <= x"ed0901d8";--ldi r1, 0x203b;; +when "0000111" => data_out <= x"ed100020";--ldi r2, 4;; +when "0001000" => data_out <= x"ed180028";--ldi r3, 5;; +when "0001001" => data_out <= x"e7900000";--stw r2, 0(r0);; +when "0001010" => data_out <= x"e7988000";--stw r3, 0(r1);; + when others => data_out <= "11101011000000000000000000000010"; diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd index d4d669c..aacba01 100644 --- a/cpu/src/writeback_stage.vhd +++ b/cpu/src/writeback_stage.vhd @@ -38,6 +38,10 @@ entity writeback_stage is -- hallo stefan mir adden da jetzt mal schnell an uart port :D bus_tx : out std_logic; bus_rx : in std_logic; + -- instruction memory program port :D + new_im_data_out : out std_logic; + im_addr : out gp_register_t; + im_data : out gp_register_t; sseg0 : out std_logic_vector(0 to 6); sseg1 : out std_logic_vector(0 to 6); diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd index a4d30f6..7b57d45 100755 --- a/cpu/src/writeback_stage_b.vhd +++ b/cpu/src/writeback_stage_b.vhd @@ -9,6 +9,7 @@ use work.mem_pkg.all; use work.extension_pkg.all; use work.extension_uart_pkg.all; use work.extension_7seg_pkg.all; +use work.extension_imp_pkg.all; architecture behav of writeback_stage is @@ -17,8 +18,8 @@ signal data_addr : word_t; signal wb_reg, wb_reg_nxt : writeback_rec; -signal ext_uart,ext_timer,ext_gpmp,ext_7seg,ext_int : extmod_rec; -signal ext_uart_out, ext_timer_out, ext_gpmp_out, ext_int_out : gp_register_t; +signal ext_uart,ext_timer,ext_gpmp,ext_7seg,ext_int,ext_imp : extmod_rec; +signal ext_uart_out, ext_timer_out, ext_gpmp_out, ext_int_out,ext_imp_out : gp_register_t; --signal int_req : interrupt_t; signal uart_int : std_logic; @@ -62,6 +63,20 @@ uart : extension_uart bus_tx ); +imp : extension_imp + generic map( + RESET_VALUE + ) + port map( + clk , + reset, + ext_imp, + ext_imp_out, + im_addr, + im_data, + new_im_data_out + ); + sseg : extension_7seg generic map( RESET_VALUE @@ -304,36 +319,56 @@ begin ext_timer.sel <='0'; ext_gpmp.sel <='0'; ext_int.sel <= '0'; + ext_imp.sel <= '0'; ext_uart.wr_en <= wr_en; ext_7seg.wr_en <= wr_en; ext_timer.wr_en <= wr_en; ext_gpmp.wr_en <= wr_en; ext_int.wr_en <= wr_en; + ext_imp.wr_en <= wr_en; ext_uart.byte_en <= byte_en; ext_7seg.byte_en <= byte_en; ext_timer.byte_en <= byte_en; ext_gpmp.byte_en <= byte_en; ext_int.byte_en <= byte_en; + ext_imp.byte_en <= byte_en; ext_uart.addr <= addr; ext_7seg.addr <= addr; ext_timer.addr <= addr; ext_gpmp.addr <= addr; ext_int.addr <= addr; + ext_imp.addr <= addr; ext_uart.data <= data; ext_7seg.data <= data; ext_timer.data <= data; ext_gpmp.data <= data; ext_int.data <= data; + ext_imp.data <= data; -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.- case addrid is when EXT_UART_ADDR => ext_uart.sel <= enable; - ext_anysel <= enable; + ext_anysel <= enable; + +-- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en; +-- ext_uart.data <= ram_data; +-- ext_uart.addr <= wb_reg_nxt.address(31 downto 2); +-- case wb_reg_nxt.address(1 downto 0) is +-- when "00" => ext_uart.byte_en <= "0001"; +-- when "01" => ext_uart.byte_en <= "0010"; +-- when "10" => ext_uart.byte_en <= "0100"; +-- --when "11" => ext_uart.byte_en <= "1000"; +-- when "11" => ext_uart.byte_en <= "1111"; +-- when others => null; +-- end case; + when EXT_IMP_ADDR => + ext_imp.sel <= enable; + ext_anysel <= enable; -- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en; -- ext_uart.data <= ram_data; @@ -349,7 +384,7 @@ begin when EXT_INT_ADDR => ext_int.sel <= enable; - ext_anysel <= enable; + ext_anysel <= enable; -- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en; -- ext_uart.data <= ram_data; -- 2.25.1