From 242611b3e1ce9341601eede06ab6c6e154523e24 Mon Sep 17 00:00:00 2001 From: Martin Perner Date: Thu, 28 Oct 2010 11:39:51 +0200 Subject: [PATCH] isa: todos done flags renamed flag positions changed fixes --- 2_isa/arith.ptex | 10 +++++----- 2_isa/data.ptex | 15 ++++++++++++--- 2_isa/desdis.tex | 2 +- 2_isa/flags.tex | 3 +-- 2_isa/logic.ptex | 20 ++++++++++---------- 2_isa/misc.ptex | 19 ++++++++++++++----- 6 files changed, 43 insertions(+), 26 deletions(-) diff --git a/2_isa/arith.ptex b/2_isa/arith.ptex index 804933b..7d1d1b3 100644 --- a/2_isa/arith.ptex +++ b/2_isa/arith.ptex @@ -1,21 +1,21 @@ ins ('32', 'add', 'Add', '4 | 5 | 4 | 4 | 4 | 9 | 1 | 1', -'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C | SU', +'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C | D', 'Adds register A and register B and saves the result in register Destination', 'is set to the MSB of the result | is set if addition has a carry out | is set if a overflow occurred | is set if the result is zero ', 'add r0, r2, r4 ; add low bytes addc r1, r3, r5 ; add high bytes'); -ins ('32', 'addi', 'Add im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | S | C', +ins ('32', 'addi', 'Add im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | S | C | D', 'Adds register A and immediate and saves the result in register Destination', '','', -'mov rD, rS - addi rD, rS, 0'); +'mov rD, rS - addid rD, rS, 0'); # ins ('32', 'addx', 'Add im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C'); -ins ('32', 'sub', 'Sub', '4 | 5 | 4 | 4 | 4 | 9 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C | SU'); +ins ('32', 'sub', 'Sub', '4 | 5 | 4 | 4 | 4 | 9 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C | D'); -ins ('32', 'subi', 'Sub im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | S | C'); +ins ('32', 'subi', 'Sub im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | S | C | D'); # ins ('32', 'subx', 'Sub im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C'); diff --git a/2_isa/data.ptex b/2_isa/data.ptex index d0d10a1..f765a2d 100644 --- a/2_isa/data.ptex +++ b/2_isa/data.ptex @@ -7,7 +7,7 @@ ins ('32', 'ldw', 'Load word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15 ins ('32', 'ldh', 'Load half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement '); ins ('32', 'ldb', 'Load byte, 8bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement'); -ins ('32', 'ldi', 'Load immediate', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | - | h/l | S '); +ins ('32', 'ldi', 'Load immediate', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | S | h/l | - '); ins ('32', 'stw', 'store word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement '); ins ('32', 'sth', 'store half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement '); @@ -19,8 +19,17 @@ ins ('32', 'stx', 'Store to program space', '4 | 5 | 4 | 4 | 15', 'Conditions | ins ('32', 'stackop', 'pop/push/disc/fetch from/to stack', '4 | 5 | 4 | 2 | 17', 'Conditions | OpCode | Register Destination (not for disc) | Type | - ', -'This operation should not be used direct, instead the aliases pop, push, disc and fetch should be used.'); -plaintext ('\\mbox{}\\\\ \\todo{Type == ??}'); +'This operation should not be used direct, instead the aliases pop, push, disc and fetch should be used. +\\begin{table}[!h] +\\centering +\\begin{tabular}{|c|c|} \\hline +\\textbf{Type} & \\textbf{Bits} \\\\ \hline + pop & 00 \\\\ \hline + disc & 01 \\\\ \hline + fetch & 10 \\\\ \hline + push & 11 \\\\ \hline +\\end{tabular} +\\end{table}'); #ins ('32', 'pop', 'pop from stack', '4 | 5 | 4 | 19', 'Conditions | OpCode | Register Destination | - '); diff --git a/2_isa/desdis.tex b/2_isa/desdis.tex index bc9514c..2f4103e 100644 --- a/2_isa/desdis.tex +++ b/2_isa/desdis.tex @@ -4,5 +4,5 @@ \item Saving the return address of a call onto the stack and not into a link register \item UART and timers are implemented as extension modules, which will allow us to implement additions modules for various functions \item We defined that carry set is the condition below (unsigned lower) - \item We use little endian for encoding our data and program space\todo{hatten wir uns ned auf big endian geeinigt?} + \item We use big endian for encoding our data and program space \end{itemize} diff --git a/2_isa/flags.tex b/2_isa/flags.tex index 5fa1f15..998e1ab 100644 --- a/2_isa/flags.tex +++ b/2_isa/flags.tex @@ -3,7 +3,7 @@ In table~\ref{tab:flags} the flags that can suffix instructions are described. I \begin{longtable}{|c|c|c|}\hline \textbf{flag} & \textbf{function} & \textbf{default value} \\ \hline C & carry & 0 (not set) \\ \hline - SU & Status register update & 1 (set) \\ \hline + D & Status register update disable & 0 (not set) \\ \hline H/L & use high or low 16-bits & L (not set) \\ \hline F & fill unused 16-bits with value of F & 0 (not set)\footnote{this means that andxf must be used, if the not specified 16-bit, should be preserve} \\ \hline S & sign extension & 0 (not set) \\ \hline @@ -12,4 +12,3 @@ In table~\ref{tab:flags} the flags that can suffix instructions are described. I \caption{ISA flag overview} \label{tab:flags} \end{longtable} -\todo{@SU: mit welchem suffix deaktivieren? ``SU'' selbst ist imho verwirrend} diff --git a/2_isa/logic.ptex b/2_isa/logic.ptex index e5c25a3..aa97db8 100644 --- a/2_isa/logic.ptex +++ b/2_isa/logic.ptex @@ -1,28 +1,28 @@ -ins ('32', 'and', 'And', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | SU'); +ins ('32', 'and', 'And', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | D'); # ins ('32', 'andi', 'And im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -'); -ins ('32', 'andx', 'And im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | SU'); +ins ('32', 'andx', 'And im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | D'); -ins ('32', 'or', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | SU'); +ins ('32', 'or', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | D'); # ins ('32', 'ori', 'Or im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -'); -ins ('32', 'orx', 'Or im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | SU'); +ins ('32', 'orx', 'Or im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | D'); -ins ('32', 'xor', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | SU'); +ins ('32', 'xor', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | D'); # ins ('32', 'xori', 'Xor im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -'); -ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | SU', +ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | D', '', '', '', 'not rD - xorxlf rD, rD, 0xFFFF'); -ins ('32', 'lls', 'left shift', '4 | 5 | 4 | 4 | 5 | 8 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | C | SU', +ins ('32', 'l{l,r}s', 'left/right shift', '4 | 5 | 4 | 4 | 5 | 6 | 1 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | l/r | A C | D', '',' | Will change if C is set | | '); -plaintext ('\\mbox{}\\\\ \\todo{lls und lrs zusammenfassen $\rightarrow$ ein bit entscheidet fuer shift nach links oder rechts}'); +#plaintext ('\\mbox{}\\\\ \\todo{lls und lrs zusammenfassen $\rightarrow$ ein bit entscheidet fuer shift nach links oder rechts}'); -ins ('32', 'lrs', 'right shift', '4 | 5 | 4 | 4 | 5 | 7 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | A | C | SU', -'',' | Will change if C is set | | '); +# ins ('32', 'lrs', 'right shift', '4 | 5 | 4 | 4 | 5 | 7 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | A | C | D', +# '',' | Will change if C is set | | '); diff --git a/2_isa/misc.ptex b/2_isa/misc.ptex index 09c5a7f..775d8fb 100644 --- a/2_isa/misc.ptex +++ b/2_isa/misc.ptex @@ -1,9 +1,18 @@ ins ('32', 'branch', 'Branch; jump to pc+imm', '4 | 5 | 16 | 3 | 2 | 1 | 1', 'Conditions | OpCode | Immediate | - | Type | +/- | S', -'This instruction should be used with it\'s aliases branch, call, ret and reti. No flags will be affected by this instructions.'); - -plaintext ('\\mbox{}\\\\ \\todo{Type == ??}'); - -plaintext ('\\mbox{}\\\\ \\todo{branchreg? :-(}'); +'This instruction should be used with it\'s aliases branch, call, ret and reti. No flags will be affected by this instructions. +\\begin{table}[!h] +\\centering +\\begin{tabular}{|c|c|} \\hline +\\textbf{Type} & \\textbf{Bits} \\\\ \hline + branch & 00 \\\\ \hline + call & 01 \\\\ \hline + ret & 10 \\\\ \hline + reti & 11 \\\\ \hline +\\end{tabular} +\\end{table}'); + +ins ('32', 'branchreg', 'Branch; jump to value of reg', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register A | - | Type | +/- | -', +'This instruction should be used with it\'s aliases branchr and callr. No flags will be affected by this instructions. If Type is set to 1, the current value of the programcounter is pushed onto the stack.'); #ins ('32', 'call', 'Call; save pc+4 in stack, jump to pc+imm', '4 | 5 | 16 | 5 | 1 | 1', 'Conditions | OpCode | Immediate | - | +/- | S'); -- 2.25.1