From 0a7c3ba7339003e4918db8ca5c2495c0b9abf941 Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Thu, 20 Jan 2011 11:53:46 +0100 Subject: [PATCH] dt: baudrate an PLL (50MHz) angepasst --- cpu/src/core_top.vhd | 2 +- dt/dt.qpf | 6 +++--- dt/dt.qsf | 3 +-- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd index a8d3bde..531ccd1 100644 --- a/cpu/src/core_top.vhd +++ b/cpu/src/core_top.vhd @@ -174,7 +174,7 @@ begin -- writeback_st : writeback_stage - generic map('0', '1', "altera", 2083) + generic map('0', '1', "altera", 5208) port map(sys_clk, sys_res_n and soft_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, diff --git a/dt/dt.qpf b/dt/dt.qpf index f311d83..6785b58 100644 --- a/dt/dt.qpf +++ b/dt/dt.qpf @@ -18,14 +18,14 @@ # # Quartus II # Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition -# Date created = 15:17:41 January 19, 2011 +# Date created = 11:39:04 January 20, 2011 # # -------------------------------------------------------------------------- # QUARTUS_VERSION = "10.0" -DATE = "15:17:41 January 19, 2011" +DATE = "11:39:04 January 20, 2011" # Revisions -PROJECT_REVISION = "DSE" PROJECT_REVISION = "dt" +PROJECT_REVISION = "DSE" diff --git a/dt/dt.qsf b/dt/dt.qsf index 4f558f7..8135268 100644 --- a/dt/dt.qsf +++ b/dt/dt.qsf @@ -81,7 +81,6 @@ set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -set_global_assignment -name VHDL_FILE ../cpu/src/core_top_c2de1.vhd set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be_b.vhd set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be.vhd set_global_assignment -name VHDL_FILE ../cpu/src/rom.vhd @@ -101,7 +100,6 @@ set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_b.vhd set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram.vhd set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram_b.vhd set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram.vhd -set_global_assignment -name VHDL_FILE ../cpu/src/pipeline_tb.vhd set_global_assignment -name VHDL_FILE ../cpu/src/mem_pkg.vhd set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage_b.vhd set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage.vhd @@ -143,4 +141,5 @@ set_global_assignment -name MISC_FILE /homes/c0725782/calu/dt/dt.dpf set_global_assignment -name VHDL_FILE pll/pll.vhd set_location_assignment PIN_152 -to sys_clk_in + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file -- 2.25.1