From cde0d011bc1b001e7d6bd5b9d3d3678e4cd7e2e7 Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Sun, 19 Dec 2010 18:24:17 +0100 Subject: [PATCH] kleinigkeiten --- cpu/src/r_w_ram_b.vhd | 2 +- cpu/src/writeback_stage_b.vhd | 8 ++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd index e735c20..a120a29 100644 --- a/cpu/src/r_w_ram_b.vhd +++ b/cpu/src/r_w_ram_b.vhd @@ -10,7 +10,7 @@ architecture behaviour of r_w_ram is subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0); type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE; - signal ram : RAM_TYPE; + signal ram : RAM_TYPE := (others => x"00000000"); begin process(clk) diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd index a1b08b8..585e0e2 100755 --- a/cpu/src/writeback_stage_b.vhd +++ b/cpu/src/writeback_stage_b.vhd @@ -192,7 +192,7 @@ end process; -out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel) +out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel, result) variable reg_we_v : std_logic; variable data_out : gp_register_t; begin @@ -222,7 +222,7 @@ begin data_out(4*byte_t'length-1 downto 3*byte_t'length) := (others => '0'); end if; - data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))); + data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length); if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0); @@ -231,6 +231,10 @@ begin regfile_val <= data_out; + if wb_reg.dmem_en = '0' then + regfile_val <= result; + end if; + reg_we <= reg_we_v; end process; -- 2.25.1