From 830d494c7fbbd0591e185378d8cf8085673e6b8c Mon Sep 17 00:00:00 2001 From: Stefan Date: Wed, 10 Nov 2010 17:45:21 +0100 Subject: [PATCH] VHDL Grundkonstrukt --- cpu/src/common_pkg.vhd | 25 ++++++++++ cpu/src/core_pkg.vhd | 87 +++++++++++++++++++++++++++++++++++ cpu/src/decode_stage.vhd | 20 ++++++++ cpu/src/decode_stage_b.vhd | 26 +++++++++++ cpu/src/execute_stage.vhd | 20 ++++++++ cpu/src/execute_stage_b.vhd | 25 ++++++++++ cpu/src/fetch_stage.vhd | 31 +++++++++++++ cpu/src/fetch_stage_b.vhd | 63 +++++++++++++++++++++++++ cpu/src/mem_pkg.vhd | 84 +++++++++++++++++++++++++++++++++ cpu/src/r2_w_ram.vhd | 23 +++++++++ cpu/src/r2_w_ram_b.vhd | 25 ++++++++++ cpu/src/r_w_ram.vhd | 23 +++++++++ cpu/src/r_w_ram_b.vhd | 24 ++++++++++ cpu/src/writeback_stage.vhd | 20 ++++++++ cpu/src/writeback_stage_b.vhd | 25 ++++++++++ 15 files changed, 521 insertions(+) create mode 100644 cpu/src/common_pkg.vhd create mode 100644 cpu/src/core_pkg.vhd create mode 100644 cpu/src/decode_stage.vhd create mode 100644 cpu/src/decode_stage_b.vhd create mode 100644 cpu/src/execute_stage.vhd create mode 100644 cpu/src/execute_stage_b.vhd create mode 100644 cpu/src/fetch_stage.vhd create mode 100644 cpu/src/fetch_stage_b.vhd create mode 100755 cpu/src/mem_pkg.vhd create mode 100755 cpu/src/r2_w_ram.vhd create mode 100755 cpu/src/r2_w_ram_b.vhd create mode 100755 cpu/src/r_w_ram.vhd create mode 100755 cpu/src/r_w_ram_b.vhd create mode 100644 cpu/src/writeback_stage.vhd create mode 100644 cpu/src/writeback_stage_b.vhd diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd new file mode 100644 index 0000000..0bd0be7 --- /dev/null +++ b/cpu/src/common_pkg.vhd @@ -0,0 +1,25 @@ +library IEEE; + +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package common_pkg is + + constant WORD_WIDTH : INTEGER := 32; + constant BYTE_WIDTH : INTEGER := 8; + + constant INSTR_ADDR_WIDTH : INTEGER := 32; + constant PHYS_INSTR_ADDR_WIDTH : INTEGER := 11; + constant REG_ADDR_WIDTH : INTEGER := 4; + constant DATA_ADDR_WIDTH : INTEGER := 32; + constant PHYS_DATA_ADDR_WIDTH : INTEGER := 32; + + subtype instruction_word_t is std_logic_vector(WORD_WIDTH-1 downto 0); + subtype instruction_addr_t is std_logic_vector(INSTR_ADDR_WIDTH-1 downto 0); + + subtype gp_register_t is std_logic_vector(WORD_WIDTH-1 downto 0); + + subtype data_ram_word_t is std_logic_vector(WORD_WIDTH-1 downto 0); + subtype data_ram_addr_t is std_logic_vecotr(DATA_ADDR_WIDTH-1 downto 0); + +end package common_pkg; diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd new file mode 100644 index 0000000..301a517 --- /dev/null +++ b/cpu/src/core_pkg.vhd @@ -0,0 +1,87 @@ +library IEEE; + +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.common_pkg.all; + +package core_pkg is + + component fetch_stage is + generic ( + -- active reset value + RESET_VALUE : std_logic; + -- active logic value + LOGIC_ACT : std_logic; + + ); + port( + --System inputs + clk : in std_logic; + reset : in std_logic; + + --Data inputs + jump_result : in instruction_addr_t; + prediction_result : in instruction_addr_t; + branch_prediction_bit : in std_logic; + alu_jump_bit : in std_logic; + + --Data outputs + instruction : out instruction_word_t + + ); + end component fetch_stage; + + + + component decode_stage is + generic ( + -- active reset value + RESET_VALUE : std_logic; + -- active logic value + LOGIC_ACT : std_logic; + + ); + port( + --System inputs + clk : in std_logic; + reset : in std_logic; + ); + end component decode_stage; + + + + component execute_stage is + generic ( + -- active reset value + RESET_VALUE : std_logic; + -- active logic value + LOGIC_ACT : std_logic; + + ); + port( + --System inputs + clk : in std_logic; + reset : in std_logic; + ); + end component execute_stage; + + + + component writeback_stage is + generic ( + -- active reset value + RESET_VALUE : std_logic; + -- active logic value + LOGIC_ACT : std_logic; + + ); + port( + --System inputs + clk : in std_logic; + reset : in std_logic; + ); + end component writeback_stage; + + +end package core_pkg; diff --git a/cpu/src/decode_stage.vhd b/cpu/src/decode_stage.vhd new file mode 100644 index 0000000..4be1c3e --- /dev/null +++ b/cpu/src/decode_stage.vhd @@ -0,0 +1,20 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity decode_stage is + + generic ( + -- active reset value + RESET_VALUE : std_logic; + -- active logic value + LOGIC_ACT : std_logic; + + ); + port( + --System inputs + clk : in std_logic; + reset : in std_logic; + ); + +end decode_stage; diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd new file mode 100644 index 0000000..48761ea --- /dev/null +++ b/cpu/src/decode_stage_b.vhd @@ -0,0 +1,26 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.core_pkg.all; +use work.common_pkg.all; + +architecture behav of decode_stage is + + +begin + +syn: process(sys_clk, reset) + +begin + + if (reset = RESET_VALUE) then + + elsif rising_edge(sys_clk) then + + end if; + +end process; + +end behav; + diff --git a/cpu/src/execute_stage.vhd b/cpu/src/execute_stage.vhd new file mode 100644 index 0000000..d69fdc0 --- /dev/null +++ b/cpu/src/execute_stage.vhd @@ -0,0 +1,20 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity execute_stage is + + generic ( + -- active reset value + RESET_VALUE : std_logic; + -- active logic value + LOGIC_ACT : std_logic; + + ); + port( + --System inputs + clk : in std_logic; + reset : in std_logic; + ); + +end execute_stage; diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd new file mode 100644 index 0000000..6b6b621 --- /dev/null +++ b/cpu/src/execute_stage_b.vhd @@ -0,0 +1,25 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.core_pkg.all; + +architecture behav of execute_stage is + + +begin + +syn: process(sys_clk, reset) + +begin + + if (reset = RESET_VALUE) then + + elsif rising_edge(sys_clk) then + + end if; + +end process; + +end behav; + diff --git a/cpu/src/fetch_stage.vhd b/cpu/src/fetch_stage.vhd new file mode 100644 index 0000000..c81e2ac --- /dev/null +++ b/cpu/src/fetch_stage.vhd @@ -0,0 +1,31 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.common_pkg; + +entity fetch_stage is + + generic ( + -- active reset value + RESET_VALUE : std_logic; + -- active logic value + LOGIC_ACT : std_logic; + + ); + port( + --System inputs + clk : in std_logic; + reset : in std_logic; + + --Data inputs + jump_result : in instruction_addr_t; + prediction_result : in instruction_addr_t; + branch_prediction_bit : in std_logic; + alu_jump_bit : in std_logic; + + --Data outputs + instruction : out instruction_word_t + ); + +end fetch_stage; diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd new file mode 100644 index 0000000..2dd8e92 --- /dev/null +++ b/cpu/src/fetch_stage_b.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.core_pkg.all; +use work.common_pkg.all; + +architecture behav of fetch_stage is + +signal instr_w_addr : instruction_addr_t; +signal instr_r_addr : instruction_addr_t; +signal instr_r_addr_nxt : instruction_addr_t; +signal instr_we : std_logic; +signal instr_wr_data : instruction_word_t; +signal instr_rd_data : instruction_word_t; + +begin + + instruction_ram : r_w_ram + generic map ( + PHYS_INSTR_ADDR_WIDTH, + WORD_WIDTH + ) + + port map ( + sys_clk, + instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0), + instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0), + instr_we, + instr_wr_data, + instr_rd_data + ); + +syn: process(sys_clk, reset) + +begin + + if (reset = RESET_VALUE) then + instr_r_addr <= (others => '0'); + elsif rising_edge(sys_clk) then + instr_r_addr <= instr_r_addr_nxt; + end if; + +end process; + + +asyn: process(instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit) + +begin + + instruction <= instr_rd_data; + instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1); + + if (alu_jump_bit = LOGIC_ACT) then + instr_r_addr_nxt <= jump_result; + elsif (branch_prediction_bit = LOGIC_ACT) then + instr_r_addr_nxt <= prediction_result; + end if; + +end process; + +end behav; + diff --git a/cpu/src/mem_pkg.vhd b/cpu/src/mem_pkg.vhd new file mode 100755 index 0000000..cba7fd6 --- /dev/null +++ b/cpu/src/mem_pkg.vhd @@ -0,0 +1,84 @@ +library IEEE; + +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package mem_pkg is + + component r_w_ram is + generic ( + ADDR_WIDTH : integer range 1 to integer'high; + DATA_WIDTH : integer range 1 to integer'high + ); + port( + --System inputs + clk : in std_logic; + --Input + wr_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + + wr_en : in std_logic; + data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); + + --Output + data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) + ); + end component r_w_ram; + + component r2_w_ram is + generic ( + ADDR_WIDTH : integer range 1 to integer'high; + DATA_WIDTH : integer range 1 to integer'high + ); + port( + --System inputs + clk : in std_logic; + --Input + wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0); + + wr_en : in std_logic; + data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); + + --Output + data_out1, data_out2: out std_logic_vector(DATA_WIDTH-1 downto 0) + ); + end component r2_w_ram; + + component rw2_ram is + generic ( + ADDR_WIDTH : integer range 1 to integer'high; + DATA_WIDTH : integer range 1 to integer'high + ); + port( + --System inputs + clk : in std_logic; + --Input + wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0); + + wr_en : in std_logic; + data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); + + --Output + out1, out2: out std_logic_vector(DATA_WIDTH-1 downto 0) + ); + end component rw2_ram; + + component rw_ram is + generic ( + ADDR_WIDTH : integer range 1 to integer'high; + DATA_WIDTH : integer range 1 to integer'high + ); + port( + --System inputs + clk : in std_logic; + --Input + wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0); + + wr_en : in std_logic; + data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); + + --Output + out1, out2: out std_logic_vector(DATA_WIDTH-1 downto 0) + ); + end component rw_ram; + +end package mem_pkg; diff --git a/cpu/src/r2_w_ram.vhd b/cpu/src/r2_w_ram.vhd new file mode 100755 index 0000000..ec15c61 --- /dev/null +++ b/cpu/src/r2_w_ram.vhd @@ -0,0 +1,23 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity r2_w_ram is + generic ( + ADDR_WIDTH : integer range 1 to integer'high; + DATA_WIDTH : integer range 1 to integer'high + ); + port( + --System inputs + clk : in std_logic; + --Input + wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0); + + wr_en : in std_logic; + data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); + + --Output + data_out1, data_out2: out std_logic_vector(DATA_WIDTH-1 downto 0) + ); + +end entity r2_w_ram; diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd new file mode 100755 index 0000000..4350511 --- /dev/null +++ b/cpu/src/r2_w_ram_b.vhd @@ -0,0 +1,25 @@ +library ieee; + +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +architecture behaviour of r2_w_ram is + + subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0); + type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE; + + signal ram : RAM_TYPE; --:= (others=> x"00"); + +begin + process(clk) + begin + if rising_edge(clk) then + data_out1 <= ram(to_integer(UNSIGNED(rd_addr1))); + data_out2 <= ram(to_integer(UNSIGNED(rd_addr2))); + + if wr_en = '1' then + ram(to_integer(UNSIGNED(wr_addr))) <= data_in; + end if; + end if; + end process; +end architecture behaviour; diff --git a/cpu/src/r_w_ram.vhd b/cpu/src/r_w_ram.vhd new file mode 100755 index 0000000..2b63f11 --- /dev/null +++ b/cpu/src/r_w_ram.vhd @@ -0,0 +1,23 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity r_w_ram is + generic ( + ADDR_WIDTH : integer range 1 to integer'high; + DATA_WIDTH : integer range 1 to integer'high + ); + port( + --System inputs + clk : in std_logic; + --Input + wr_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + + wr_en : in std_logic; + data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); + + --Output + data_out : out std_logic_vector(DATA_WIDTH-1 downto 0) + ); + +end entity r_w_ram; diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd new file mode 100755 index 0000000..50c7660 --- /dev/null +++ b/cpu/src/r_w_ram_b.vhd @@ -0,0 +1,24 @@ +library ieee; + +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +architecture behaviour of r_w_ram is + + subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0); + type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE; + + signal ram : RAM_TYPE; --:= (others=> x"00"); + +begin + process(clk) + begin + if rising_edge(clk) then + data_out <= ram(to_integer(UNSIGNED(rd_addr))); + + if wr_en = '1' then + ram(to_integer(UNSIGNED(wr_addr))) <= data_in; + end if; + end if; + end process; +end architecture behaviour; diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd new file mode 100644 index 0000000..965f996 --- /dev/null +++ b/cpu/src/writeback_stage.vhd @@ -0,0 +1,20 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity writeback_stage is + + generic ( + -- active reset value + RESET_VALUE : std_logic; + -- active logic value + LOGIC_ACT : std_logic; + + ); + port( + --System inputs + clk : in std_logic; + reset : in std_logic; + ); + +end writeback_stage; diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd new file mode 100644 index 0000000..4e5fba3 --- /dev/null +++ b/cpu/src/writeback_stage_b.vhd @@ -0,0 +1,25 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.core_pkg.all; + +architecture behav of writeback_stage is + + +begin + +syn: process(sys_clk, reset) + +begin + + if (reset = RESET_VALUE) then + + elsif rising_edge(sys_clk) then + + end if; + +end process; + +end behav; + -- 2.25.1