From 7abf429570db9f476d7a02981358ae872b6a44d5 Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Wed, 1 Dec 2010 23:23:56 +0100 Subject: [PATCH] static branch - getestet, 58MHz lt quartus --- cpu/create_project.tcl | 7 +++++-- cpu/src/core_top.vhd | 7 +++++-- cpu/src/decode_stage_b.vhd | 4 ++-- cpu/src/r_w_ram_b.vhd | 11 +++++++---- cpu/src/writeback_stage_b.vhd | 11 ++++++----- 5 files changed, 25 insertions(+), 15 deletions(-) diff --git a/cpu/create_project.tcl b/cpu/create_project.tcl index 0b13c22..5364415 100755 --- a/cpu/create_project.tcl +++ b/cpu/create_project.tcl @@ -51,6 +51,9 @@ if {$make_assignments} { set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd set_global_assignment -name VHDL_FILE ../src/gpm_pkg.vhd + set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd + set_global_assignment -name VHDL_FILE ../src/extension.vhd + set_global_assignment -name VHDL_FILE ../src/extension_b.vhd set_global_assignment -name VHDL_FILE ../src/exec_op.vhd set_global_assignment -name VHDL_FILE ../src/exec_op/add_op_b.vhd @@ -62,8 +65,8 @@ if {$make_assignments} { set_global_assignment -name VHDL_FILE ../src/alu.vhd set_global_assignment -name VHDL_FILE ../src/alu_b.vhd - set_global_assignment -name VHDL_FILE ../src/gpm.vhd - set_global_assignment -name VHDL_FILE ../src/gpm_b.vhd +# set_global_assignment -name VHDL_FILE ../src/gpm.vhd +# set_global_assignment -name VHDL_FILE ../src/gpm_b.vhd set_global_assignment -name VHDL_FILE ../src/execute_stage.vhd set_global_assignment -name VHDL_FILE ../src/execute_stage_b.vhd diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd index f0e1a4a..bb95789 100644 --- a/cpu/src/core_top.vhd +++ b/cpu/src/core_top.vhd @@ -26,6 +26,7 @@ architecture behav of core_top is signal branch_prediction_bit_pin : std_logic; signal alu_jump_bit_pin : std_logic; signal instruction_pin : instruction_word_t; + signal prog_cnt_pin : instruction_addr_t; signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0); signal reg_wr_data_pin : gp_register_t; @@ -71,7 +72,8 @@ begin alu_jump_bit => alu_jump_bit_pin, --: in std_logic; --Data outputs - instruction => instruction_pin --: out instruction_word_t + instruction => instruction_pin, --: out instruction_word_t + prog_cnt => prog_cnt_pin ); decode_st : decode_stage @@ -89,6 +91,7 @@ begin --Data inputs instruction => instruction_pin, --: in instruction_word_t; + prog_cnt => prog_cnt_pin, reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0); reg_wr_data => reg_wr_data_pin, --: in gp_register_t; reg_we => reg_we_pin, --: in std_logic; @@ -127,7 +130,7 @@ begin --end process; result <= result_pin; - nop_pin <= (alu_jump_bit_pin xor brpr_pin); + nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin); jump_result <= jump_result_pin; diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd index dc5e389..60cc287 100644 --- a/cpu/src/decode_stage_b.vhd +++ b/cpu/src/decode_stage_b.vhd @@ -109,7 +109,7 @@ end process; -- fills output register -to_next: process(instr_spl) +to_next: process(instr_spl, prog_cnt) begin dec_op_inst_nxt.condition <= instr_spl.predicates; @@ -180,7 +180,7 @@ end process; -- async process: calculates branch prediction -br_pred: process(instr_spl) +br_pred: process(instr_spl, prog_cnt) begin diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd index 585dc92..023b1b7 100644 --- a/cpu/src/r_w_ram_b.vhd +++ b/cpu/src/r_w_ram_b.vhd @@ -12,7 +12,8 @@ architecture behaviour of r_w_ram is -- r0 = 0, r1 = 1, r2 = 3, r3 = A - signal ram : RAM_TYPE := ( + signal ram : RAM_TYPE := ( 0 => "11101101000000000000000000000000", -- r0 = 0 + 1 => "11101101000010000000000000111000", -- r1 = 7 2 => "11101101000100000000000000101000", -- r2 = 5 3 => "11101101000110000000000000100000", -- r3 = 4 @@ -20,15 +21,17 @@ architecture behaviour of r_w_ram is 5 => "11100010001010100000100000000000", -- r5 = r4 and r1 6 => "11100001000000000000000000001000", -- r0 = r0 + 1 - 7 => "11101100100000000000000000010000", -- cmpi r0 , 2 => 2-2 => 1001 + 7 => "11101100100000000000000000011000", -- cmpi r0 , 2 8 => "00001011011111111111110010000011", -- jump -7 9 => "11101011000000000000000010000010", -- jump +1 10 => "11100111101010100000000000000001", -- stw r5,r4,1 - 11 => "11101100001000100000000000000000", --cmp r4 , r4 => 2-2 => 1001 + 11 => "11101100001000100000000000000000", -- cmp r4 , r4 => 2-2 => 1001 + + 12 => "11101011000000000000000000000010", -- jump +0 - 0 => "11101101000000000000000000000000", -- r0 = 0 + others => x"F0000000"); diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd index 3573680..862c1d3 100644 --- a/cpu/src/writeback_stage_b.vhd +++ b/cpu/src/writeback_stage_b.vhd @@ -95,11 +95,12 @@ begin end if; end if; - jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en); + --jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en); + jump <= (alu_jmp xor br_pred);-- and (write_en or wb_reg.dmem_en); - if alu_jmp = '0' and br_pred = '1' and write_en = '0' then - jump <= '1'; - end if; +-- if alu_jmp = '0' and br_pred = '1' and write_en = '0' then +-- jump <= '1'; +-- end if; jump_addr <= result; if ((alu_jmp and wb_reg.dmem_en) = '1') then @@ -128,7 +129,7 @@ begin end process; -addr_de_mult: process(wb_reg_nxt.address) +addr_de_mult: process(wb_reg_nxt.address, ram_data, wb_reg) begin -- 2.25.1