From dd5693dc4dfe9339d3301009e42a8f01fa5a6873 Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Mon, 20 Dec 2010 23:26:07 +0100 Subject: [PATCH] small bugfix in wb-stage --- cpu/create_project.tcl | 2 + cpu/cyc1.tcl | 135 ++++++++++++++++++++++++ cpu/de1_cyclone_fmax.tcl | 157 ++++++++++++++++++++++++++++ cpu/src/alu_b.vhd | 1 + cpu/src/fetch_stage_b.vhd | 2 +- cpu/src/rom_b.vhd | 36 +++++-- cpu/test.s | 11 ++ dt/dt.drc.rpt | 213 +++++++++++++++++++------------------- dt/dt.qsf | 18 +++- 9 files changed, 459 insertions(+), 116 deletions(-) create mode 100644 cpu/cyc1.tcl create mode 100644 cpu/de1_cyclone_fmax.tcl create mode 100644 cpu/test.s diff --git a/cpu/create_project.tcl b/cpu/create_project.tcl index 367e4a2..c2dc47b 100755 --- a/cpu/create_project.tcl +++ b/cpu/create_project.tcl @@ -34,6 +34,8 @@ if {$make_assignments} { set_global_assignment -name TOP_LEVEL_ENTITY core_top set_global_assignment -name VHDL_FILE ../src/core_top.vhd set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd + set_global_assignment -name VHDL_FILE ../src/rom.vhd + set_global_assignment -name VHDL_FILE ../src/rom_b.vhd set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd diff --git a/cpu/cyc1.tcl b/cpu/cyc1.tcl new file mode 100644 index 0000000..a0951bb --- /dev/null +++ b/cpu/cyc1.tcl @@ -0,0 +1,135 @@ +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Quartus II: Generate Tcl File for Project +# File: cyc1.tcl +# Generated on: Mon Dec 20 23:24:35 2010 + +# Load Quartus II Tcl Project package +package require ::quartus::project + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "dt"]} { + puts "Project dt is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists dt]} { + project_open -revision dt dt + } else { + project_new -revision dt dt + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + set_global_assignment -name FAMILY Cyclone + set_global_assignment -name DEVICE EP1C12Q240C8 + set_global_assignment -name TOP_LEVEL_ENTITY core_top + set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1" + set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:08:54 DECEMBER 16, 2010" + set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1" + set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 + set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + set_global_assignment -name USE_CONFIGURATION_DEVICE ON + set_global_assignment -name GENERATE_RBF_FILE ON + set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF + set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" + set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS" + set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" + set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" + set_global_assignment -name VHDL_FILE ../cpu/src/rom.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/rom_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_pkg.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx_arc.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx_arc.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/pipeline_tb.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/mem_pkg.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_pkg.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/extension_pkg.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/extension_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/extension.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/exec_op.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/decoder_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/decoder.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/core_top.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/core_pkg.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/common_pkg.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/alu_pkg.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/alu_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/alu.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/xor_op_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/shift_op_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd + set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd + set_global_assignment -name SMART_RECOMPILE ON + set_global_assignment -name ENABLE_DRC_SETTINGS ON + set_global_assignment -name ENABLE_CLOCK_LATENCY ON + set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON + set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED + set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON + set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON + set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON + set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON + set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM + set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL + set_global_assignment -name FITTER_EFFORT "STANDARD FIT" + set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON + set_global_assignment -name MUX_RESTRUCTURE OFF + set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" + set_location_assignment PIN_42 -to sys_res + set_location_assignment PIN_166 -to bus_tx + set_location_assignment PIN_152 -to sys_clk + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + # Commit assignments + export_assignments + + # Close project + if {$need_to_close_project} { + project_close + } +} diff --git a/cpu/de1_cyclone_fmax.tcl b/cpu/de1_cyclone_fmax.tcl new file mode 100644 index 0000000..2ffbe71 --- /dev/null +++ b/cpu/de1_cyclone_fmax.tcl @@ -0,0 +1,157 @@ +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Quartus II: Generate Tcl File for Project +# File: de1_cyclone_fmax.tcl +# Generated on: Mon Dec 20 19:47:21 2010 + +# Load Quartus II Tcl Project package +package require ::quartus::project + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "de1_cyclone"]} { + puts "Project de1_cyclone is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists de1_cyclone]} { + project_open -revision de1_cyclone de1_cyclone + } else { + project_new -revision de1_cyclone de1_cyclone + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + set_global_assignment -name FAMILY "Cyclone II" + set_global_assignment -name DEVICE EP2C20F484C7 + set_global_assignment -name TOP_LEVEL_ENTITY core_top + set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1" + set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:41:06 DECEMBER 20, 2010" + set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1" + set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)" + set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation + set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga + set_global_assignment -name MISC_FILE de1_cyclone.dpf + set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" + set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" + set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" + set_global_assignment -name VHDL_FILE ../src/core_top.vhd + set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd + set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd + set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd + set_global_assignment -name VHDL_FILE ../src/rom.vhd + set_global_assignment -name VHDL_FILE ../src/rom_b.vhd + set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd + set_global_assignment -name VHDL_FILE ../src/r2_w_ram_b.vhd + set_global_assignment -name VHDL_FILE ../src/common_pkg.vhd + set_global_assignment -name VHDL_FILE ../src/core_pkg.vhd + set_global_assignment -name VHDL_FILE ../src/fetch_stage.vhd + set_global_assignment -name VHDL_FILE ../src/fetch_stage_b.vhd + set_global_assignment -name VHDL_FILE ../src/decoder.vhd + set_global_assignment -name VHDL_FILE ../src/decoder_b.vhd + set_global_assignment -name VHDL_FILE ../src/decode_stage.vhd + set_global_assignment -name VHDL_FILE ../src/decode_stage_b.vhd + set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd + set_global_assignment -name VHDL_FILE ../src/extension_uart_pkg.vhd + set_global_assignment -name VHDL_FILE ../src/extension_uart.vhd + set_global_assignment -name VHDL_FILE ../src/extension_uart_b.vhd + set_global_assignment -name VHDL_FILE ../src/rs232_tx.vhd + set_global_assignment -name VHDL_FILE ../src/rs232_tx_arc.vhd + set_global_assignment -name VHDL_FILE ../src/rs232_rx.vhd + set_global_assignment -name VHDL_FILE ../src/rs232_rx_arc.vhd + set_global_assignment -name VHDL_FILE ../src/extension_7seg_pkg.vhd + set_global_assignment -name VHDL_FILE ../src/extension_7seg.vhd + set_global_assignment -name VHDL_FILE ../src/extension_7seg_b.vhd + set_global_assignment -name VHDL_FILE ../src/alu_pkg.vhd + set_global_assignment -name VHDL_FILE ../src/extension.vhd + set_global_assignment -name VHDL_FILE ../src/extension_b.vhd + set_global_assignment -name VHDL_FILE ../src/exec_op.vhd + set_global_assignment -name VHDL_FILE ../src/exec_op/add_op_b.vhd + set_global_assignment -name VHDL_FILE ../src/exec_op/and_op_b.vhd + set_global_assignment -name VHDL_FILE ../src/exec_op/or_op_b.vhd + set_global_assignment -name VHDL_FILE ../src/exec_op/xor_op_b.vhd + set_global_assignment -name VHDL_FILE ../src/exec_op/shift_op_b.vhd + set_global_assignment -name VHDL_FILE ../src/alu.vhd + set_global_assignment -name VHDL_FILE ../src/alu_b.vhd + set_global_assignment -name VHDL_FILE ../src/execute_stage.vhd + set_global_assignment -name VHDL_FILE ../src/execute_stage_b.vhd + set_global_assignment -name VHDL_FILE ../src/writeback_stage.vhd + set_global_assignment -name VHDL_FILE ../src/writeback_stage_b.vhd + set_global_assignment -name FMAX_REQUIREMENT "80 MHz" -section_id sys_clk + set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" + set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_global_assignment -name SMART_RECOMPILE ON + set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED + set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON + set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON + set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON + set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM + set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL + set_global_assignment -name FITTER_EFFORT "STANDARD FIT" + set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON + set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON + set_global_assignment -name MUX_RESTRUCTURE OFF + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_location_assignment PIN_L1 -to sys_clk + set_location_assignment PIN_R22 -to sys_res + set_location_assignment PIN_G12 -to bus_tx + set_location_assignment PIN_F14 -to bus_rx + set_location_assignment PIN_J2 -to sseg0[0] + set_location_assignment PIN_J1 -to sseg0[1] + set_location_assignment PIN_H2 -to sseg0[2] + set_location_assignment PIN_H1 -to sseg0[3] + set_location_assignment PIN_F2 -to sseg0[4] + set_location_assignment PIN_F1 -to sseg0[5] + set_location_assignment PIN_E2 -to sseg0[6] + set_location_assignment PIN_E1 -to sseg1[0] + set_location_assignment PIN_H6 -to sseg1[1] + set_location_assignment PIN_H5 -to sseg1[2] + set_location_assignment PIN_H4 -to sseg1[3] + set_location_assignment PIN_G3 -to sseg1[4] + set_location_assignment PIN_D2 -to sseg1[5] + set_location_assignment PIN_D1 -to sseg1[6] + set_location_assignment PIN_G5 -to sseg2[0] + set_location_assignment PIN_G6 -to sseg2[1] + set_location_assignment PIN_C2 -to sseg2[2] + set_location_assignment PIN_C1 -to sseg2[3] + set_location_assignment PIN_E3 -to sseg2[4] + set_location_assignment PIN_E4 -to sseg2[5] + set_location_assignment PIN_D3 -to sseg2[6] + set_location_assignment PIN_F4 -to sseg3[0] + set_location_assignment PIN_D5 -to sseg3[1] + set_location_assignment PIN_D6 -to sseg3[2] + set_location_assignment PIN_J4 -to sseg3[3] + set_location_assignment PIN_L8 -to sseg3[4] + set_location_assignment PIN_F3 -to sseg3[5] + set_location_assignment PIN_D4 -to sseg3[6] + set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + # Commit assignments + export_assignments + + # Close project + if {$need_to_close_project} { + project_close + } +} diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd index c9e832e..e19b52d 100755 --- a/cpu/src/alu_b.vhd +++ b/cpu/src/alu_b.vhd @@ -135,6 +135,7 @@ begin result_v.result := right_operand; res_prod := '1'; mem_op := '0'; + addr(DATA_ADDR_WIDTH + 2) <= '0'; end if; if op_detail(ST_OPT) = '1' then mem_en := '1'; diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd index 7409e42..e1faf1f 100644 --- a/cpu/src/fetch_stage_b.vhd +++ b/cpu/src/fetch_stage_b.vhd @@ -17,7 +17,7 @@ signal instr_rd_data : instruction_word_t; begin - instruction_ram : r_w_ram + instruction_ram : r_w_ram --rom generic map ( PHYS_INSTR_ADDR_WIDTH, WORD_WIDTH diff --git a/cpu/src/rom_b.vhd b/cpu/src/rom_b.vhd index e21ddcc..3e054f5 100644 --- a/cpu/src/rom_b.vhd +++ b/cpu/src/rom_b.vhd @@ -65,17 +65,39 @@ begin -- -- when "00000011101" => data_out <= x"ed510058"; -- when "00000011110" => data_out <= x"e7850000"; --- + -- uart echo + +--1;00000000;ed010058;ldi r0, 0x200B;; +--1;00000004;ed090060;ldi r1, 0x200C;; +--1;00000008;ed110080;ldi r2, 0x2010;; +--1;0000000c;e7188000;ldw r3, 0(r1);; +--1;00000010;ec1a0000;cmp r3, r4;; +--1;00000014;1b7ffd81;breq 0;; +--1;00000018;e7980000;stw r3, 0(r0);; +--1;0000001c;e7990000;stw r3, 0(r2);; +--1;00000020;e1218000;addi r4, r3, 0;; +--1;00000024;eb7ffb81;br 0;; when "00000000000" => data_out <= x"ed010058"; when "00000000001" => data_out <= x"ed090060"; - when "00000000010" => data_out <= x"e5860000"; --x"e7188000"; - when "00000000011" => data_out <= x"e5a00000"; --x"ec1a0000"; - when "00000000100" => data_out <= x"1b7ffe01"; - when "00000000101" => data_out <= x"e7980000"; - when "00000000110" => data_out <= x"e1218000"; - when "00000000111" => data_out <= x"eb7ffc81"; + when "00000000010" => data_out <= x"ed110080"; --x"e7188000"; f + when "00000000011" => data_out <= x"e7188000"; --x"ec1a0000"; + when "00000000100" => data_out <= x"ec1a0000"; + when "00000000101" => data_out <= x"1b7ffe01"; + when "00000000110" => data_out <= x"e7990000"; -- f + when "00000000111" => data_out <= x"e7980000"; + when "00000001000" => data_out <= x"e1218000"; + when "00000001001" => data_out <= x"eb7ffb81"; + +-- when "00000000000" => data_out <= x"ed010058"; +-- when "00000000001" => data_out <= x"ed090060"; +-- when "00000000010" => data_out <= x"e7188000"; --x"e7188000"; +-- when "00000000011" => data_out <= x"ec1a0000"; --x"ec1a0000"; +-- when "00000000100" => data_out <= x"1b7ffe01"; +-- when "00000000101" => data_out <= x"e7980000"; +-- when "00000000110" => data_out <= x"e1218000"; +-- when "00000000111" => data_out <= x"eb7ffc81"; when others => data_out <= "11101011000000000000000000000010"; diff --git a/cpu/test.s b/cpu/test.s new file mode 100644 index 0000000..f75e5cf --- /dev/null +++ b/cpu/test.s @@ -0,0 +1,11 @@ +ldi r0, 0x200B;; +ldi r1, 0x200C;; +ldi r2, 0x2010;; +ldw r3, 0(r1);; +cmp r3, r4;; +breq 4;; +stw r3, 0(r0);; +stw r3, 0(r2);; +addi r4, r3, 0;; +br 4;; + diff --git a/dt/dt.drc.rpt b/dt/dt.drc.rpt index c6106ee..cf3bf3c 100644 --- a/dt/dt.drc.rpt +++ b/dt/dt.drc.rpt @@ -1,5 +1,5 @@ Design Assistant report for dt -Mon Dec 20 17:39:01 2010 +Mon Dec 20 23:23:39 2010 Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition @@ -38,7 +38,7 @@ applicable agreement for further details. +-------------------------------------------------------------------------+ ; Design Assistant Summary ; +-----------------------------------+-------------------------------------+ -; Design Assistant Status ; Analyzed - Mon Dec 20 17:39:01 2010 ; +; Design Assistant Status ; Analyzed - Mon Dec 20 23:23:39 2010 ; ; Revision Name ; dt ; ; Top-level Entity Name ; core_top ; ; Family ; Cyclone ; @@ -47,8 +47,8 @@ applicable agreement for further details. ; - Rule S102 ; 12 ; ; Total Medium Violations ; 1 ; ; - Rule R102 ; 1 ; -; Total Information only Violations ; 99 ; -; - Rule T101 ; 49 ; +; Total Information only Violations ; 100 ; +; - Rule T101 ; 50 ; ; - Rule T102 ; 50 ; +-----------------------------------+-------------------------------------+ @@ -106,19 +106,19 @@ applicable agreement for further details. +-----------------------------------------------------------------------------------------------------------------------+---------------------------------------+ ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; execute_stage:exec_st|reg.alu_jump ; ; Synchronous and reset port source node(s) list ; sys_res ; -; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[0] ; +; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[2] ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[1] ; ; Synchronous and reset port source node(s) list ; sys_res ; -; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[2] ; -; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[3] ; ; Synchronous and reset port source node(s) list ; sys_res ; -; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[4] ; +; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[0] ; +; Synchronous and reset port source node(s) list ; sys_res ; +; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[6] ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[5] ; ; Synchronous and reset port source node(s) list ; sys_res ; -; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[6] ; +; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[4] ; ; Synchronous and reset port source node(s) list ; sys_res ; ; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[7] ; ; Synchronous and reset port source node(s) list ; sys_res ; @@ -131,23 +131,23 @@ applicable agreement for further details. +-----------------------------------------------------------------------------------------------------------------------+---------------------------------------+ -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Medium Violations ; -+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+ -; Rule name ; Name ; -+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+ -; Rule R102: External reset signals should be synchronized using two cascaded registers ; sys_res ; -; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[1] ; -; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[2] ; -; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[3] ; -; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[4] ; -; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[5] ; -; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[6] ; -; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[7] ; -; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[8] ; -; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[9] ; -; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[10] ; -+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Medium Violations ; ++---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+ +; Rule name ; Name ; ++---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+ +; Rule R102: External reset signals should be synchronized using two cascaded registers ; sys_res ; +; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[15] ; +; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[31] ; +; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[14] ; +; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[12] ; +; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[13] ; +; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[10] ; +; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[11] ; +; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[8] ; +; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[9] ; +; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[7] ; ++---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -155,105 +155,106 @@ applicable agreement for further details. +------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------+ ; Rule name ; Name ; Fan-Out ; +------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------+ -; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[1]~19 ; 96 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.dmem_en ; 63 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|left_operand[5]~3 ; 53 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; sys_res ; 543 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23 ; 63 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; ~GND ; 208 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a1 ; 33 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|left_operand[5]~3 ; 54 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[1]~19 ; 95 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.dmem_en ; 66 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[0]~25 ; 100 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; sys_clk ; 569 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; sys_res ; 549 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.imm_set ; 65 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[1]~13 ; 42 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 53 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 81 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[1] ; 103 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0 ; 32 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; ~GND ; 208 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16 ; 33 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[2]~0 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[3]~1 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[4]~2 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[5]~3 ; 32 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[6]~4 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[7]~5 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[8]~6 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[9]~7 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[10]~8 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[11]~9 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[12]~10 ; 32 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 60 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[1] ; 109 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|WideOr2~0 ; 42 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23 ; 63 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP ; 56 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 50 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[13] ; 34 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP ; 57 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|WideOr2~0 ; 36 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 59 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|Selector74~2 ; 71 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[13] ; 56 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[3]~22 ; 71 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 78 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[2]~16 ; 74 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_out~2 ; 80 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072 ; 71 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[2]~16 ; 75 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a1 ; 33 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|calc~2 ; 31 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; 51 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 35 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[31]~0 ; 31 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31]~2 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[3] ; 39 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[2] ; 64 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[31]~0 ; 32 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 40 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 39 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; 32 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|calc~2 ; 31 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 33 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 64 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; 33 ; ; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|Selector0~0 ; 35 ; -; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 35 ; -; Rule T102: Top nodes with the highest number of fan-outs ; sys_clk ; 569 ; -; Rule T102: Top nodes with the highest number of fan-outs ; sys_res ; 549 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; sys_clk ; 563 ; +; Rule T102: Top nodes with the highest number of fan-outs ; sys_clk ; 563 ; +; Rule T102: Top nodes with the highest number of fan-outs ; sys_res ; 543 ; ; Rule T102: Top nodes with the highest number of fan-outs ; ~GND ; 208 ; -; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[1] ; 109 ; +; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[1] ; 103 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[0]~25 ; 100 ; -; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[1]~19 ; 96 ; +; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[1]~19 ; 95 ; +; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 81 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_out~2 ; 80 ; -; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 78 ; -; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[2]~16 ; 75 ; +; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[2]~16 ; 74 ; +; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|Selector74~2 ; 71 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[3]~22 ; 71 ; -; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072 ; 71 ; +; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.dmem_en ; 66 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|rtw_rec.imm_set ; 65 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 64 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[2] ; 64 ; -; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.dmem_en ; 63 ; ; Rule T102: Top nodes with the highest number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23 ; 63 ; -; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 60 ; -; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP ; 56 ; -; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|left_operand[5]~3 ; 53 ; +; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 59 ; +; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP ; 57 ; +; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[13] ; 56 ; +; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|left_operand[5]~3 ; 54 ; +; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 53 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; 51 ; -; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 50 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[1]~13 ; 42 ; -; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|WideOr2~0 ; 42 ; -; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 40 ; +; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 39 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[3] ; 39 ; +; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|WideOr2~0 ; 36 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 35 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|Selector0~0 ; 35 ; -; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[13] ; 34 ; -; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16 ; 33 ; +; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 33 ; ; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; 33 ; ; Rule T102: Top nodes with the highest number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a1 ; 33 ; -; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 33 ; -; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31]~2 ; 32 ; -; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[2]~0 ; 32 ; -; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[3]~1 ; 32 ; -; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; 32 ; -; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[7]~5 ; 32 ; -; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[8]~6 ; 32 ; -; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[9]~7 ; 32 ; -; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[4]~2 ; 32 ; -; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ; +; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16 ; 33 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[10]~8 ; 32 ; -; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[11]~9 ; 32 ; +; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[3]~1 ; 32 ; +; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[9]~7 ; 32 ; +; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[7]~5 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[31]~0 ; 32 ; +; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[4]~2 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[5]~3 ; 32 ; +; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31]~2 ; 32 ; +; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0 ; 32 ; +; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[12]~10 ; 32 ; +; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[2]~0 ; 32 ; +; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; 32 ; +; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[6]~4 ; 32 ; +; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[8]~6 ; 32 ; ; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[31]~0 ; 31 ; ; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|calc~2 ; 31 ; -; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|pwr_en~4 ; 30 ; +------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------+ @@ -263,56 +264,54 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II Design Assistant Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition - Info: Processing started: Mon Dec 20 17:38:59 2010 + Info: Processing started: Mon Dec 20 23:23:37 2010 Info: Command: quartus_drc --read_settings_files=off --write_settings_files=off dt -c dt -Critical Warning: Synopsys Design Constraints File file not found: 'dt.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. -Info: No user constrained base clocks found in the design Critical Warning: (High) Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source. Found 12 node(s) related to this rule. Critical Warning: Node "execute_stage:exec_st|reg.alu_jump" - Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[0]" - Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[1]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[2]" + Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[1]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[3]" - Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[4]" - Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[5]" + Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[0]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[6]" + Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[5]" + Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[4]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[7]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[8]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[9]" Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[10]" Warning: (Medium) Rule R102: External reset signals should be synchronized using two cascaded registers. Found 1 node(s) related to this rule. Warning: Node "sys_res" -Info: (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 49 node(s) with highest fan-out. +Info: (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 50 node(s) with highest fan-out. + Info: Node "sys_res" + Info: Node "fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23" + Info: Node "~GND" + Info: Node "fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a1" + Info: Node "execute_stage:exec_st|left_operand[5]~3" Info: Node "execute_stage:exec_st|right_operand[1]~19" Info: Node "writeback_stage:writeback_st|wb_reg.dmem_en" - Info: Node "execute_stage:exec_st|left_operand[5]~3" Info: Node "execute_stage:exec_st|right_operand[0]~25" - Info: Node "sys_clk" - Info: Node "sys_res" Info: Node "decode_stage:decode_st|rtw_rec.imm_set" Info: Node "execute_stage:exec_st|right_operand[1]~13" + Info: Node "decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP" + Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[3]" + Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[1]" Info: Node "decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0" - Info: Node "~GND" Info: Node "decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16" Info: Node "writeback_stage:writeback_st|data_addr[2]~0" Info: Node "writeback_stage:writeback_st|data_addr[3]~1" Info: Node "writeback_stage:writeback_st|data_addr[4]~2" Info: Node "writeback_stage:writeback_st|data_addr[5]~3" + Info: Node "writeback_stage:writeback_st|data_addr[6]~4" Info: Node "writeback_stage:writeback_st|data_addr[7]~5" Info: Node "writeback_stage:writeback_st|data_addr[8]~6" Info: Node "writeback_stage:writeback_st|data_addr[9]~7" Info: Node "writeback_stage:writeback_st|data_addr[10]~8" Info: Node "writeback_stage:writeback_st|data_addr[11]~9" Info: Node "writeback_stage:writeback_st|data_addr[12]~10" - Info: Node "decode_stage:decode_st|dec_op_inst.op_group.LDST_OP" - Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[1]" - Info: Node "execute_stage:exec_st|alu:alu_inst|WideOr2~0" - Info: Node "fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.STACK_OP" - Info: Node "decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP" - Info: Node "writeback_stage:writeback_st|wb_reg.address[13]" - Info: Node "execute_stage:exec_st|right_operand[3]~22" - Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[3]" + Info: Node "execute_stage:exec_st|alu:alu_inst|WideOr2~0" + Info: Node "decode_stage:decode_st|dec_op_inst.op_group.LDST_OP" + Info: Node "execute_stage:exec_st|alu:alu_inst|Selector74~2" Info: Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated. Info: (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out. Info: Node "sys_clk" @@ -321,36 +320,36 @@ Info: (Information) Rule T102: Top nodes with the highest number of fan-outs. (V Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[1]" Info: Node "execute_stage:exec_st|right_operand[0]~25" Info: Node "execute_stage:exec_st|right_operand[1]~19" - Info: Node "writeback_stage:writeback_st|data_out~2" Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[3]" + Info: Node "writeback_stage:writeback_st|data_out~2" Info: Node "execute_stage:exec_st|right_operand[2]~16" + Info: Node "execute_stage:exec_st|alu:alu_inst|Selector74~2" Info: Node "execute_stage:exec_st|right_operand[3]~22" - Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072" + Info: Node "writeback_stage:writeback_st|wb_reg.dmem_en" Info: Node "decode_stage:decode_st|rtw_rec.imm_set" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.OR_OP" Info: Node "writeback_stage:writeback_st|wb_reg.address[2]" - Info: Node "writeback_stage:writeback_st|wb_reg.dmem_en" Info: Node "fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.LDST_OP" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.STACK_OP" + Info: Node "writeback_stage:writeback_st|wb_reg.address[13]" Info: Node "execute_stage:exec_st|left_operand[5]~3" - Info: Node "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP" + Info: Node "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT" Info: Node "execute_stage:exec_st|right_operand[1]~13" - Info: Node "execute_stage:exec_st|alu:alu_inst|WideOr2~0" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP" Info: Node "writeback_stage:writeback_st|wb_reg.address[3]" + Info: Node "execute_stage:exec_st|alu:alu_inst|WideOr2~0" Info: Node "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP" Info: Node "execute_stage:exec_st|alu:alu_inst|Selector0~0" - Info: Node "writeback_stage:writeback_st|wb_reg.address[13]" - Info: Node "decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16" + Info: Node "decode_stage:decode_st|dec_op_inst.op_group.AND_OP" Info: Node "decode_stage:decode_st|dec_op_inst.op_group.XOR_OP" Info: Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated. -Info: Design Assistant information: finished post-fitting analysis of current design -- generated 99 information messages and 13 warning messages -Info: Quartus II Design Assistant was successful. 0 errors, 16 warnings - Info: Peak virtual memory: 195 megabytes - Info: Processing ended: Mon Dec 20 17:39:01 2010 +Info: Design Assistant information: finished post-fitting analysis of current design -- generated 100 information messages and 13 warning messages +Info: Quartus II Design Assistant was successful. 0 errors, 15 warnings + Info: Peak virtual memory: 191 megabytes + Info: Processing ended: Mon Dec 20 23:23:39 2010 Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:02 + Info: Total CPU time (on all processors): 00:00:01 diff --git a/dt/dt.qsf b/dt/dt.qsf index 1fda27f..02febd5 100644 --- a/dt/dt.qsf +++ b/dt/dt.qsf @@ -105,4 +105,20 @@ set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/shift_op_b.vhd set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name ENABLE_DRC_SETTINGS ON +set_global_assignment -name ENABLE_CLOCK_LATENCY ON +set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM +set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name MUX_RESTRUCTURE OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file -- 2.25.1