From 3e9337b7a4d81fb059f90716d7df9aa3bec9d719 Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Sun, 19 Dec 2010 10:11:56 +0100 Subject: [PATCH] version not running! uart synthetisierbar, reg zw. exec und wb eingebaut, forward und jump funktioniert noch nicht!!! --- cpu/src/common_pkg.vhd | 14 ++ cpu/src/core_top.vhd | 48 ++++- cpu/src/execute_stage_b.vhd | 7 + cpu/src/extension_uart_b.vhd | 2 +- cpu/src/extension_uart_pkg.vhd | 4 +- cpu/src/rom_b.vhd | 7 - cpu/src/rs232_rx.vhd | 1 - cpu/src/rs232_rx_arc.vhd | 313 +++++++++++++++++---------------- cpu/src/rs232_tx_arc.vhd | 7 +- cpu/src/writeback_stage_b.vhd | 59 ++++--- 10 files changed, 264 insertions(+), 198 deletions(-) diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd index ec18a20..1e2a42d 100755 --- a/cpu/src/common_pkg.vhd +++ b/cpu/src/common_pkg.vhd @@ -91,6 +91,7 @@ package common_pkg is end record; + type read_through_write_rec is record rtw_reg : gp_register_t; @@ -135,6 +136,19 @@ package common_pkg is byte_s : std_logic; end record; + type exec2wb_rec is record + result : gp_register_t; --reg (alu result or jumpaddr) + result_addr : gp_addr_t; --reg + address : word_t; --ureg + ram_data : word_t; --ureg + alu_jmp : std_logic; --reg + br_pred : std_logic; --reg + write_en : std_logic; --reg (register file) bei jump 1 wenn addr in result + dmem_en : std_logic; --ureg (jump addr in mem or in address) + dmem_write_en : std_logic; --ureg + hword : std_logic; --ureg + byte_s : std_logic; --ureg + end record; function inc(value : in std_logic_vector; constant by : in integer := 1) return std_logic_vector; function log2c(constant value : in integer range 0 to integer'high) return integer; diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd index d81095c..5352332 100644 --- a/cpu/src/core_top.vhd +++ b/cpu/src/core_top.vhd @@ -59,6 +59,7 @@ architecture behav of core_top is signal gpm_out_pin : gp_register_t; signal nop_pin : std_logic; + signal vers, vers_nxt : exec2wb_rec; begin @@ -117,14 +118,54 @@ begin port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin); - writeback_st : writeback_stage + + vers_nxt.result <= result_pin; + vers_nxt.result_addr <= result_addr_pin; + vers_nxt.address <= addr_pin; + vers_nxt.ram_data <= data_pin; + vers_nxt.alu_jmp <= alu_jump_pin; + vers_nxt.br_pred <= brpr_pin; + vers_nxt.write_en <= wr_en_pin; + vers_nxt.dmem_en <= dmem_pin; + vers_nxt.dmem_write_en <= dmem_wr_en_pin; + vers_nxt.hword <= hword_pin; + vers_nxt.byte_s <= byte_s_pin; + +-- writeback_st : writeback_stage +-- generic map('0', '1') +-- port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, +-- wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, +-- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3); +-- + + writeback_st : writeback_stage generic map('0', '1') - port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, - wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, + port map(sys_clk, sys_res, vers.result, vers.result_addr, vers.address, vers.ram_data, vers.alu_jmp, vers.br_pred, + vers.write_en, vers.dmem_en, vers.dmem_write_en, vers.hword, vers.byte_s, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3); +syn: process(sys_clk, sys_res) +begin + + if sys_res = '0' then + vers.result <= (others => '0'); + vers.result_addr <= (others => '0'); + vers.address <= (others => '0'); + vers.ram_data <= (others => '0'); + vers.alu_jmp <= '0'; + vers.br_pred <= '0'; + vers.write_en <= '0'; + vers.dmem_en <= '0'; + vers.dmem_write_en <= '0'; + vers.hword <= '0'; + vers.byte_s <= '0'; + elsif rising_edge(sys_clk) then + vers <= vers_nxt; + end if; + +end process; --init : process(all) @@ -145,4 +186,5 @@ begin -- sys_res <= '1'; -- reg_wr_data <= reg_wr_data_pin; + end behav; diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd index 7221e60..1c4a6bc 100644 --- a/cpu/src/execute_stage_b.vhd +++ b/cpu/src/execute_stage_b.vhd @@ -123,13 +123,20 @@ result_addr <= reg.res_addr; alu_jump <= reg.alu_jump; brpr <= reg.brpr; wr_en <= reg.wr_en; + dmem <= alu_nxt.mem_op; + --dmem <= reg.result(4); + dmem_write_en <= alu_nxt.mem_en; + --dmem_write_en <= reg.result(0); --dmem_write_en <= '1'; + hword <= alu_nxt.hw_op; + --hword <= reg.result(1); + byte_s <= alu_nxt.byte_op; --addr <= alu_nxt.result; diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd index 9f64cf5..97fa9fb 100644 --- a/cpu/src/extension_uart_b.vhd +++ b/cpu/src/extension_uart_b.vhd @@ -83,7 +83,7 @@ end process syn; -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------ -gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int) +gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx) variable tmp_data : gp_register_t; diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd index 60f2ffa..7851222 100644 --- a/cpu/src/extension_uart_pkg.vhd +++ b/cpu/src/extension_uart_pkg.vhd @@ -16,8 +16,8 @@ package extension_uart_pkg is --RS232 constant UART_WIDTH : integer := 8; subtype uart_data is std_logic_vector(UART_WIDTH-1 downto 0); -constant BAUD_RATE_WITH : integer := 16; -subtype baud_rate_l is std_logic_vector(BAUD_RATE_WITH-1 downto 0); +constant BAUD_RATE_WIDTH : integer := 16; +subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0); --CLKs --constant CLK_FREQ_MHZ : real := 33.33; --constant BAUD_RATE : integer := 115200; diff --git a/cpu/src/rom_b.vhd b/cpu/src/rom_b.vhd index d234e43..5204162 100644 --- a/cpu/src/rom_b.vhd +++ b/cpu/src/rom_b.vhd @@ -14,12 +14,6 @@ architecture behaviour of rom is signal rrrr_addr : std_logic_vector(31 downto 0); - signal ram : RAM_TYPE := ( - - - - others => x"F0000000"); - begin process(clk) begin @@ -73,7 +67,6 @@ begin end case; if wr_en = '1' then - ram(to_integer(UNSIGNED(wr_addr))) <= data_in; end if; end if; end process; diff --git a/cpu/src/rs232_rx.vhd b/cpu/src/rs232_rx.vhd index 9254fb9..6f83ceb 100755 --- a/cpu/src/rs232_rx.vhd +++ b/cpu/src/rs232_rx.vhd @@ -12,7 +12,6 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -use IEEE.std_logic_arith.all; use work.common_pkg.all; use work.core_pkg.all; diff --git a/cpu/src/rs232_rx_arc.vhd b/cpu/src/rs232_rx_arc.vhd index 62ff9c6..1bdc472 100755 --- a/cpu/src/rs232_rx_arc.vhd +++ b/cpu/src/rs232_rx_arc.vhd @@ -1,155 +1,158 @@ ---------------------------------------------------------------------------------- --- Filename : rs232_rx_arc.vhd --- ========== --- --- Beschreibung : Empfang von Daten ueber die RS232 Schnittstelle --- ============== --- --- Autoren : Martin Perner, Schwarz Manfred --- ========= ----------------------------------------------------------------------------------- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -use work.common_pkg.all; -use work.core_pkg.all; -use work.extension_uart_pkg.all; - -architecture beh of rs232_rx is - -- definierern der intern verwendeten Signale - type STATE_TYPE is (IDLE, READ_START, READ_BIT, READ_STOP, POST_STOP); - signal state, state_next : STATE_TYPE; - signal bus_rx_last, bus_rx_int, new_rx_data_nxt : std_logic := '0'; - signal cnt, cnt_next : integer := 0; - signal baud_cnt, baud_cnt_next : integer := 0; - signal rx_data_int, rx_data_nxt, rx_data_res_int, rx_data_res_nxt : uart_data; - -begin - -- syncronisierungs Prozess - rs232_rx_syn : process(sys_clk, sys_res_n) - begin - if (sys_res_n = RESET_VALUE) then - -- reset Zustand - state <= IDLE; - cnt <= 0; - rx_data_res_int <= x"00"; - - elsif rising_edge(sys_clk) then - -- sync Zustand, uebernehmen der next-Signale - state <= state_next; - cnt <= cnt_next; - baud_cnt <= baud_cnt_next; - bus_rx_int <= bus_rx_last; - rx_data_int <= rx_data_nxt; - rx_data_res_int <= rx_data_res_nxt; - new_rx_data <= new_rx_data_nxt; - - end if; - end process; - - -- setzen des Ausgangsignals, Rxt-Daten - rx_data <= rx_data_res_int; - - -- Zustandsmaschienen Prozess - rs232_states : process(sys_clk,state,cnt, bus_rx, bus_rx_last, baud_cnt,bus_rx_int,bd_rate) - begin - state_next <= state; -- mal schauen ob des so geht - bus_rx_last <= bus_rx; -- mal schauen ob des so geht - case state is - when IDLE => - -- nach einem Wechsel der rxt-Leitung von 1 auf 0 wird der einlese Vorgang - -- getriggert mithilfe eines Zustandsuebergangs von IDLE auf READ_START - if (bus_rx_last = '0' and bus_rx_int = '1') then - state_next <= READ_START; - end if; - when READ_START => - -- im READ_START Zustand wird eine halbe Bitzeit gewartet. Liegt auf der rxt-Leitung - -- immer noch die 0 an so wird mit deim Lesebvorgang mit einem Zustandswechsel von - -- READ_START nach READ_BIT vorgefahren, wenn eine 1 anliegt wird abgebrochen und - -- wieder nach IDLE gewechselt - if (bus_rx = '0' and baud_cnt = bd_rate/2) then - state_next <= READ_BIT; - elsif (bus_rx = '1' and baud_cnt = bd_rate/2) then - state_next <= IDLE; - end if; - when READ_BIT => - -- hier werden mit Hilfe eines Countersignals 8 Datenbits im Abstand der eingestellten - -- Bitzeit eingelesen und gespeichert. - -- Nach beendigung wird in den Zustand READ_STOP gewechselt. - if (cnt = 7 and baud_cnt = bd_rate) then - state_next <= READ_STOP; - else - state_next <= READ_BIT; - end if; - when READ_STOP => - -- hier wird nur noch auf das Stopbit abgewartet und gelesen um den - -- Lesevorgang koerrekt zu beenden - if baud_cnt = bd_rate and bus_rx = '1' then - state_next <= POST_STOP; - elsif baud_cnt = bd_rate and bus_rx = '0' then - state_next <= IDLE; - end if; - when POST_STOP => - -- hier wird nur noch eine halbe Bitzeit gewartet - if baud_cnt = bd_rate/2 then - state_next <= IDLE; - end if; - end case; - end process; - - -- Ausgabe Logik - rs232_tx_baud : process(state, cnt, bus_rx, baud_cnt, rx_data_int, rx_data_res_int,bad_rate) - begin - -- Signale halten um Latches zu vermeiden - cnt_next <= cnt; - new_rx_data_nxt <= '0'; - baud_cnt_next <= baud_cnt; - rx_data_nxt <= rx_data_int; - rx_data_res_nxt <= rx_data_res_int; - -- Statewechesel wie obenbeschrieben - case state is - when IDLE => - baud_cnt_next <= 0; - when READ_START => - -- baut_cnt zyklenweise erhoehen bis es einer halben Bitzeit entspricht - -- anschliessend zuruecksetzten - baud_cnt_next <= baud_cnt + 1; - if baud_cnt = bd_rate/2 then - baud_cnt_next <= 0; - rx_data_nxt <= x"00"; - end if; - when READ_BIT => - -- baut_cnt zyklenweise erhoehen bis es einer Bitzeit entspricht - -- anschliessend zuruecksetzen - -- Zustand der rxt-Leitung im rx_data_nxt abspeichern - baud_cnt_next <= baud_cnt + 1; - if baud_cnt = bd_rate then - baud_cnt_next <= 0; - cnt_next <= cnt+1; - rx_data_nxt(cnt) <= bus_rx; - end if; - when READ_STOP => - -- baut_cnt zyklenweise erhoehen bis es einer Bitzeit entspricht - -- anschliessend zuruecksetzen - -- Counter reseten - -- Signal fuer neue rx-Daten setzen um die send_logic zu aktivieren - cnt_next <= 0; - baud_cnt_next <= baud_cnt + 1; - if baud_cnt = bd_rate then - baud_cnt_next <= 0; - end if; - when POST_STOP => - --halbe bitzeit wartenr auf counter warten - baud_cnt_next <= baud_cnt + 1; - if baud_cnt = bd_rate/2 then - new_rx_data_nxt <= '1'; - rx_data_res_nxt <= rx_data_int; - baud_cnt_next <= 0; - end if; - end case; - end process; - -end architecture beh; - +--------------------------------------------------------------------------------- +-- Filename : rs232_rx_arc.vhd +-- ========== +-- +-- Beschreibung : Empfang von Daten ueber die RS232 Schnittstelle +-- ============== +-- +-- Autoren : Martin Perner, Schwarz Manfred +-- ========= +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.extension_uart_pkg.all; + +use work.common_pkg.all; +use work.core_pkg.all; + +architecture beh of rs232_rx is + -- definierern der intern verwendeten Signale + type STATE_TYPE is (IDLE, READ_START, READ_BIT, READ_STOP, POST_STOP); + signal state, state_next : STATE_TYPE; + signal bus_rx_last, bus_rx_int, new_rx_data_nxt : std_logic := '0'; + signal cnt, cnt_next : integer := 0; + signal baud_cnt, baud_cnt_next : std_logic_vector(BAUD_RATE_WIDTH-1 downto 0); + signal rx_data_int, rx_data_nxt, rx_data_res_int, rx_data_res_nxt : uart_data; + +begin + -- syncronisierungs Prozess + rs232_rx_syn : process(sys_clk, sys_res_n) + begin + if (sys_res_n = RESET_VALUE) then + -- reset Zustand + state <= IDLE; + cnt <= 0; + rx_data_res_int <= x"00"; + baud_cnt <= (others => '0'); + + elsif rising_edge(sys_clk) then + -- sync Zustand, uebernehmen der next-Signale + state <= state_next; + cnt <= cnt_next; + baud_cnt <= baud_cnt_next; + bus_rx_int <= bus_rx_last; + rx_data_int <= rx_data_nxt; + rx_data_res_int <= rx_data_res_nxt; + new_rx_data <= new_rx_data_nxt; + + end if; + end process; + + -- setzen des Ausgangsignals, Rxt-Daten + rx_data <= rx_data_res_int; + + -- Zustandsmaschienen Prozess + rs232_states : process(sys_clk,state,cnt, bus_rx, bus_rx_last, baud_cnt,bus_rx_int,bd_rate) + begin + state_next <= state; -- mal schauen ob des so geht + bus_rx_last <= bus_rx; -- mal schauen ob des so geht + case state is + when IDLE => + -- nach einem Wechsel der rxt-Leitung von 1 auf 0 wird der einlese Vorgang + -- getriggert mithilfe eines Zustandsuebergangs von IDLE auf READ_START + if (bus_rx_last = '0' and bus_rx_int = '1') then + state_next <= READ_START; + end if; + when READ_START => + -- im READ_START Zustand wird eine halbe Bitzeit gewartet. Liegt auf der rxt-Leitung + -- immer noch die 0 an so wird mit deim Lesebvorgang mit einem Zustandswechsel von + -- READ_START nach READ_BIT vorgefahren, wenn eine 1 anliegt wird abgebrochen und + -- wieder nach IDLE gewechselt + + if (bus_rx = '0' and baud_cnt(BAUD_RATE_WIDTH-2 downto 0) = bd_rate(BAUD_RATE_WIDTH-1 downto 1)) then + state_next <= READ_BIT; + elsif (bus_rx = '1' and baud_cnt(BAUD_RATE_WIDTH-2 downto 0) = bd_rate(BAUD_RATE_WIDTH-1 downto 1)) then + state_next <= IDLE; + end if; + when READ_BIT => + -- hier werden mit Hilfe eines Countersignals 8 Datenbits im Abstand der eingestellten + -- Bitzeit eingelesen und gespeichert. + -- Nach beendigung wird in den Zustand READ_STOP gewechselt. + if (cnt = 7 and baud_cnt = bd_rate) then + state_next <= READ_STOP; + else + state_next <= READ_BIT; + end if; + when READ_STOP => + -- hier wird nur noch auf das Stopbit abgewartet und gelesen um den + -- Lesevorgang koerrekt zu beenden + if baud_cnt = bd_rate and bus_rx = '1' then + state_next <= POST_STOP; + elsif baud_cnt = bd_rate and bus_rx = '0' then + state_next <= IDLE; + end if; + when POST_STOP => + -- hier wird nur noch eine halbe Bitzeit gewartet + if baud_cnt(BAUD_RATE_WIDTH-2 downto 0) = bd_rate(BAUD_RATE_WIDTH-1 downto 1) then + state_next <= IDLE; + end if; + end case; + end process; + + -- Ausgabe Logik + rs232_rx_baud : process(state, cnt, bus_rx, baud_cnt, rx_data_int, rx_data_res_int, bd_rate) + begin + -- Signale halten um Latches zu vermeiden + cnt_next <= cnt; + new_rx_data_nxt <= '0'; + baud_cnt_next <= baud_cnt; + rx_data_nxt <= rx_data_int; + rx_data_res_nxt <= rx_data_res_int; + -- Statewechesel wie obenbeschrieben + case state is + when IDLE => + baud_cnt_next <= (others =>'0'); --0; + when READ_START => + -- baut_cnt zyklenweise erhoehen bis es einer halben Bitzeit entspricht + -- anschliessend zuruecksetzten + baud_cnt_next <= std_logic_vector(unsigned(baud_cnt) + 1); + if baud_cnt(BAUD_RATE_WIDTH-2 downto 0) = bd_rate(BAUD_RATE_WIDTH-1 downto 1) then + baud_cnt_next <= (others => '0'); + rx_data_nxt <= x"00"; + end if; + when READ_BIT => + -- baut_cnt zyklenweise erhoehen bis es einer Bitzeit entspricht + -- anschliessend zuruecksetzen + -- Zustand der rxt-Leitung im rx_data_nxt abspeichern + baud_cnt_next <= std_logic_vector(unsigned(baud_cnt) + 1); + if baud_cnt = bd_rate then + baud_cnt_next <= (others => '0'); + cnt_next <= cnt+1; + rx_data_nxt(cnt) <= bus_rx; + end if; + when READ_STOP => + -- baut_cnt zyklenweise erhoehen bis es einer Bitzeit entspricht + -- anschliessend zuruecksetzen + -- Counter reseten + -- Signal fuer neue rx-Daten setzen um die send_logic zu aktivieren + cnt_next <= 0; + baud_cnt_next <= std_logic_vector(unsigned(baud_cnt) + 1); + if baud_cnt = bd_rate then + baud_cnt_next <= (others => '0'); + end if; + when POST_STOP => + --halbe bitzeit wartenr auf counter warten + baud_cnt_next <= baud_cnt + 1; + if baud_cnt(BAUD_RATE_WIDTH-2 downto 0) = bd_rate(BAUD_RATE_WIDTH-1 downto 1) then + new_rx_data_nxt <= '1'; + rx_data_res_nxt <= rx_data_int; + baud_cnt_next <= (others => '0'); + end if; + end case; + end process; + +end architecture beh; + diff --git a/cpu/src/rs232_tx_arc.vhd b/cpu/src/rs232_tx_arc.vhd index 43d862b..9b5a582 100755 --- a/cpu/src/rs232_tx_arc.vhd +++ b/cpu/src/rs232_tx_arc.vhd @@ -37,6 +37,7 @@ begin state <= IDLE; idle_sig <= '0'; bus_tx_int <= '1'; + baud_cnt <= 0; elsif rising_edge(sys_clk) then -- sync Zustand, uebernehmen der next-Signale baud_cnt <= baud_cnt_next; @@ -69,7 +70,7 @@ begin end process; -- Ausgabe Logik - rs232_tx_baud : process(sys_clk, sys_res_n, state, baud_cnt, cnt, tx_data, bus_tx_int,stop_bit) + rs232_tx_baud : process(sys_clk, sys_res_n, state, baud_cnt, cnt, tx_data, bus_tx_int,stop_bit, bd_rate) begin -- Solang idle_sig auf 0 ist wird im SEND Zustand verblieben idle_sig_next <= '0'; @@ -99,14 +100,14 @@ begin when 9 => -- counter = 9 => Stopbit versenden bus_tx_nxt <= '1'; - -- stop_bit 0 heißt 1 stop bit + -- stop_bit 0 heit 1 stop bit if stop_bit = '0' then cnt_next <= 0; idle_sig_next <= '1'; end if; when 10 => bus_tx_nxt <= '1'; - -- stop_bit 1 heißt 2 stop bits + -- stop_bit 1 heit 2 stop bits if stop_bit = '1' then cnt_next <= 0; -- Signalisieren dass der Sendevorgang beendet ist diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd index 8c13049..6f2c9c4 100644 --- a/cpu/src/writeback_stage_b.vhd +++ b/cpu/src/writeback_stage_b.vhd @@ -21,7 +21,7 @@ signal ext_uart,ext_timer,ext_gpmp,ext_7seg : extmod_rec; signal sel_nxt, dmem_we, bus_rx :std_logic; - +signal calc_mem_res : gp_register_t; begin @@ -104,25 +104,25 @@ begin wb_reg_nxt.hword <= hword; wb_reg_nxt.byte_s <= byte_s; - regfile_val <= result; --(others => '0'); + calc_mem_res <= result; --(others => '0'); if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then -- ram read operation --alu_jmp = '0' and - regfile_val <= data_ram_read; + calc_mem_res <= data_ram_read; if (wb_reg.hword = '1') then - regfile_val <= (others => '0'); + calc_mem_res <= (others => '0'); if (wb_reg.address(1) = '1') then - regfile_val(15 downto 0) <= data_ram_read(31 downto 16); + calc_mem_res(15 downto 0) <= data_ram_read(31 downto 16); else - regfile_val(15 downto 0) <= data_ram_read(15 downto 0); + calc_mem_res(15 downto 0) <= data_ram_read(15 downto 0); end if; end if; if (wb_reg.byte_s = '1') then - regfile_val <= (others => '0'); + calc_mem_res <= (others => '0'); case wb_reg.address(1 downto 0) is - when "00" => regfile_val(7 downto 0) <= data_ram_read(7 downto 0); - when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8); - when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16); - when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24); + when "00" => calc_mem_res(7 downto 0) <= data_ram_read(7 downto 0); + when "01" => calc_mem_res(7 downto 0) <= data_ram_read(15 downto 8); + when "10" => calc_mem_res(7 downto 0) <= data_ram_read(23 downto 16); + when "11" => calc_mem_res(7 downto 0) <= data_ram_read(31 downto 24); when others => null; end case; end if; @@ -159,7 +159,7 @@ end process; -out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt) +out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res) begin reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp); @@ -172,12 +172,19 @@ begin data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0); dmem_we <= wb_reg_nxt.dmem_write_en; end if; + + regfile_val <= calc_mem_res; + + if (wb_reg.address(31 downto 4) = EXT_UART_ADDR) then + regfile_val <= data_ram_read_ext; + end if; end process; -addr_de_mult: process(wb_reg_nxt.address, ram_data, wb_reg,sel_nxt,wb_reg_nxt.dmem_write_en) +addr_de_mult: process(wb_reg_nxt, ram_data, wb_reg,sel_nxt) begin + ext_uart.sel <='0'; ext_uart.wr_en <= wb_reg_nxt.dmem_write_en; ext_uart.byte_en <= (others => '0'); @@ -203,19 +210,19 @@ begin ext_gpmp.addr <= (others => '0'); -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.- case wb_reg_nxt.address(31 downto 4) is - when EXT_UART_ADDR => - ext_uart.sel <='1'; - ext_uart.wr_en <= wb_reg_nxt.dmem_write_en; - ext_uart.data <= ram_data; - ext_uart.addr <= wb_reg_nxt.address(31 downto 2); - case wb_reg_nxt.address(1 downto 0) is - when "00" => ext_uart.byte_en <= "0001"; - when "01" => ext_uart.byte_en <= "0010"; - when "10" => ext_uart.byte_en <= "0100"; - --when "11" => ext_uart.byte_en <= "1000"; - when "11" => ext_uart.byte_en <= "1111"; - when others => null; - end case; +-- when EXT_UART_ADDR => +-- ext_uart.sel <='1'; +-- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en; +-- ext_uart.data <= ram_data; +-- ext_uart.addr <= wb_reg_nxt.address(31 downto 2); +-- case wb_reg_nxt.address(1 downto 0) is +-- when "00" => ext_uart.byte_en <= "0001"; +-- when "01" => ext_uart.byte_en <= "0010"; +-- when "10" => ext_uart.byte_en <= "0100"; +-- --when "11" => ext_uart.byte_en <= "1000"; +-- when "11" => ext_uart.byte_en <= "1111"; +-- when others => null; +-- end case; when EXT_7SEG_ADDR => ext_7seg.sel <='1'; -- 2.25.1