From 2d98d2f7b3eaa3afc1cc264725b2596184f1e6e3 Mon Sep 17 00:00:00 2001 From: Manfred Date: Thu, 16 Dec 2010 14:19:56 +0100 Subject: [PATCH] uart : es sendet !!!! --- cpu/sim/testcore1.do | 17 +++ cpu/src/extension_pkg.vhd | 3 +- cpu/src/extension_uart.vhd | 1 + cpu/src/extension_uart_b.vhd | 188 ++++++++++++++++----------------- cpu/src/extension_uart_pkg.vhd | 50 +++------ cpu/src/r_w_ram_b.vhd | 64 ++++++----- cpu/src/rs232_tx.vhd | 6 +- cpu/src/rs232_tx_arc.vhd | 14 ++- cpu/src/writeback_stage_b.vhd | 35 ++++-- 9 files changed, 206 insertions(+), 172 deletions(-) diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do index 0126674..e9eaf93 100644 --- a/cpu/sim/testcore1.do +++ b/cpu/sim/testcore1.do @@ -119,5 +119,22 @@ add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writebac add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_uart +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co_nxt +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w2_uart_config +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w3_uart_send +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w4_uart_receive +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/data_out +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/new_tx_data +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/bus_tx +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/tx_data +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/tx_rdy +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/tx_rdy_int +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/sys_clk +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/cnt +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/stop_bit +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bd_rate + run 5000 ns diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd index ba4aec5..7be5162 100644 --- a/cpu/src/extension_pkg.vhd +++ b/cpu/src/extension_pkg.vhd @@ -38,7 +38,8 @@ constant EXT_7SEG_ADDR: ext_addrid_t := x"FFFFFFA"; constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB"; constant EXT_TIMER_ADDR: ext_addrid_t := x"FFFFFFC"; constant EXT_AC97_ADDR: ext_addrid_t := x"FFFFFFD"; -constant EXT_UART_ADDR: ext_addrid_t := x"FFFFFFE"; +--constant EXT_UART_ADDR: ext_addrid_t := x"FFFFFFE"; +constant EXT_UART_ADDR: ext_addrid_t := x"0000000"; constant EXT_GPMP_ADDR: ext_addrid_t := x"FFFFFFF"; component extension_gpm is diff --git a/cpu/src/extension_uart.vhd b/cpu/src/extension_uart.vhd index 9a31d1d..368f218 100644 --- a/cpu/src/extension_uart.vhd +++ b/cpu/src/extension_uart.vhd @@ -3,6 +3,7 @@ use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.common_pkg.all; +use work.extension_pkg.all; use work.extension_uart_pkg.all; diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd index 471a9c4..95e761b 100644 --- a/cpu/src/extension_uart_b.vhd +++ b/cpu/src/extension_uart_b.vhd @@ -6,18 +6,22 @@ use work.common_pkg.all; use work.core_pkg.all; use work.mem_pkg.all; +use work.extension_pkg.all; use work.extension_uart_pkg.all; architecture behav of extension_uart is -signal int_rec,int_rec_nxt : extmod_rec; -signal w1_st_co, w1_st_co_nxt, w2_wewillsee, w2_wewillsee_nxt, w3_wewillsee, w3_wewillsee_nxt, w4_wewillsee, w4_wewillsee_nxt : gp_register_t; -signal new_tx_data, tx_busy : std_logic; +signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t; +signal new_wb_data, new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic; +signal bd_rate : baud_rate_l; begin rs232_tx_inst : rs232_tx +generic map( + RESET_VALUE + ) port map( --System inputs clk, @@ -28,8 +32,10 @@ port map( --From/to sendlogic new_tx_data, - w3_wewillsee(byte_t'range), - tx_busy + w3_uart_send(byte_t'range), + tx_rdy, + bd_rate, + w1_st_co(0) ); @@ -39,28 +45,67 @@ port map( syn : process (clk, reset) begin if (reset = RESET_VALUE) then - int_rec.sel <= '0'; - int_rec.wr_en <= '0'; - int_rec.byte_en <= (others=>'0'); - int_rec.data <= (others=>'0'); - int_rec.addr <= (others=>'0'); - - - elsif rising_edge(clk) then - int_rec <= int_rec_nxt; - - + w1_st_co <= (others=>'0'); + w2_uart_config <= (others=>'0'); + w3_uart_send <= (others=>'0'); + w4_uart_receive <= (others=>'0'); + + + elsif rising_edge(clk) then + w1_st_co <= w1_st_co_nxt; + w2_uart_config <= w2_uart_config_nxt; + w3_uart_send <= w3_uart_send_nxt; + w4_uart_receive <= w4_uart_receive_nxt; + new_tx_data <= new_tx_data_nxt; + tx_rdy_int <= tx_rdy; end if; end process syn; -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------ -gwriten : process (ext_reg) +gwriten : process (ext_reg,tx_rdy) + +variable tmp_data : gp_register_t; begin if ext_reg.sel = '1' and ext_reg.wr_en = '1' then - int_rec_nxt <= ext_reg; + tmp_data := (others =>'0'); + if ext_reg.byte_en(0) = '1' then + tmp_data(byte_t'range) :=ext_reg.data(byte_t'range); + end if; + if ext_reg.byte_en(1) = '1' then + tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length); + end if; + if ext_reg.byte_en(2) = '1' then + tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length); + end if; + if ext_reg.byte_en(3) = '1' then + tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length); + end if; + + case ext_reg.addr(1 downto 0) is + when "00" => + w1_st_co_nxt <= tmp_data; + when "01" => + w2_uart_config_nxt <= tmp_data; + when "10" => + w1_st_co_nxt(16) <= '1'; -- busy flag set + w3_uart_send_nxt <= tmp_data; + when "11" => + w4_uart_receive_nxt <= tmp_data; + when others => null; + end case; + else + w1_st_co_nxt <= w1_st_co; + w2_uart_config_nxt <= w2_uart_config; + w3_uart_send_nxt <= w3_uart_send; + w4_uart_receive_nxt <= w4_uart_receive; + end if; + + if tx_rdy = '1' and tx_rdy_int = '0' then + w1_st_co_nxt(16) <= '0'; -- busy flag reset end if; + end process gwriten; gread : process (clk,ext_reg) @@ -88,46 +133,46 @@ begin when "01" => tmp_data := (others =>'0'); if ext_reg.byte_en(0) = '1' then - tmp_data(byte_t'range) := w2_wewillsee(byte_t'range); + tmp_data(byte_t'range) := w2_uart_config(byte_t'range); end if; if ext_reg.byte_en(1) = '1' then - tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_wewillsee((2*byte_t'length-1) downto byte_t'length); + tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length); end if; if ext_reg.byte_en(2) = '1' then - tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_wewillsee((3*byte_t'length-1) downto 2*byte_t'length); + tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length); end if; if ext_reg.byte_en(3) = '1' then - tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_wewillsee((4*byte_t'length-1) downto 3*byte_t'length); + tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length); end if; data_out <= tmp_data; when "10" => tmp_data := (others =>'0'); if ext_reg.byte_en(0) = '1' then - tmp_data(byte_t'range) := w3_wewillsee(byte_t'range); + tmp_data(byte_t'range) := w3_uart_send(byte_t'range); end if; if ext_reg.byte_en(1) = '1' then - tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_wewillsee((2*byte_t'length-1) downto byte_t'length); + tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length); end if; if ext_reg.byte_en(2) = '1' then - tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_wewillsee((3*byte_t'length-1) downto 2*byte_t'length); + tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length); end if; if ext_reg.byte_en(3) = '1' then - tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_wewillsee((4*byte_t'length-1) downto 3*byte_t'length); + tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length); end if; data_out <= tmp_data; when "11" => tmp_data := (others =>'0'); if ext_reg.byte_en(0) = '1' then - tmp_data(byte_t'range) := w4_wewillsee(byte_t'range); + tmp_data(byte_t'range) := w4_uart_receive(byte_t'range); end if; if ext_reg.byte_en(1) = '1' then - tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_wewillsee((2*byte_t'length-1) downto byte_t'length); + tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length); end if; if ext_reg.byte_en(2) = '1' then - tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_wewillsee((3*byte_t'length-1) downto 2*byte_t'length); + tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length); end if; if ext_reg.byte_en(3) = '1' then - tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_wewillsee((4*byte_t'length-1) downto 3*byte_t'length); + tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length); end if; data_out <= tmp_data; when others => null; @@ -137,81 +182,34 @@ begin end if; end process gread; -proc_data : process (clk,int_rec) -variable tmp_data : gp_register_t; +-------------------------- LESEN UND SCHREIBEN ENDE --------------------------------------------------------------- + +-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------ + +dataprocess : process (ext_reg,tx_rdy) + begin - case int_rec.addr(1 downto 0) is + + new_tx_data_nxt <= '0'; + bd_rate <= w2_uart_config(15 downto 0); + + if ext_reg.sel = '1' and ext_reg.wr_en = '1' then + case ext_reg.addr(1 downto 0) is when "00" => - tmp_data := (others =>'0'); - if int_rec.byte_en(0) = '1' then - tmp_data(byte_t'range) :=int_rec.data(byte_t'range); - end if; - if int_rec.byte_en(1) = '1' then - tmp_data((2*byte_t'length-1) downto byte_t'length) := int_rec.data((2*byte_t'length-1) downto byte_t'length); - end if; - if int_rec.byte_en(2) = '1' then - tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := int_rec.data((3*byte_t'length-1) downto 2*byte_t'length); - end if; - if int_rec.byte_en(3) = '1' then - tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := int_rec.data((4*byte_t'length-1) downto 3*byte_t'length); - end if; - w1_st_co_nxt <= tmp_data; + when "01" => - tmp_data := (others =>'0'); - if int_rec.byte_en(0) = '1' then - tmp_data(byte_t'range) := int_rec.data(byte_t'range); - end if; - if int_rec.byte_en(1) = '1' then - tmp_data((2*byte_t'length-1) downto byte_t'length) := int_rec.data((2*byte_t'length-1) downto byte_t'length); - end if; - if int_rec.byte_en(2) = '1' then - tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := int_rec.data((3*byte_t'length-1) downto 2*byte_t'length); - end if; - if int_rec.byte_en(3) = '1' then - tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := int_rec.data((4*byte_t'length-1) downto 3*byte_t'length); - end if; - w2_wewillsee_nxt <= tmp_data; + when "10" => - tmp_data := (others =>'0'); - if int_rec.byte_en(0) = '1' then - tmp_data(byte_t'range) :=int_rec.data(byte_t'range); - end if; - if int_rec.byte_en(1) = '1' then - tmp_data((2*byte_t'length-1) downto byte_t'length) := int_rec.data((2*byte_t'length-1) downto byte_t'length); - end if; - if int_rec.byte_en(2) = '1' then - tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := int_rec.data((3*byte_t'length-1) downto 2*byte_t'length); - end if; - if int_rec.byte_en(3) = '1' then - tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := int_rec.data((4*byte_t'length-1) downto 3*byte_t'length); - end if; - w3_wewillsee_nxt <= tmp_data; + new_tx_data_nxt <= '1'; when "11" => - tmp_data := (others =>'0'); - if int_rec.byte_en(0) = '1' then - tmp_data(byte_t'range) := w4_wewillsee(byte_t'range); - end if; - if int_rec.byte_en(1) = '1' then - tmp_data((2*byte_t'length-1) downto byte_t'length) := int_rec.data((2*byte_t'length-1) downto byte_t'length); - end if; - if int_rec.byte_en(2) = '1' then - tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := int_rec.data((3*byte_t'length-1) downto 2*byte_t'length); - end if; - if int_rec.byte_en(3) = '1' then - tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := int_rec.data((4*byte_t'length-1) downto 3*byte_t'length); - end if; - w4_wewillsee_nxt <= tmp_data; + when others => null; end case; -end process proc_data; - --------------------------- LESEN UND SCHREIBEN ENDE --------------------------------------------------------------- - --------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------ - + end if; +end process dataprocess; diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd index fb839ff..604a060 100644 --- a/cpu/src/extension_uart_pkg.vhd +++ b/cpu/src/extension_uart_pkg.vhd @@ -4,44 +4,20 @@ use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.common_pkg.all; - +use work.extension_pkg.all; package extension_uart_pkg is -constant EXTWORDL : integer := log2c(4); -constant BYTEADDR : integer := log2c(4); -constant PCOUNT : integer := 3; -constant EXTWORDS : integer := EXTWORDL + BYTEADDR; - -subtype ext_addrid_t is std_logic_vector(gp_register_t'high - EXTWORDS downto 0); -subtype ext_addr_t is std_logic_vector((gp_register_t'high-BYTEADDR) downto 0); -subtype paddr_t is std_logic_vector(log2c(PCOUNT)-1 downto 0); - - type extmod_rec is record - sel : std_logic; - wr_en : std_logic; - byte_en : std_logic_vector(gp_register_t'length/byte_t'length-1 downto 0); - data : gp_register_t; - addr : ext_addr_t; - end record; - - -type status_rec is record - zero : std_logic; - oflo : std_logic; - sign : std_logic; - carry : std_logic; -end record; - -constant EXT_7SEG_ADDR: ext_addrid_t := x"FFFFFFA"; -constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB"; -constant EXT_TIMER_ADDR: ext_addrid_t := x"FFFFFFC"; -constant EXT_AC97_ADDR: ext_addrid_t := x"FFFFFFD"; -constant EXT_UART_ADDR: ext_addrid_t := x"FFFFFFE"; -constant EXT_GPMP_ADDR: ext_addrid_t := x"FFFFFFF"; + + + + + --RS232 constant UART_WIDTH : integer := 8; subtype uart_data is std_logic_vector(UART_WIDTH-1 downto 0); +constant BAUD_RATE_WITH : integer := 16; +subtype baud_rate_l is std_logic_vector(BAUD_RATE_WITH-1 downto 0); --CLKs constant CLK_FREQ_MHZ : real := 33.33; constant BAUD_RATE : integer := 115200; @@ -68,6 +44,10 @@ constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAU end component extension_uart; component rs232_tx is + generic ( + -- active reset value + RESET_VALUE : std_logic + ); port( --System inputs @@ -80,8 +60,10 @@ component rs232_tx is --From/to sendlogic new_tx_data : in std_logic; tx_data : in uart_data; - tx_rdy : out std_logic - ); + tx_rdy : out std_logic; + bd_rate : in baud_rate_l; + stop_bit : in std_logic +); end component rs232_tx; end package extension_uart_pkg; diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd index fa01d93..c995c10 100644 --- a/cpu/src/r_w_ram_b.vhd +++ b/cpu/src/r_w_ram_b.vhd @@ -14,22 +14,32 @@ architecture behaviour of r_w_ram is signal ram : RAM_TYPE := ( - 0 => "11101101000000000000000000000000", --ldi - 1 => "11101101001000000000000000000000", --ldi - 2 => "11100111101000000000000000000000", --stw - 3 => "11100001000000000000000000100001", - 4 => "11101100100000000000001100000000", - 5 => "00001011011111111111111010000011", - 6 => "11101101000000000000000000001000", - 7 => "11100111100000000000000000001111", - 8 => "11100111100000000000000000010011", - - 9 => x"ed080048", --;ldi r1, 9;; - 10 => x"ed500080", --;ldil r10, list@lo ;; global pointer - 11 => x"fd500002", --;ldih r10, list@hi;; - 12 => x"eb000107", --;call+ fibcall;; + + 0 => "11101101000000000000000001011000", -- r0 = 11 + 1 => "11101101000010000000000000111000", -- r1 = 7 + 2 => "11100111100010000000000000000000", --stw + 3 => "11101101000000000000000000011000", -- r0 = 3 + 4 => "11101101000010000000000001001000", -- r1 = 9 + 5 => "11100111000010000000000000000000", --ldw + 6 => "11101101000000000000000000011000", -- r0 = 3 + 7 => "11101101000010000000000001001000", -- r1 = 9 + --8 => "11100111100010000000000000000000", --stw +-- 0 => "11101101000000000000000000000000", --ldi +-- 1 => "11101101001000000000000000000000", --ldi +-- 2 => "11100111101000000000000000000000", --stw +-- 3 => "11100001000000000000000000100001", +-- 4 => "11101100100000000000001100000000", +-- 5 => "00001011011111111111111010000011", +-- 6 => "11101101000000000000000000001000", +-- 7 => "11100111100000000000000000001111", +-- 8 => "11100111100000000000000000010011", + +-- 9 => x"ed080048", --;ldi r1, 9;; +-- 10 => x"ed500080", --;ldil r10, list@lo ;; global pointer +-- 11 => x"fd500002", --;ldih r10, list@hi;; +-- 12 => x"eb000107", --;call+ fibcall;; --13 => x"eb7ffe03", --;br+ main;; - 13 => "11101011000000000000000000000010", -- endless loop --2; fib(n) { +-- 13 => "11101011000000000000000000000010", -- endless loop --2; fib(n) { --2; if (list[n] > 0) { --2; return list[n] --2; } @@ -39,32 +49,32 @@ architecture behaviour of r_w_ram is --2; } --3;fibcall; --2;update counter for aligned access - 14 => x"e5088800", --;lls r1, r1, 2 ;; *4 +-- 14 => x"e5088800", --;lls r1, r1, 2 ;; *4 --2;calculate adress of top element - 15 => x"e0150800", --;add r2, r10, r1;; +-- 15 => x"e0150800", --;add r2, r10, r1;; --3;fibmem; --2;load top element - 16 => x"e7010000", --;ldw r0, 0(r2);; +-- 16 => x"e7010000", --;ldw r0, 0(r2);; --2;compare if set - 17 => x"ec800000", --;cmpi r0, 0;; +-- 17 => x"ec800000", --;cmpi r0, 0;; --2;return if set - 18 => x"0b000008", --;retnz-;; +-- 18 => x"0b000008", --;retnz-;; --2;decrement adress for next lopp - 19 => x"e1910020", --;subi r2, r2, 4;; +-- 19 => x"e1910020", --;subi r2, r2, 4;; --2;iterative call for n-1 element - 20 => x"eb7ffe07", --;call+ fibmem;; +-- 20 => x"eb7ffe07", --;call+ fibmem;; --2;load n-2 element - 21 => x"e7197ffc", --;ldw r3, 0-4(r2);; +-- 21 => x"e7197ffc", --;ldw r3, 0-4(r2);; --2;add n-1 and n-2 element - 22 => x"e0018000", --;add r0, r3, r0;; +-- 22 => x"e0018000", --;add r0, r3, r0;; --2;increment address for n element --2;is needed because after return --2;we need r2 to be set to the address --2;of element n - 23 => x"e1110020", --;addi r2, r2, 4;; +-- 23 => x"e1110020", --;addi r2, r2, 4;; --2;store fib n - 24 => x"e7810000", --;stw r0, 0(r2);; - 25 => x"eb00000a", --;ret+;; +-- 24 => x"e7810000", --;stw r0, 0(r2);; +-- 25 => x"eb00000a", --;ret+;; -- 1 1 2 3 5 8 13 21 34 55 diff --git a/cpu/src/rs232_tx.vhd b/cpu/src/rs232_tx.vhd index d8fb516..d6684d3 100755 --- a/cpu/src/rs232_tx.vhd +++ b/cpu/src/rs232_tx.vhd @@ -31,10 +31,12 @@ entity rs232_tx is --Bus bus_tx : out std_logic; - --From/to sendlogic + --From/to extension new_tx_data : in std_logic; tx_data : in uart_data; - tx_rdy : out std_logic + tx_rdy : out std_logic; + bd_rate : in baud_rate_l; + stop_bit : in std_logic ); end rs232_tx; diff --git a/cpu/src/rs232_tx_arc.vhd b/cpu/src/rs232_tx_arc.vhd index cc29340..188566a 100755 --- a/cpu/src/rs232_tx_arc.vhd +++ b/cpu/src/rs232_tx_arc.vhd @@ -99,11 +99,19 @@ begin when 9 => -- counter = 9 => Stopbit versenden bus_tx_nxt <= '1'; + -- stop_bit 0 heißt 1 stop bit + if stop_bit = '0' then + cnt_next <= 0; + idle_sig_next <= '1'; + end if; when 10 => bus_tx_nxt <= '1'; - cnt_next <= 0; - -- Signalisieren dass der Sendevorgang beendet ist - idle_sig_next <= '1'; + -- stop_bit 1 heißt 2 stop bits + if stop_bit = '1' then + cnt_next <= 0; + -- Signalisieren dass der Sendevorgang beendet ist + idle_sig_next <= '1'; + end if; when others => -- counter von 1 bis 8 => Datenbits versenden bus_tx_nxt <= tx_data(cnt-1); diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd index c771c91..0ad3689 100644 --- a/cpu/src/writeback_stage_b.vhd +++ b/cpu/src/writeback_stage_b.vhd @@ -7,15 +7,18 @@ use work.core_pkg.all; use work.mem_pkg.all; use work.extension_pkg.all; +use work.extension_uart_pkg.all; architecture behav of writeback_stage is -signal data_ram_read : word_t; +signal data_ram_read, data_ram_read_ext : word_t; signal wb_reg, wb_reg_nxt : writeback_rec; signal ext_uart,ext_timer,ext_gpmp : extmod_rec; +signal bus_tx,sel_nxt :std_logic; + begin @@ -36,6 +39,18 @@ begin data_ram_read ); +uart : extension_uart + generic map( + RESET_VALUE + ) + port map( + clk , + reset, + ext_uart, + data_ram_read_ext, + bus_tx + ); + syn: process(clk, reset) @@ -134,39 +149,39 @@ begin end process; -addr_de_mult: process(wb_reg_nxt.address, ram_data, wb_reg) +addr_de_mult: process(wb_reg_nxt.address, ram_data, wb_reg,sel_nxt,wb_reg_nxt.dmem_write_en) begin - - ext_uart.sel <='0'; - ext_uart.wr_en <= '0'; + ext_uart.sel <='0'; + ext_uart.wr_en <= wb_reg_nxt.dmem_write_en; ext_uart.byte_en <= (others => '0'); ext_uart.data <= (others => '0'); ext_uart.addr <= (others => '0'); ext_timer.sel <='0'; - ext_timer.wr_en <= '0'; + ext_timer.wr_en <= wb_reg_nxt.dmem_write_en; ext_timer.byte_en <= (others => '0'); ext_timer.data <= (others => '0'); ext_timer.addr <= (others => '0'); ext_gpmp.sel <='0'; - ext_gpmp.wr_en <= '0'; + ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en; ext_gpmp.byte_en <= (others => '0'); ext_gpmp.data <= (others => '0'); ext_gpmp.addr <= (others => '0'); -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.- case wb_reg_nxt.address(wb_reg_nxt.address'high downto 4) is when EXT_UART_ADDR => - ext_uart.sel <='1'; - ext_uart.wr_en <= wb_reg_nxt.dmem_write_en; + ext_uart.sel <='1'; + ext_timer.wr_en <= wb_reg_nxt.dmem_write_en; ext_uart.data <= ram_data; ext_uart.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR); case wb_reg.address(1 downto 0) is when "00" => ext_uart.byte_en <= "0001"; when "01" => ext_uart.byte_en <= "0010"; when "10" => ext_uart.byte_en <= "0100"; - when "11" => ext_uart.byte_en <= "1000"; + --when "11" => ext_uart.byte_en <= "1000"; + when "11" => ext_uart.byte_en <= "1111"; when others => null; end case; when EXT_TIMER_ADDR => -- 2.25.1