From 0400376e8079507732ceef10581239444caabb65 Mon Sep 17 00:00:00 2001 From: Markus HOFSTAETTER Date: Mon, 15 Nov 2010 13:49:35 +0100 Subject: [PATCH] exec impl. --- cpu/src/alu.vhd | 2 +- cpu/src/alu_pkg.vhd | 25 ++++++++++++++++---- cpu/src/common_pkg.vhd | 4 ++-- cpu/src/exec_op/shift_op_b.vhd | 25 ++++++++++---------- cpu/src/execute_stage.vhd | 1 + cpu/src/execute_stage_b.vhd | 42 +++++++++++++++++++++++++++++++--- cpu/src/extension_pkg.vhd | 23 +++++++++++++++++++ cpu/src/gpm.vhd | 40 ++++++++++++++++++++++++++++++++ 8 files changed, 139 insertions(+), 23 deletions(-) create mode 100644 cpu/src/extension_pkg.vhd create mode 100644 cpu/src/gpm.vhd diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd index b94421a..8928ece 100755 --- a/cpu/src/alu.vhd +++ b/cpu/src/alu.vhd @@ -13,7 +13,7 @@ entity alu is clk : in std_logic; reset : in std_logic; --operation inputs - condition : condition_t; + condition : in condition_t; op_group : in op_info_t; left_operand : in gp_register_t; right_operand : in gp_register_t; diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd index 05e040d..088565b 100755 --- a/cpu/src/alu_pkg.vhd +++ b/cpu/src/alu_pkg.vhd @@ -26,14 +26,14 @@ package alu_pkg is result_addr : gp_addr_t; status : status_rec; - stackpointer : gp_register_t; + --stackpointer : gp_register_t; alu_jmp : std_logic; - brpr_bit : std_logic; + brpr : std_logic; reg_op : std_logic; mem_op : std_logic; - new_val : std_logic; + --new_val : std_logic; mem_en : std_logic; hw_op : std_logic; @@ -71,7 +71,24 @@ package alu_pkg is -- function xor_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec; -- function shift_op(left_operand, right_operand : gp_register_t; arith,sleft,carry : std_logic ;alu_result : alu_result_rec) return alu_result_rec; - + + component alu is + --some modules won't need all inputs + port( + --System inputs + + clk : in std_logic; + reset : in std_logic; + --operation inputs + condition : in condition_t; + op_group : in op_info_t; + left_operand : in gp_register_t; + right_operand : in gp_register_t; + op_detail : in op_opt_t; + alu_state : in alu_result_rec; + alu_result : out alu_result_rec + ); + end component alu; end package alu_pkg; diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd index 1dca196..3046651 100755 --- a/cpu/src/common_pkg.vhd +++ b/cpu/src/common_pkg.vhd @@ -49,11 +49,11 @@ package common_pkg is constant IMM_OPT : integer := 0; -- no sharing constant SUB_OPT : integer := 1; - constant LOG_OPT : integer := 1; + constant ARITH_OPT : integer := 1; constant CARRY_OPT : integer := 2; - constant LEFT_OPT : integer := 3; + constant RIGHT_OPT : integer := 3; constant NO_PSW_OPT : integer := 4;--no sharing constant NO_DST_OPT : integer := 5; --no sharing diff --git a/cpu/src/exec_op/shift_op_b.vhd b/cpu/src/exec_op/shift_op_b.vhd index 0b5a73c..2d5311d 100755 --- a/cpu/src/exec_op/shift_op_b.vhd +++ b/cpu/src/exec_op/shift_op_b.vhd @@ -11,30 +11,29 @@ architecture shift_op of exec_op is begin - logic <= op_detail(LOG_OPT); - ls <= op_detail(LEFT_OPT); + arith <= op_detail(ARITH_OPT); + rs <= op_detail(RIGHT_OPT); carry <= op_detail(CARRY_OPT); -calc: process(left_operand, right_operand, logic,ls, carry, alu_state) +calc: process(left_operand, right_operand, arith,rs, carry, alu_state) variable alu_result_v : alu_result_rec; variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0); variable tmp_sb : std_logic; - begin +begin alu_result_v := alu_state; - if ls = '1' then - tmp_sb := (carry and alu_state.status.carry and logic); - tmp_shift := to_bitvector(alu_state.status.carry & left_operand & tmp_sb); - tmp_shift := tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0)); - - alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high); - - else - tmp_sb := (carry and alu_state.status.carry and logic) or (not(logic) and left_operand(gp_register_t'high)); + if rs = '1' then + tmp_sb := (carry and alu_state.status.carry and not(arith)) or (arith and left_operand(gp_register_t'high)); tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry); tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0)); alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0); + else + tmp_sb := (carry and alu_state.status.carry and not(arith)); + tmp_shift := to_bitvector(alu_state.status.carry & left_operand & tmp_sb); + tmp_shift := tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0)); + + alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high); end if; alu_result_v.result := to_stdlogicvector(tmp_shift)(gp_register_t'length downto 1); diff --git a/cpu/src/execute_stage.vhd b/cpu/src/execute_stage.vhd index d69fdc0..925c579 100644 --- a/cpu/src/execute_stage.vhd +++ b/cpu/src/execute_stage.vhd @@ -15,6 +15,7 @@ entity execute_stage is --System inputs clk : in std_logic; reset : in std_logic; + dec_instr : in dec_op ); end execute_stage; diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd index 6b6b621..095d4dc 100644 --- a/cpu/src/execute_stage_b.vhd +++ b/cpu/src/execute_stage_b.vhd @@ -2,24 +2,60 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.core_pkg.all; +use work.common_pkg.all; +use work.alu_pkg.all; architecture behav of execute_stage is +signal condition : condition_t; +signal op_group : op_info_t; +signal op_detail : op_opt_t; +signal left_operand, right_operand : gp_register_t; +signal alu_state, alu_nxt : alu_result_rec; + +signal psw : status_rec; begin +alu_inst : alu +port map(clk, reset, condition, op_group, + op_detail, left_operand, right_operand, alu_state, alu_nxt); + syn: process(sys_clk, reset) begin if (reset = RESET_VALUE) then - + condition <= elsif rising_edge(sys_clk) then end if; -end process; +end process; + +asyn: process(reset,condition) +begin + + condition <= dec_instr.condition; + op_group <= dec_instr.op_group; + op_detail <= dec_instr.op_detail; + left_operand <= dec_instr.src1; + right_operand <= dec_instr.src2; + + alu_state.status <= psw; + alu_state.result_addr <= dec_instr.daddr; + alu_state.brpr <= brpr; + alu_state.reg_op <= '0'; + alu_state.mem_op <= '0'; + alu_state. + + if reset = RESET_VALUE then + condition <= COND_NEVER; + else + + end if; + +end process asyn; end behav; diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd new file mode 100644 index 0000000..bf58a27 --- /dev/null +++ b/cpu/src/extension_pkg.vhd @@ -0,0 +1,23 @@ +library IEEE; + +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.common_pkg.all; + + +package extension_pkg is + + type extmod_rec is record + clk : std_logic; + reset : std_logic; + sel : std_logic; + + wr_en : std_logic; + byte_en : std_logic_vector(gp_register_t'length/byte_t'length-1 downto 0); + data : data_ram_word_t; + addr : data_addr_t; + end record; + + +end package extension_pkg; diff --git a/cpu/src/gpm.vhd b/cpu/src/gpm.vhd new file mode 100644 index 0000000..7bba400 --- /dev/null +++ b/cpu/src/gpm.vhd @@ -0,0 +1,40 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.common_pkg.all; +use work.alu_pkg.all; +use work.extension_pgk.all; + +entity gpm is + + generic ( + -- active reset value + RESET_VALUE : std_logic; + -- active logic value + LOGIC_ACT : std_logic + + ); + port( + --System inputs + clk : in std_logic; + reset : in std_logic; + + exti : in extmod_rec; + --alu outpus + alu_nxt : in alu_result_rec; + --input + + --output + psw : out status_rec; + --to memcnt + addr : out gp_register_t; + mem_en : out std_logic; + ldst : out std_logic; + --, hw,byte: std_logic; + --to output bus + exto : out data_ram_word_t + + ); + +end gpm; -- 2.25.1