From c22560759ba6cbf74fc32fc5b20609156942ee0f Mon Sep 17 00:00:00 2001 From: "U-Thor\\Schakal" Date: Sat, 11 Dec 2010 10:34:05 +0100 Subject: [PATCH] bugfix: sp operation first approach. --- cpu/sim/testcore.do | 5 ++--- cpu/src/alu.vhd | 1 + cpu/src/alu_b.vhd | 6 +++++- cpu/src/core_pkg.vhd | 1 + cpu/src/core_top.vhd | 3 ++- cpu/src/execute_stage_b.vhd | 2 +- cpu/src/extension_b.vhd | 31 +++++++++++++++---------------- cpu/src/pipeline_tb.vhd | 7 +++++-- 8 files changed, 32 insertions(+), 24 deletions(-) diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do index c1a219c..41ea364 100644 --- a/cpu/sim/testcore.do +++ b/cpu/sim/testcore.do @@ -7,6 +7,7 @@ vcom -work work ../src/r_w_ram_b.vhd vcom -work work ../src/r2_w_ram.vhd vcom -work work ../src/r2_w_ram_b.vhd vcom -work work ../src/common_pkg.vhd +vcom -work work ../src/extension_pkg.vhd vcom -work work ../src/core_pkg.vhd vcom -work work ../src/decoder.vhd vcom -work work ../src/decoder_b.vhd @@ -17,7 +18,6 @@ vcom -work work ../src/decode_stage_b.vhd vcom -work work ../src/alu_pkg.vhd vcom -work work ../src/extension_pkg.vhd -vcom -work work ../src/gpm_pkg.vhd vcom -work work ../src/exec_op.vhd vcom -work work ../src/exec_op/add_op_b.vhd @@ -29,12 +29,11 @@ vcom -work work ../src/exec_op/shift_op_b.vhd vcom -work work ../src/alu.vhd vcom -work work ../src/alu_b.vhd vcom -work work ../src/extension_pkg.vhd -vcom -work work ../src/gpm_pkg.vhd +#vcom -work work ../src/gpm_pkg.vhd #vcom -work work ../src/gpm.vhd #vcom -work work ../src/gpm_b.vhd -vcom -work work ../src/extension_pkg.vhd vcom -work work ../src/extension.vhd vcom -work work ../src/extension_b.vhd diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd index 3df35c9..4d2e747 100755 --- a/cpu/src/alu.vhd +++ b/cpu/src/alu.vhd @@ -4,6 +4,7 @@ use IEEE.numeric_std.all; use work.common_pkg.all; use work.alu_pkg.all; +use work.extension_pkg.all; entity alu is --some modules won't need all inputs diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd index c46f9e5..b0bf5a4 100755 --- a/cpu/src/alu_b.vhd +++ b/cpu/src/alu_b.vhd @@ -41,7 +41,7 @@ begin shift_inst : entity work.exec_op(shift_op) port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result); -calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr) +calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr, pval) variable result_v : alu_result_rec; variable res_prod : std_logic; variable cond_met : std_logic; @@ -63,6 +63,10 @@ begin addr <= add_result.result; data <= right_operand; + pinc <= '0'; + pwr_en <= '0'; + paddr <= (others =>'0'); + result_v.result := add_result.result; case cond is diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd index 4d31870..2340344 100644 --- a/cpu/src/core_pkg.vhd +++ b/cpu/src/core_pkg.vhd @@ -4,6 +4,7 @@ use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.common_pkg.all; +use work.extension_pkg.all; package core_pkg is diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd index d67243c..47eb124 100644 --- a/cpu/src/core_top.vhd +++ b/cpu/src/core_top.vhd @@ -4,6 +4,7 @@ use IEEE.numeric_std.all; use work.common_pkg.all; use work.core_pkg.all; +use work.extension_pkg.all; entity core_top is @@ -48,7 +49,7 @@ architecture behav of core_top is signal hword_pin : std_logic; signal byte_s_pin : std_logic; - signal gpm_in_pin : ext_mod_rec; + signal gpm_in_pin : extmod_rec; signal gpm_out_pin : gp_register_t; signal nop_pin : std_logic; diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd index ccbfee3..f2c2dc2 100644 --- a/cpu/src/execute_stage_b.vhd +++ b/cpu/src/execute_stage_b.vhd @@ -4,7 +4,7 @@ use IEEE.numeric_std.all; use work.common_pkg.all; use work.alu_pkg.all; -use work.gpm_pkg.all; +--use work.gpm_pkg.all; use work.extension_pkg.all; architecture behav of execute_stage is diff --git a/cpu/src/extension_b.vhd b/cpu/src/extension_b.vhd index d004bbb..8ffb46a 100644 --- a/cpu/src/extension_b.vhd +++ b/cpu/src/extension_b.vhd @@ -25,16 +25,16 @@ syn : process (clk, reset) begin if (reset = RESET_VALUE) then reg.status <= (others=>'0'); - reg.pointers <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,DATA_ADDR_WIDTH))); + reg.preg <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,reg.preg(0)'length)))); elsif rising_edge(clk) then reg <= reg_nxt; end if; end process syn; -asyn : process (clk, reset, reg, psw_nxt, ext_reg, pval, pwr_en, pinc, paddr) +asyn : process (clk, reset, reg, psw_nxt, ext_reg, pwr_en, pinc, paddr) variable reg_nxt_v : gpm_internal; variable incb : gp_register_t; - variable sel_pval : gp_register_t; + variable sel_pval : std_logic_vector(reg.preg(0)'range); variable data_out_v : gp_register_t; variable data_v : gp_register_t; @@ -58,48 +58,47 @@ begin case ext_reg.addr(1 downto 0) is when "00" => if ext_reg.byte_en(0) = '1' then - reg_nxt_v.psw := (data_v(0), data_v(1), data_v(3), data_v(2)); - psw <= reg_nxt_v.psw; + reg_nxt_v.status := (data_v(0), data_v(1), data_v(3), data_v(2)); + psw <= reg_nxt_v.status; end if; when "01" => --STACK_POINTER tmp_data := (others =>'0'); - tmp_data(tmp_data'high downto BYTE_ADDR) := reg.preg(0); + tmp_data(tmp_data'high downto BYTEADDR) := reg.preg(0); if ext_reg.byte_en(0) = '1' then tmp_data(byte_t'range) := data_v(byte_t'range); end if; if ext_reg.byte_en(1) = '1' then - tmp_data((2*byte_t'length-1) downto byte_t'length) := data_v(2*byte_t'length-1) downto byte_t'length); + tmp_data((2*byte_t'length-1) downto byte_t'length) := data_v((2*byte_t'length-1) downto byte_t'length); end if; if ext_reg.byte_en(2) = '1' then - tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := data_v(3*byte_t'length-1) downto 2*byte_t'length); + tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := data_v((3*byte_t'length-1) downto 2*byte_t'length); end if; if ext_reg.byte_en(3) = '1' then - tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := data_v(4*byte_t'length-1) downto 3*byte_t'length); + tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := data_v((4*byte_t'length-1) downto 3*byte_t'length); end if; - reg_nxt_v.preg(0) := tmp_data(tmp_data'high downto BYTE_ADDR); + reg_nxt_v.preg(0) := tmp_data(tmp_data'high downto BYTEADDR); when others => null; end case; end if; - if (ext_reg.sel = '1') and wr_en = '0' then + if (ext_reg.sel = '1') and ext_reg.wr_en = '0' then case ext_reg.addr(1 downto 0) is when "00" => if ext_reg.byte_en(0) = '1' then - data_out_v(3 downto 0) <= (reg.status.sign, reg.status.carry, reg.status.oflo, reg.status.zero); + data_out_v(3 downto 0) := (reg.status.sign, reg.status.carry, reg.status.oflo, reg.status.zero); end if; when "01" => --STACK_POINTER - data_out_v(data_out_v'high downto BYTE_ADDR) := reg.preg(0); + data_out_v(data_out_v'high downto BYTEADDR) := reg.preg(0); when others => null; end case; end if; - - sel_pval := reg_nxt_v.preg(unsigned(paddr)); + sel_pval:= reg_nxt_v.preg(to_integer(unsigned(paddr))); if pwr_en = '1' then reg_nxt_v.preg(to_integer(unsigned(paddr))) := std_logic_vector(unsigned(sel_pval)+unsigned(incb)); @@ -111,7 +110,7 @@ begin data_out <= data_out_v; pval <= (others =>'0'); - pval(pval'high downto BYTE_ADDR) <= sel_pval; + pval(pval'high downto BYTEADDR) <= sel_pval; end process asyn; end behav; diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd index aafbd4c..fd86d72 100644 --- a/cpu/src/pipeline_tb.vhd +++ b/cpu/src/pipeline_tb.vhd @@ -49,6 +49,9 @@ architecture behavior of pipeline_tb is signal dmem_wr_en_pin : std_logic; signal hword_pin : std_logic; signal byte_s_pin : std_logic; + + signal gpm_in_pin : extmod_rec; + signal gpm_out_pin : gp_register_t; signal nop_pin : std_logic; @@ -121,8 +124,8 @@ begin ); exec_st : execute_stage generic map('0') - port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin, - data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin); + port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, + data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin); writeback_st : writeback_stage generic map('0', '1') -- 2.25.1