From b333da851dda456b48f2a2535c4aeba143c657e1 Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Fri, 17 Dec 2010 22:43:27 +0100 Subject: [PATCH] instr mem durch case, fibonacci als programm, 7seg als extension geadded, resultat am 7seg ausgegeben, fmax muss optimiert werden, evtl. reg vor ram und ext --- cpu/create_project.tcl | 48 ++++++++++++- cpu/sim/testcore.do | 7 +- cpu/src/core_pkg.vhd | 7 +- cpu/src/core_top.vhd | 9 ++- cpu/src/decoder_b.vhd | 2 +- cpu/src/extension_pkg.vhd | 2 +- cpu/src/fetch_stage_b.vhd | 2 +- cpu/src/mem_pkg.vhd | 19 +++++ cpu/src/pipeline_tb.vhd | 6 +- cpu/src/r_w_ram_b.vhd | 128 ++-------------------------------- cpu/src/writeback_stage.vhd | 7 +- cpu/src/writeback_stage_b.vhd | 44 ++++++++++-- 12 files changed, 143 insertions(+), 138 deletions(-) diff --git a/cpu/create_project.tcl b/cpu/create_project.tcl index 5364415..27fa930 100755 --- a/cpu/create_project.tcl +++ b/cpu/create_project.tcl @@ -47,10 +47,22 @@ if {$make_assignments} { set_global_assignment -name VHDL_FILE ../src/decode_stage.vhd set_global_assignment -name VHDL_FILE ../src/decode_stage_b.vhd + set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd + set_global_assignment -name VHDL_FILE ../src/extension_uart_pkg.vhd + set_global_assignment -name VHDL_FILE ../src/extension_uart.vhd + set_global_assignment -name VHDL_FILE ../src/extension_uart_b.vhd + set_global_assignment -name VHDL_FILE ../src/rs232_tx.vhd + set_global_assignment -name VHDL_FILE ../src/rs232_tx_arc.vhd + set_global_assignment -name VHDL_FILE ../src/rs232_rx.vhd + set_global_assignment -name VHDL_FILE ../src/rs232_rx_arc.vhd + set_global_assignment -name VHDL_FILE ../src/extension_7seg_pkg.vhd + set_global_assignment -name VHDL_FILE ../src/extension_7seg.vhd + set_global_assignment -name VHDL_FILE ../src/extension_7seg_b.vhd + set_global_assignment -name VHDL_FILE ../src/alu_pkg.vhd set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd - set_global_assignment -name VHDL_FILE ../src/gpm_pkg.vhd +# set_global_assignment -name VHDL_FILE ../src/gpm_pkg.vhd set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd set_global_assignment -name VHDL_FILE ../src/extension.vhd set_global_assignment -name VHDL_FILE ../src/extension_b.vhd @@ -78,6 +90,40 @@ if {$make_assignments} { set_location_assignment PIN_L1 -to sys_clk set_location_assignment PIN_R22 -to sys_res + set_location_assignment PIN_G12 -to bus_tx + + set_location_assignment PIN_J2 -to sseg0[0] + set_location_assignment PIN_J1 -to sseg0[1] + set_location_assignment PIN_H2 -to sseg0[2] + set_location_assignment PIN_H1 -to sseg0[3] + set_location_assignment PIN_F2 -to sseg0[4] + set_location_assignment PIN_F1 -to sseg0[5] + set_location_assignment PIN_E2 -to sseg0[6] + + set_location_assignment PIN_E1 -to sseg1[0] + set_location_assignment PIN_H6 -to sseg1[1] + set_location_assignment PIN_H5 -to sseg1[2] + set_location_assignment PIN_H4 -to sseg1[3] + set_location_assignment PIN_G3 -to sseg1[4] + set_location_assignment PIN_D2 -to sseg1[5] + set_location_assignment PIN_D1 -to sseg1[6] + + set_location_assignment PIN_G5 -to sseg2[0] + set_location_assignment PIN_G6 -to sseg2[1] + set_location_assignment PIN_C2 -to sseg2[2] + set_location_assignment PIN_C1 -to sseg2[3] + set_location_assignment PIN_E3 -to sseg2[4] + set_location_assignment PIN_E4 -to sseg2[5] + set_location_assignment PIN_D3 -to sseg2[6] + + set_location_assignment PIN_F4 -to sseg3[0] + set_location_assignment PIN_D5 -to sseg3[1] + set_location_assignment PIN_D6 -to sseg3[2] + set_location_assignment PIN_J4 -to sseg3[3] + set_location_assignment PIN_L8 -to sseg3[4] + set_location_assignment PIN_F3 -to sseg3[5] + set_location_assignment PIN_D4 -to sseg3[6] + set_global_assignment -name FMAX_REQUIREMENT "80.00 MHz" -section_id sys_clk set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do index 9a4c3fe..0b2647e 100644 --- a/cpu/sim/testcore.do +++ b/cpu/sim/testcore.do @@ -6,17 +6,22 @@ vcom -work work ../src/r_w_ram.vhd vcom -work work ../src/r_w_ram_b.vhd vcom -work work ../src/r2_w_ram.vhd vcom -work work ../src/r2_w_ram_b.vhd +vcom -work work ../src/rom.vhd +vcom -work work ../src/rom_b.vhd vcom -work work ../src/common_pkg.vhd +vcom -work work ../src/core_pkg.vhd vcom -work work ../src/extension_pkg.vhd vcom -work work ../src/extension_uart_pkg.vhd vcom -work work ../src/extension_uart.vhd vcom -work work ../src/extension_uart_b.vhd +vcom -work work ../src/extension_7seg_pkg.vhd +vcom -work work ../src/extension_7seg.vhd +vcom -work work ../src/extension_7seg_b.vhd vcom -work work ../src/rs232_tx.vhd vcom -work work ../src/rs232_tx_arc.vhd vcom -work work ../src/rs232_rx.vhd vcom -work work ../src/rs232_rx_arc.vhd -vcom -work work ../src/core_pkg.vhd vcom -work work ../src/decoder.vhd vcom -work work ../src/decoder_b.vhd vcom -work work ../src/fetch_stage.vhd diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd index 0072827..d3aeb3f 100644 --- a/cpu/src/core_pkg.vhd +++ b/cpu/src/core_pkg.vhd @@ -145,7 +145,12 @@ package core_pkg is jump_addr : out instruction_addr_t; jump : out std_logic; -- same here - bus_tx : out std_logic + bus_tx : out std_logic; + + sseg0 : out std_logic_vector(0 to 6); + sseg1 : out std_logic_vector(0 to 6); + sseg2 : out std_logic_vector(0 to 6); + sseg3 : out std_logic_vector(0 to 6) ); end component writeback_stage; diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd index fdd760f..d81095c 100644 --- a/cpu/src/core_top.vhd +++ b/cpu/src/core_top.vhd @@ -15,7 +15,12 @@ entity core_top is -- result : out gp_register_t; -- reg_wr_data : out gp_register_t -- uart - bus_tx : out std_logic + bus_tx : out std_logic; + + sseg0 : out std_logic_vector(0 to 6); + sseg1 : out std_logic_vector(0 to 6); + sseg2 : out std_logic_vector(0 to 6); + sseg3 : out std_logic_vector(0 to 6) ); end core_top; @@ -116,7 +121,7 @@ begin generic map('0', '1') port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, - reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx); + reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3); diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd index 911bd00..7425381 100644 --- a/cpu/src/decoder_b.vhd +++ b/cpu/src/decoder_b.vhd @@ -154,7 +154,7 @@ begin instr_s.op_detail(IMM_OPT) := '1'; instr_s.op_detail(NO_PSW_OPT) := instruction(0); - if (instr_s.opcode = "00111") then + if (instr_s.opcode = "00101") then instr_s.op_group := AND_OP; end if; diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd index 89cc7a7..20cf1cd 100644 --- a/cpu/src/extension_pkg.vhd +++ b/cpu/src/extension_pkg.vhd @@ -34,7 +34,7 @@ type status_rec is record carry : std_logic; end record; -constant EXT_7SEG_ADDR: ext_addrid_t := x"FFFFFFA"; +constant EXT_7SEG_ADDR: ext_addrid_t := x"0000201"; constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB"; constant EXT_TIMER_ADDR: ext_addrid_t := x"FFFFFFC"; constant EXT_AC97_ADDR: ext_addrid_t := x"FFFFFFD"; diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd index 7409e42..b2058a7 100644 --- a/cpu/src/fetch_stage_b.vhd +++ b/cpu/src/fetch_stage_b.vhd @@ -17,7 +17,7 @@ signal instr_rd_data : instruction_word_t; begin - instruction_ram : r_w_ram + instruction_ram : rom --r_w_ram generic map ( PHYS_INSTR_ADDR_WIDTH, WORD_WIDTH diff --git a/cpu/src/mem_pkg.vhd b/cpu/src/mem_pkg.vhd index 72ecb58..c8ab2b8 100644 --- a/cpu/src/mem_pkg.vhd +++ b/cpu/src/mem_pkg.vhd @@ -23,6 +23,25 @@ package mem_pkg is data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) ); end component r_w_ram; + + component rom is + generic ( + ADDR_WIDTH : integer range 1 to integer'high; + DATA_WIDTH : integer range 1 to integer'high + ); + port( + --System inputs + clk : in std_logic; + --Input + wr_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + + wr_en : in std_logic; + data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); + + --Output + data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) + ); + end component rom; component r2_w_ram is generic ( diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd index d87cee1..8539c42 100644 --- a/cpu/src/pipeline_tb.vhd +++ b/cpu/src/pipeline_tb.vhd @@ -48,7 +48,7 @@ architecture behavior of pipeline_tb is signal dmem_pin : std_logic;--memop signal dmem_wr_en_pin : std_logic; signal hword_pin : std_logic; - signal byte_s_pin : std_logic; + signal byte_s_pin, tx_pin : std_logic; signal gpm_in_pin : extmod_rec; signal gpm_out_pin : gp_register_t; @@ -56,6 +56,8 @@ architecture behavior of pipeline_tb is signal cycle_cnt : integer; + signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6); + begin @@ -133,7 +135,7 @@ begin generic map('0', '1') port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, - reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin); + reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, sseg0, sseg1, sseg2, sseg3); diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd index 81682bb..e735c20 100644 --- a/cpu/src/r_w_ram_b.vhd +++ b/cpu/src/r_w_ram_b.vhd @@ -10,136 +10,20 @@ architecture behaviour of r_w_ram is subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0); type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE; - -- r0 = 0, r1 = 1, r2 = 3, r3 = A - - signal ram : RAM_TYPE := ( - -- 0 => x"ed2802d0", -- ldi r5, 0x5a;; - -- 1 => x"ed010058", -- ldi r0, 0x200b;; - -- 2 => x"e7a80000", -- stw r5, 0(r0);; - -- 3 => x"e7828000", -- stw r0, 0(r5);; - -- 4 => "11101011000000000000000000000010", - - --8 => "11100111100010000000000000000000", --stw --- 0 => "11101101000000000000000000000000", --ldi --- 1 => "11101101001000000000000000000000", --ldi --- 2 => "11100111101000000000000000000000", --stw --- 3 => "11100001000000000000000000100001", --- 4 => "11101100100000000000001100000000", --- 5 => "00001011011111111111111010000011", --- 6 => "11101101000000000000000000001000", --- 7 => "11100111100000000000000000001111", --- 8 => "11100111100000000000000000010011", - --- 9 => x"ed080048", --;ldi r1, 9;; --- 10 => x"ed500080", --;ldil r10, list@lo ;; global pointer --- 11 => x"fd500002", --;ldih r10, list@hi;; --- 12 => x"eb000107", --;call+ fibcall;; - --13 => x"eb7ffe03", --;br+ main;; --- 13 => "11101011000000000000000000000010", -- endless loop --2; fib(n) { - --2; if (list[n] > 0) { - --2; return list[n] - --2; } - --2; a = fib(n-1) - --2; list[n] = a + list[n-2] - --2; return list[n] - --2; } - --3;fibcall; - --2;update counter for aligned access --- 14 => x"e5088800", --;lls r1, r1, 2 ;; *4 - --2;calculate adress of top element --- 15 => x"e0150800", --;add r2, r10, r1;; - --3;fibmem; - --2;load top element --- 16 => x"e7010000", --;ldw r0, 0(r2);; - --2;compare if set --- 17 => x"ec800000", --;cmpi r0, 0;; - --2;return if set --- 18 => x"0b000008", --;retnz-;; - --2;decrement adress for next lopp --- 19 => x"e1910020", --;subi r2, r2, 4;; - --2;iterative call for n-1 element --- 20 => x"eb7ffe07", --;call+ fibmem;; - --2;load n-2 element --- 21 => x"e7197ffc", --;ldw r3, 0-4(r2);; - --2;add n-1 and n-2 element --- 22 => x"e0018000", --;add r0, r3, r0;; - --2;increment address for n element - --2;is needed because after return - --2;we need r2 to be set to the address - --2;of element n --- 23 => x"e1110020", --;addi r2, r2, 4;; - --2;store fib n --- 24 => x"e7810000", --;stw r0, 0(r2);; --- 25 => x"eb00000a", --;ret+;; - --- 1 1 2 3 5 8 13 21 34 55 - - - others => x"F0000000"); - --- signal ram : RAM_TYPE := ( 0 => "11101101000000000000000000000000", -- r0 = 0 --- --- 1 => "11101101000010000000000000111000", -- r1 = 7 --- 2 => "11101101000100000000000000101000", -- r2 = 5 --- 3 => "11101101000110000000000000100000", -- r3 = 4 --- 4 => "11100000001000010001100000000000", -- r4 = r2 + r3 --- 5 => "11100010001010100000100000000000", -- r5 = r4 and r1 --- --- 6 => "11100001000000000000000000001000", -- r0 = r0 + 1 --- 7 => "11101100100000000000000000011000", -- cmpi r0 , 2 --- --- 8 => "00001011011111111111110010000111", -- jump -7 --- 9 => "11101011000000000000000010000010", -- jump +1 --- --10 => "11101011000000000000000010000010", -- jump +1 --- - -- 10 => "11100111101010100000000000000001", -- stw r5,r4,1 - -- 11 => "11101100001000100000000000000000", -- cmp r4 , r4 => 2-2 => 1001 --- --- 12 => "11101011000000000000000000000010", -- jump +0 - - - - --- others => x"F0000000"); - --- signal ram : RAM_TYPE := ( 0 => "11100000000100001000000000000000", --add r2, r1, r0 => r2 = 1 --- 1 => "11100000000110001000000000000000", --add r3, r1, r0 => r3 = 1 --- 2 => "11100000001000011001000000000000", --add r4, r3, r2 => r4 = 2 --- 3 => "11100000000100001000000000000000", --add r2, r1, r0 => r2 = 1 --- 4 => "11100000000110001000000000000000", --add r3, r1, r0 => r3 = 1 --- 5 => "11100000001000011001000000000000", --add r4, r3, r2 => r4 = 2 --- 6 => "11101100000000001000000000000000", --cmp r0 , r1 => 0-1 => 0100 --- 7 => "00000000001010101010000000000001", --addnqd r5, r5, r4 => r5 = 2 --- 8 => "00000000001010101010000000000000", --addnq r5, r5, r4 => r5 = 4 --- 9 => "11101100001000100000000000000000", --cmp r4 , r4 => 2-2 => 1001 --- 10 => "00000001001100001000000001010000", --addinq r6, r1, 0xA => nix --- 11 => "00010001001100001000000001010000", --addieq r6, r1, 0xA => r6 = 0xB --- 12 => "00010001101100110000000001010000", --subieq r6, r5, 0xA => r6 = 1 --- 13 => "11100000000100001000000000000000", --add r2, r1, r0 => r2 = 1 --- 14 => "11100010000100001000000000000000", --and r2, r1, r0 => r2 = 0 --- 15 => "11101100000000001000000000000000", --cmp r0 , r1 => 0-1 => 0100 --- 16 => "10000000001010101010000000000001", --addabd r5, r5, r4 => r5 = 6 --- 17 => "10110011101110001000010000110001", --orxltd r7, 1086 => r7 = 1086 --- 18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1 => r7 = 2 --- 19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2 => r7 = 4 --- others => x"F0000000"); - - + signal ram : RAM_TYPE; + begin process(clk) begin if rising_edge(clk) then - -- data_out <= ram(to_integer(UNSIGNED(rd_addr))); - case rd_addr is - when "00000000000" => data_out <= x"ed2802d0"; -- ldi r5, 0x5a;; - when "00000000001" => data_out <= x"ed010058"; -- ldi r0, 0x200b;; - when "00000000010" => data_out <= x"e7a80000"; -- stw r5, 0(r0);; - when others => data_out <= "11101011000000000000000000000010"; - end case; + data_out <= ram(to_integer(UNSIGNED(rd_addr))); + + if wr_en = '1' then ram(to_integer(UNSIGNED(wr_addr))) <= data_in; end if; end if; end process; + end architecture behaviour; diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd index 4c1364c..73c5df4 100644 --- a/cpu/src/writeback_stage.vhd +++ b/cpu/src/writeback_stage.vhd @@ -36,7 +36,12 @@ entity writeback_stage is jump_addr : out instruction_addr_t; jump : out std_logic; -- hallo stefan mir adden da jetzt mal schnell an uart port :D - bus_tx : out std_logic + bus_tx : out std_logic; + + sseg0 : out std_logic_vector(0 to 6); + sseg1 : out std_logic_vector(0 to 6); + sseg2 : out std_logic_vector(0 to 6); + sseg3 : out std_logic_vector(0 to 6) ); end writeback_stage; diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd index 77fdf20..307996e 100644 --- a/cpu/src/writeback_stage_b.vhd +++ b/cpu/src/writeback_stage_b.vhd @@ -8,6 +8,7 @@ use work.core_pkg.all; use work.mem_pkg.all; use work.extension_pkg.all; use work.extension_uart_pkg.all; +use work.extension_7seg_pkg.all; architecture behav of writeback_stage is @@ -16,7 +17,7 @@ signal data_addr : word_t; signal wb_reg, wb_reg_nxt : writeback_rec; -signal ext_uart,ext_timer,ext_gpmp : extmod_rec; +signal ext_uart,ext_timer,ext_gpmp,ext_7seg : extmod_rec; signal sel_nxt, dmem_we, bus_rx :std_logic; @@ -52,7 +53,20 @@ uart : extension_uart bus_rx, bus_tx ); - + +sseg : extension_7seg + generic map( + RESET_VALUE + ) + port map( + clk, + reset, + ext_7seg, + sseg0, + sseg1, + sseg2, + sseg3 + ); syn: process(clk, reset) @@ -170,6 +184,12 @@ begin ext_uart.data <= (others => '0'); ext_uart.addr <= (others => '0'); + ext_7seg.sel <='0'; + ext_7seg.wr_en <= wb_reg_nxt.dmem_write_en; + ext_7seg.byte_en <= (others => '0'); + ext_7seg.data <= (others => '0'); + ext_7seg.addr <= (others => '0'); + ext_timer.sel <='0'; ext_timer.wr_en <= wb_reg_nxt.dmem_write_en; ext_timer.byte_en <= (others => '0'); @@ -185,10 +205,10 @@ begin case wb_reg_nxt.address(31 downto 4) is when EXT_UART_ADDR => ext_uart.sel <='1'; - ext_timer.wr_en <= wb_reg_nxt.dmem_write_en; + ext_uart.wr_en <= wb_reg_nxt.dmem_write_en; ext_uart.data <= ram_data; ext_uart.addr <= wb_reg_nxt.address(31 downto 2); - case wb_reg.address(1 downto 0) is + case wb_reg_nxt.address(1 downto 0) is when "00" => ext_uart.byte_en <= "0001"; when "01" => ext_uart.byte_en <= "0010"; when "10" => ext_uart.byte_en <= "0100"; @@ -196,7 +216,21 @@ begin when "11" => ext_uart.byte_en <= "1111"; when others => null; end case; - + + when EXT_7SEG_ADDR => + ext_7seg.sel <='1'; + ext_7seg.wr_en <= wb_reg_nxt.dmem_write_en; + ext_7seg.data <= ram_data; + ext_7seg.addr <= wb_reg_nxt.address(31 downto 2); + ext_7seg.byte_en(1 downto 0) <= wb_reg_nxt.address(1 downto 0); + +-- case wb_reg_nxt.address(1 downto 0) is +-- when "00" => ext_7seg.byte_en <= "0001"; +-- when "01" => ext_7seg.byte_en <= "0010"; +-- when "10" => ext_7seg.byte_en <= "0100"; +-- when "11" => ext_7seg.byte_en <= "1000"; +-- when others => null; +-- end case; when EXT_TIMER_ADDR => ext_timer.sel <='1'; -- 2.25.1