From 8173b5fa1ed9ea2a213f8f23ee9ed92869203884 Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Wed, 1 Dec 2010 16:14:50 +0100 Subject: [PATCH] static branch 1.0 --- cpu/src/core_pkg.vhd | 8 +++++--- cpu/src/decode_stage.vhd | 1 + cpu/src/decode_stage_b.vhd | 2 ++ cpu/src/decoder_b.vhd | 19 +++++++++++++++++++ cpu/src/fetch_stage.vhd | 3 ++- cpu/src/fetch_stage_b.vhd | 2 ++ cpu/src/pipeline_tb.vhd | 7 +++++-- 7 files changed, 36 insertions(+), 6 deletions(-) diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd index 820a16a..828f610 100644 --- a/cpu/src/core_pkg.vhd +++ b/cpu/src/core_pkg.vhd @@ -19,7 +19,7 @@ package core_pkg is --System inputs clk : in std_logic; reset : in std_logic; - + --Data inputs jump_result : in instruction_addr_t; prediction_result : in instruction_addr_t; @@ -27,8 +27,8 @@ package core_pkg is alu_jump_bit : in std_logic; --Data outputs - instruction : out instruction_word_t - + instruction : out instruction_word_t; + prog_cnt : out instruction_addr_t ); end component fetch_stage; @@ -49,6 +49,7 @@ package core_pkg is --Data inputs instruction : in instruction_word_t; + prog_cnt : in instruction_addr_t; reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0); reg_wr_data : in gp_register_t; reg_we : in std_logic; @@ -59,6 +60,7 @@ package core_pkg is -- reg2_rd_data : out gp_register_t; branch_prediction_res : out instruction_word_t; branch_prediction_bit : out std_logic; + to_next_stage : out dec_op ); end component decode_stage; diff --git a/cpu/src/decode_stage.vhd b/cpu/src/decode_stage.vhd index e99825d..92f7bfc 100644 --- a/cpu/src/decode_stage.vhd +++ b/cpu/src/decode_stage.vhd @@ -22,6 +22,7 @@ entity decode_stage is --Data inputs instruction : in instruction_word_t; + prog_cnt : in instruction_addr_t; reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0); reg_wr_data : in gp_register_t; reg_we : in std_logic; diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd index 92c0f71..c8075a1 100644 --- a/cpu/src/decode_stage_b.vhd +++ b/cpu/src/decode_stage_b.vhd @@ -67,6 +67,7 @@ begin dec_op_inst.saddr2 <= (others => '0'); dec_op_inst.daddr <= (others => '0'); dec_op_inst.displacement <= (others => '0'); + dec_op_inst.prog_cnt <= (others => '0'); elsif rising_edge(clk) then rtw_rec <= rtw_rec_nxt; @@ -117,6 +118,7 @@ begin dec_op_inst_nxt.daddr <= instr_spl.reg_dest_addr; --(others => '0'); dec_op_inst_nxt.op_group <= instr_spl.op_group; dec_op_inst_nxt.displacement <= instr_spl.displacement; + dec_op_inst_nxt.prog_cnt <= prog_cnt; end process; diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd index 87fb473..55358f8 100644 --- a/cpu/src/decoder_b.vhd +++ b/cpu/src/decoder_b.vhd @@ -292,6 +292,25 @@ begin instr_s.bp := instruction(1); instr_s.jmptype := instruction(3 downto 2); instr_s.signext := instruction(0); + instr_s.op_detail(NO_PSW_OPT) := '1'; + + + if (instr_s.opcode = "10110") then + instr_s.op_detail(IMM_OPT) := '1'; + else + instr_s.immediate(31 downto 0) := (others => '0'); + instr_s.op_detail(JMP_REG_OPT) := '1'; + instr_s.op_detail(IMM_OPT) := '1'; + end if; + + if (instr_s.signext = '1' and instr_s.immediate(15) = '1') then + instr_s.immediate(31 downto 16) := (others => '1'); + end if; + + if (instr_s.jmptype = "00") then +-- instr_s.op_detail(SUB_OPT) := not instr_s.opcode(0); + instr_s.op_group := JMP_OP; + end if; end if; -- when "10111" => --brreg diff --git a/cpu/src/fetch_stage.vhd b/cpu/src/fetch_stage.vhd index 5713c02..e77cfbf 100644 --- a/cpu/src/fetch_stage.vhd +++ b/cpu/src/fetch_stage.vhd @@ -26,7 +26,8 @@ entity fetch_stage is alu_jump_bit : in std_logic; --Data outputs - instruction : out instruction_word_t + instruction : out instruction_word_t; + prog_cnt : out instruction_addr_t ); end fetch_stage; diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd index 67dde3c..a73ab05 100644 --- a/cpu/src/fetch_stage_b.vhd +++ b/cpu/src/fetch_stage_b.vhd @@ -64,5 +64,7 @@ begin end process; +prog_cnt <= std_logic_vector(unsigned(instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0)) + 1; + end behav; diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd index 7a90561..3315344 100644 --- a/cpu/src/pipeline_tb.vhd +++ b/cpu/src/pipeline_tb.vhd @@ -31,6 +31,7 @@ architecture behavior of pipeline_tb is signal branch_prediction_bit_pin : std_logic; signal alu_jump_bit_pin : std_logic; signal instruction_pin : instruction_word_t; + signal prog_cnt : instruction_addr_t; signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0); signal reg_wr_data_pin : gp_register_t; @@ -87,8 +88,9 @@ begin alu_jump_bit => alu_jump_bit_pin, --: in std_logic; --Data outputs - instruction => instruction_pin --: out instruction_word_t - ); + instruction => instruction_pin, --: out instruction_word_t + prog_cnt => prog_cnt + ); decode_st : decode_stage generic map ( @@ -105,6 +107,7 @@ begin --Data inputs instruction => instruction_pin, --: in instruction_word_t; + prog_cnt => prog_cnt, reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0); reg_wr_data => reg_wr_data_pin, --: in gp_register_t; reg_we => reg_we_pin, --: in std_logic; -- 2.25.1