From 9b9e39f3672127dd87ea9dd022bddb3df3c2bef3 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Markus=20Hofst=C3=A4tter?= Date: Mon, 29 Nov 2010 15:48:35 +0100 Subject: [PATCH] stw alu --- cpu/src/alu.vhd | 3 ++- cpu/src/alu_b.vhd | 38 ++++++++++++++++++++++++------------- cpu/src/alu_pkg.vhd | 5 ++--- cpu/src/common_pkg.vhd | 3 ++- cpu/src/decoder_b.vhd | 1 + cpu/src/execute_stage_b.vhd | 5 ++++- cpu/src/r_w_ram_b.vhd | 2 ++ 7 files changed, 38 insertions(+), 19 deletions(-) diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd index 7950c6c..9883530 100755 --- a/cpu/src/alu.vhd +++ b/cpu/src/alu.vhd @@ -16,7 +16,8 @@ entity alu is cond : in condition_t; op_group : in op_info_t; left_operand : in gp_register_t; - right_operand : in gp_register_t; + right_operand : in gp_register_t; + displacement : in gp_register_t; op_detail : in op_opt_t; alu_state : in alu_result_rec; alu_result : out alu_result_rec; diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd index 634c7d1..9f29b0b 100755 --- a/cpu/src/alu_b.vhd +++ b/cpu/src/alu_b.vhd @@ -21,37 +21,42 @@ architecture behaviour of alu is ); end component exec_op; - signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec; + signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec; + signal left, right : gp_register_t; begin add_inst : entity work.exec_op(add_op) - port map(clk,reset,left_operand, right_operand, op_detail, alu_state, add_result); + port map(clk,reset,left, right, op_detail, alu_state, add_result); and_inst : entity work.exec_op(and_op) - port map(clk,reset,left_operand, right_operand, op_detail, alu_state, and_result); + port map(clk,reset,left, right, op_detail, alu_state, and_result); or_inst : entity work.exec_op(or_op) - port map(clk,reset,left_operand, right_operand, op_detail, alu_state, or_result); + port map(clk,reset,left, right, op_detail, alu_state, or_result); xor_inst : entity work.exec_op(xor_op) - port map(clk,reset,left_operand, right_operand, op_detail, alu_state, xor_result); + port map(clk,reset,left, right, op_detail, alu_state, xor_result); shift_inst : entity work.exec_op(shift_op) - port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result); + port map(clk,reset,left, right, op_detail, alu_state, shift_result); -calc: process(left_operand, right_operand, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result) +calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result) variable result_v : alu_result_rec; variable res_prod : std_logic; variable cond_met : std_logic; - variable mem_en : std_logic; + variable mem_en : std_logic; + variable mem_op : std_logic; begin result_v := alu_state; result_v.result := add_result.result; res_prod := '1'; - mem_en := '0'; - addr <= add_result.result; + mem_en := '0'; + mem_op := '0'; + addr <= add_result.result; + left <= left_operand; + right <= right_operand; case cond is when COND_NZERO => @@ -101,8 +106,16 @@ begin when SHIFT_OP => result_v := shift_result; when LDST_OP => + res_prod := '0'; + mem_op := '1'; if op_detail(IMM_OPT) = '1' then result_v.result := right_operand; + res_prod := '1'; + mem_op := '0'; + end if; + if op_detail(ST_OPT) = '1' then + right <= displacement; + mem_en := '1'; end if; end case; @@ -119,10 +132,9 @@ begin end if; result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met; - result_v.mem_en := mem_en and cond_met; + result_v.mem_en := mem_en and cond_met; + result_v.mem_op := mem_op and cond_met; - - data <= add_result.result; alu_result <= result_v; end process calc; diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd index 13285d9..7e1562d 100755 --- a/cpu/src/alu_pkg.vhd +++ b/cpu/src/alu_pkg.vhd @@ -84,11 +84,10 @@ package alu_pkg is op_group : in op_info_t; left_operand : in gp_register_t; right_operand : in gp_register_t; + displacement : in gp_register_t; op_detail : in op_opt_t; alu_state : in alu_result_rec; - alu_result : out alu_result_rec; - addr : out gp_register_t; - data : out gp_register_t + alu_result : out alu_result_rec ); end component alu; diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd index 8d3ac51..dd6350c 100755 --- a/cpu/src/common_pkg.vhd +++ b/cpu/src/common_pkg.vhd @@ -52,7 +52,8 @@ package common_pkg is constant ARITH_OPT : integer := 1; constant CARRY_OPT : integer := 2; - + constant ST_OPT : integer := 2; + constant RIGHT_OPT : integer := 3; constant NO_PSW_OPT : integer := 4;--no sharing diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd index 8f97d9f..87fb473 100644 --- a/cpu/src/decoder_b.vhd +++ b/cpu/src/decoder_b.vhd @@ -264,6 +264,7 @@ begin instr_s.reg_src1_addr := instruction(18 downto 15); -- mem addr instr_s.displacement(14 downto 0) := instruction(14 downto 0); instr_s.op_detail(NO_PSW_OPT) := '1'; + instr_s.op_detail(ST_OPT) := '1'; instr_s.op_group := LDST_OP; end if; diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd index 73c7bf2..79a3661 100644 --- a/cpu/src/execute_stage_b.vhd +++ b/cpu/src/execute_stage_b.vhd @@ -29,7 +29,7 @@ begin alu_inst : alu port map(clk, reset, condition, op_group, - left_operand, right_operand, op_detail, alu_state, alu_nxt,addr,data); + left_operand, right_operand, dec_instr.displacement, op_detail, alu_state, alu_nxt); gpm_inst : gpm generic map(RESET_VALUE) @@ -105,6 +105,9 @@ dmem_write_en <= alu_nxt.mem_en; hword <= alu_nxt.hw_op; --hword <= reg.result(1); byte_s <= alu_nxt.byte_op; + +addr <= alu_nxt.result; +data <= right_operand; --byte_s <= reg.result(2); end behav; diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd index 6db0659..1093b1b 100644 --- a/cpu/src/r_w_ram_b.vhd +++ b/cpu/src/r_w_ram_b.vhd @@ -17,6 +17,8 @@ architecture behaviour of r_w_ram is 2 => "11101101000110000000000000100000", -- r3 = 4 3 => "11100000001000010001100000000000", -- r4 = r2 + r3 4 => "11100010001010100000100000000000", -- r5 = r4 and r1 + 5 => "11100111101010100000000000000001", -- stw r5,r4,1 + others => x"F0000000"); -- signal ram : RAM_TYPE := ( 0 => "11100000000100001000000000000000", --add r2, r1, r0 => r2 = 1 -- 2.25.1