From 51ceb8fbeead4e281090bffefd2d9f1757c23955 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Markus=20Hofst=C3=A4tter?= Date: Mon, 15 Nov 2010 17:58:40 +0100 Subject: [PATCH] Fixed some bugs. --- cpu/sim/testcore.do | 25 +++++++++++++++++++ cpu/src/alu.vhd | 2 +- cpu/src/alu_b.vhd | 13 +++++----- cpu/src/alu_pkg.vhd | 4 +-- cpu/src/core_pkg.vhd | 23 ++++++++++++++--- cpu/src/exec_op/add_op_b.vhd | 12 ++++----- cpu/src/exec_op/shift_op_b.vhd | 11 +++------ cpu/src/execute_stage.vhd | 8 ++++-- cpu/src/execute_stage_b.vhd | 15 ++++++++---- cpu/src/extension_pkg.vhd | 4 +-- cpu/src/gpm.vhd | 6 ++--- cpu/src/gpm_b.vhd | 45 ++++++---------------------------- cpu/src/gpm_pkg.vhd | 41 +++++++++++++++++++++++++++++++ cpu/src/pipeline_tb.vhd | 33 ++++++++++++++++++++++--- cpu/src/writeback_stage.vhd | 4 ++- cpu/src/writeback_stage_b.vhd | 21 ++++++++++------ 16 files changed, 177 insertions(+), 90 deletions(-) create mode 100644 cpu/src/gpm_pkg.vhd diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do index da92a48..6f5b7c8 100644 --- a/cpu/sim/testcore.do +++ b/cpu/sim/testcore.do @@ -14,6 +14,31 @@ vcom -work work ../src/fetch_stage.vhd vcom -work work ../src/fetch_stage_b.vhd vcom -work work ../src/decode_stage.vhd vcom -work work ../src/decode_stage_b.vhd + +vcom -work work ../src/alu_pkg.vhd +vcom -work work ../src/extension_pkg.vhd +vcom -work work ../src/gpm_pkg.vhd + +vcom -work work ../src/exec_op.vhd +vcom -work work ../src/exec_op/add_op_b.vhd +vcom -work work ../src/exec_op/and_op_b.vhd +vcom -work work ../src/exec_op/or_op_b.vhd +vcom -work work ../src/exec_op/xor_op_b.vhd +vcom -work work ../src/exec_op/shift_op_b.vhd + +vcom -work work ../src/alu.vhd +vcom -work work ../src/alu_b.vhd + +vcom -work work ../src/gpm.vhd +vcom -work work ../src/gpm_b.vhd + +vcom -work work ../src/execute_stage.vhd +vcom -work work ../src/execute_stage_b.vhd + + +vcom -work work ../src/writeback_stage.vhd +vcom -work work ../src/writeback_stage_b.vhd + vcom -work work ../src/pipeline_tb.vhd vsim work.pipeline_conf_beh -t ns diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd index 02401db..7950c6c 100755 --- a/cpu/src/alu.vhd +++ b/cpu/src/alu.vhd @@ -13,7 +13,7 @@ entity alu is clk : in std_logic; reset : in std_logic; --operation inputs - condition : in condition_t; + cond : in condition_t; op_group : in op_info_t; left_operand : in gp_register_t; right_operand : in gp_register_t; diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd index 78696f2..3fb3434 100755 --- a/cpu/src/alu_b.vhd +++ b/cpu/src/alu_b.vhd @@ -38,7 +38,7 @@ begin shift_inst : exec_op port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result); -calc: process(condition, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result) +calc: process(cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result) variable result_v : alu_result_rec; variable res_prod : std_logic; variable cond_met : std_logic; @@ -49,9 +49,9 @@ begin result_v.result := add_result.result; res_prod := '1'; mem_en := '0'; - addr <= add_result; + addr <= add_result.result; - case condition is + case cond is when COND_NZERO => cond_met := not(alu_state.status.zero); when COND_ZERO => @@ -83,7 +83,8 @@ begin when COND_ALWAYS => cond_met := '1'; when COND_NEVER => - cond_met := '0'; + cond_met := '0'; + when others => null; end case; case op_group is @@ -109,11 +110,11 @@ begin result_v.status := alu_state.status; end if; - result_v.new_val := not(op_detail(NO_DST_OPT)) and res_prod and cond_met; + result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met; result_v.mem_en := mem_en and cond_met; - data <= add_result; + data <= add_result.result; alu_result <= result_v; end process calc; diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd index 8936535..ead1ac6 100755 --- a/cpu/src/alu_pkg.vhd +++ b/cpu/src/alu_pkg.vhd @@ -28,7 +28,7 @@ package alu_pkg is status : status_rec; --stackpointer : gp_register_t; - alu_jmp : std_logic; + alu_jump : std_logic; brpr : std_logic; reg_op : std_logic; mem_op : std_logic; @@ -80,7 +80,7 @@ package alu_pkg is clk : in std_logic; reset : in std_logic; --operation inputs - condition : in condition_t; + cond : in condition_t; op_group : in op_info_t; left_operand : in gp_register_t; right_operand : in gp_register_t; diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd index 24d06a2..13ac382 100644 --- a/cpu/src/core_pkg.vhd +++ b/cpu/src/core_pkg.vhd @@ -74,17 +74,32 @@ package core_pkg is end component decoder; component execute_stage is + generic ( -- active reset value - RESET_VALUE : std_logic; + RESET_VALUE : std_logic -- active logic value - LOGIC_ACT : std_logic + --LOGIC_ACT : std_logic; ); port( --System inputs clk : in std_logic; - reset : in std_logic + reset : in std_logic; + dec_instr : in dec_op; + + --System output + result : out gp_register_t;--reg + result_addr : out gp_addr_t;--reg + addr : out word_t; --memaddr + data : out gp_register_t; --mem data --ureg + alu_jump : out std_logic;--reg + brpr : out std_logic; --reg + wr_en : out std_logic;--regop --reg + dmem : out std_logic;--memop + dmem_write_en : out std_logic; + hword : out std_logic; + byte_s : out std_logic ); end component execute_stage; @@ -101,7 +116,7 @@ package core_pkg is port( --System inputs clk : in std_logic; - reset : in std_logic + reset : in std_logic; result : in gp_register_t; --reg (alu result or jumpaddr) result_addr : in gp_addr_t; --reg diff --git a/cpu/src/exec_op/add_op_b.vhd b/cpu/src/exec_op/add_op_b.vhd index 919c795..88e34d4 100644 --- a/cpu/src/exec_op/add_op_b.vhd +++ b/cpu/src/exec_op/add_op_b.vhd @@ -31,7 +31,7 @@ begin l_neg := left_operand(gp_register_t'high); carry_res := unsigned('0' & left_operand)+addcarry; - oflo1 := add_oflo(l_neg,'0',std_logic_vector(carry_res)(gp_register_t'high)); + oflo1 := add_oflo(l_neg,'0',carry_res(gp_register_t'high)); if sub = '1' then tmp_right_operand := unsigned('0' & complement); @@ -39,15 +39,15 @@ begin tmp_right_operand := unsigned('0' & right_operand); end if; - l_neg := std_logic_vector(carry_res)(gp_register_t'high); - r_neg := std_logic_vector(tmp_right_operand)(gp_register_t'high); + l_neg := carry_res(gp_register_t'high); + r_neg := tmp_right_operand(gp_register_t'high); carry_res := carry_res + tmp_right_operand; - oflo2 := add_oflo(l_neg,r_neg,std_logic_vector(carry_res)(gp_register_t'high)); + oflo2 := add_oflo(l_neg,r_neg,carry_res(gp_register_t'high)); - alu_result_v.result := std_logic_vector(carry_res)(gp_register_t'range); - alu_result_v.status.carry := std_logic_vector(carry_res)(carry_res'high); + alu_result_v.result := std_logic_vector(carry_res(gp_register_t'range)); + alu_result_v.status.carry := carry_res(carry_res'high); alu_result_v.status.carry := oflo1 or oflo2; diff --git a/cpu/src/exec_op/shift_op_b.vhd b/cpu/src/exec_op/shift_op_b.vhd index 7f00dcf..6e17280 100644 --- a/cpu/src/exec_op/shift_op_b.vhd +++ b/cpu/src/exec_op/shift_op_b.vhd @@ -7,17 +7,12 @@ use work.alu_pkg.all; architecture shift_op of exec_op is - signal logic, ls, carry : std_logic; + signal arith, rs, carry : std_logic; begin -<<<<<<< HEAD arith <= op_detail(ARITH_OPT); rs <= op_detail(RIGHT_OPT); -======= - logic <= op_detail(ARITH_OPT); - ls <= op_detail(RIGHT_OPT); ->>>>>>> 05fc0d5300956fef107bbb8507a6480ee11695ff carry <= op_detail(CARRY_OPT); calc: process(left_operand, right_operand, arith,rs, carry, alu_state) @@ -30,13 +25,13 @@ begin if rs = '1' then tmp_sb := (carry and alu_state.status.carry and not(arith)) or (arith and left_operand(gp_register_t'high)); tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry); - tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0)); + tmp_shift := tmp_shift sra to_integer(unsigned(right_operand(SHIFT_WIDTH-1 downto 0))); alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0); else tmp_sb := (carry and alu_state.status.carry and not(arith)); tmp_shift := to_bitvector(alu_state.status.carry & left_operand & tmp_sb); - tmp_shift := tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0)); + tmp_shift := tmp_shift sla to_integer(unsigned(right_operand(SHIFT_WIDTH-1 downto 0))); alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high); end if; diff --git a/cpu/src/execute_stage.vhd b/cpu/src/execute_stage.vhd index 9ca96bc..c5d6817 100644 --- a/cpu/src/execute_stage.vhd +++ b/cpu/src/execute_stage.vhd @@ -2,11 +2,15 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; +use work.common_pkg.all; +use work.alu_pkg.all; +use work.gpm_pkg.all; + entity execute_stage is generic ( -- active reset value - RESET_VALUE : std_logic; + RESET_VALUE : std_logic -- active logic value --LOGIC_ACT : std_logic; @@ -26,7 +30,7 @@ entity execute_stage is brpr : out std_logic; --reg wr_en : out std_logic;--regop --reg dmem : out std_logic;--memop - dmem_wr_en : out std_logic; + dmem_write_en : out std_logic; hword : out std_logic; byte_s : out std_logic ); diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd index 080fb00..1f2c194 100644 --- a/cpu/src/execute_stage_b.vhd +++ b/cpu/src/execute_stage_b.vhd @@ -4,6 +4,7 @@ use IEEE.numeric_std.all; use work.common_pkg.all; use work.alu_pkg.all; +use work.gpm_pkg.all; architecture behav of execute_stage is @@ -28,14 +29,18 @@ begin alu_inst : alu port map(clk, reset, condition, op_group, - op_detail, left_operand, right_operand, alu_state, alu_nxt,addr,data); + left_operand, right_operand, op_detail, alu_state, alu_nxt,addr,data); + +gpm_inst : gpm + generic map(RESET_VALUE) + port map(clk,reset,alu_nxt,psw); syn: process(clk, reset) begin if reset = RESET_VALUE then - reg.alu_jmp <= '0'; + reg.alu_jump <= '0'; reg.brpr <= '0'; reg.wr_en <= '0'; reg.result <= (others =>'0'); @@ -69,14 +74,14 @@ begin reg_nxt.alu_jump <= alu_nxt.alu_jump; reg_nxt.wr_en <= alu_nxt.reg_op; reg_nxt.result <= alu_nxt.result; - reg_nxt.reg_addr <= alu_nxt.result_addr; + reg_nxt.res_addr <= alu_nxt.result_addr; end process asyn; result <= reg.result; result_addr <= reg.res_addr; -alu_jmp <= reg.alu_jump; -brbr <= reg.brpr; +alu_jump <= reg.alu_jump; +brpr <= reg.brpr; wr_en <= reg.wr_en; dmem <= alu_nxt.mem_op; dmem_write_en <= alu_nxt.mem_en; diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd index bf58a27..be46852 100644 --- a/cpu/src/extension_pkg.vhd +++ b/cpu/src/extension_pkg.vhd @@ -15,8 +15,8 @@ package extension_pkg is wr_en : std_logic; byte_en : std_logic_vector(gp_register_t'length/byte_t'length-1 downto 0); - data : data_ram_word_t; - addr : data_addr_t; + data : gp_register_t; + addr : gp_register_t; end record; diff --git a/cpu/src/gpm.vhd b/cpu/src/gpm.vhd index 428bdbb..1012c7b 100644 --- a/cpu/src/gpm.vhd +++ b/cpu/src/gpm.vhd @@ -4,13 +4,13 @@ use IEEE.numeric_std.all; use work.common_pkg.all; use work.alu_pkg.all; -use work.extension_pgk.all; +use work.extension_pkg.all; entity gpm is generic ( -- active reset value - RESET_VALUE : std_logic; + RESET_VALUE : std_logic -- active logic value --LOGIC_ACT : std_logic @@ -26,7 +26,7 @@ entity gpm is --input --output - psw : out status_rec; + psw : out status_rec --to memcnt --addr : out gp_register_t; --mem_en : out std_logic; diff --git a/cpu/src/gpm_b.vhd b/cpu/src/gpm_b.vhd index 0818304..7327a9f 100644 --- a/cpu/src/gpm_b.vhd +++ b/cpu/src/gpm_b.vhd @@ -5,59 +5,28 @@ use IEEE.numeric_std.all; use work.common_pkg.all; use work.alu_pkg.all; -entity gpm is - - generic ( - -- active reset value - RESET_VALUE : std_logic; - -- active logic value - --LOGIC_ACT : std_logic - - ); - port( - --System inputs - clk : in std_logic; - reset : in std_logic; - - --exti : in extmod_rec; - --alu outpus - alu_nxt : in alu_result_rec; - --input - - --output - psw : out status_rec; - --to memcnt - --addr : out gp_register_t; - --mem_en : out std_logic; - --ldst : out std_logic; - --, hw,byte: std_logic; - --to output bus - --exto : out data_ram_word_t - - ); - -end gpm; - architecture behaviour of gpm is type gpm_internal is record status : status_rec; end record gpm_internal; -reg, reg_nxt : gpm_internal; +signal reg, reg_nxt : gpm_internal; begin syn : process (clk, reset) - if reset = RESET_VALUE then - reg <= (('0','0','0','0')); +begin + if (reset = RESET_VALUE) then + reg.status <= ('0','0','0','0'); elsif rising_edge(clk) then reg <= reg_nxt; end if; end process syn; asyn : process (clk, reset) - reg_nxt <= alu_nxt.status; +begin + reg_nxt.status <= alu_nxt.status; end process asyn; -psw <= reg; +psw <= reg.status; end architecture behaviour; diff --git a/cpu/src/gpm_pkg.vhd b/cpu/src/gpm_pkg.vhd new file mode 100644 index 0000000..281878b --- /dev/null +++ b/cpu/src/gpm_pkg.vhd @@ -0,0 +1,41 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.common_pkg.all; +use work.alu_pkg.all; + +package gpm_pkg is + component gpm is + + generic ( + -- active reset value + RESET_VALUE : std_logic + -- active logic value + --LOGIC_ACT : std_logic + + ); + port( + --System inputs + clk : in std_logic; + reset : in std_logic; + + --exti : in extmod_rec; + --alu outpus + alu_nxt : in alu_result_rec; + --input + + --output + psw : out status_rec + --to memcnt + --addr : out gp_register_t; + --mem_en : out std_logic; + --ldst : out std_logic; + --, hw,byte: std_logic; + --to output bus + --exto : out data_ram_word_t + + ); + + end component gpm; +end package gpm_pkg; diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd index e856e69..c1c6b0c 100644 --- a/cpu/src/pipeline_tb.vhd +++ b/cpu/src/pipeline_tb.vhd @@ -4,7 +4,6 @@ use IEEE.numeric_std.all; use work.common_pkg.all; use work.core_pkg.all; - ------------------------------------------------------------------------------- -- ENTITY ------------------------------------------------------------------------------- @@ -37,6 +36,18 @@ architecture behavior of pipeline_tb is signal reg_we_pin : std_logic; signal to_next_stage_pin : dec_op; + signal result_pin : gp_register_t;--reg + signal result_addr_pin : gp_addr_t;--reg + signal addr_pin : word_t; --memaddr + signal data_pin : gp_register_t; --mem data --ureg + signal alu_jump_pin : std_logic;--reg + signal brpr_pin : std_logic; --reg + signal wr_en_pin : std_logic;--regop --reg + signal dmem_pin : std_logic;--memop + signal dmem_wr_en_pin : std_logic; + signal hword_pin : std_logic; + signal byte_s_pin : std_logic; + begin -- instruction_ram : r_w_ram @@ -101,6 +112,16 @@ begin to_next_stage => to_next_stage_pin ); + exec_st : execute_stage + generic map('0') + port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin, result_pin, result_addr_pin,addr_pin, + data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin); + + writeback_st : writeback_stage + generic map('0', '1') + port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, + wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, + reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin); @@ -133,9 +154,9 @@ begin -- initial reset ----------------------------------------------------------------------------- sys_res_n_pin <= '0'; - reg_w_addr_pin <= (others => '0'); - reg_wr_data_pin <= (others => '0'); - reg_we_pin <= '0'; +-- reg_w_addr_pin <= (others => '0'); +-- reg_wr_data_pin <= (others => '0'); +-- reg_we_pin <= '0'; icwait(10); dummy <= '1'; @@ -166,6 +187,10 @@ configuration pipeline_conf_beh of pipeline_tb is end for; for decode_st : decode_stage use entity work.decode_stage(behav); end for; + for exec_st : execute_stage use entity work.execute_stage(behav); + end for; + for writeback_st : writeback_stage use entity work.writeback_stage(behav); + end for; end for; end pipeline_conf_beh; diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd index 7d6e3c2..256fa55 100644 --- a/cpu/src/writeback_stage.vhd +++ b/cpu/src/writeback_stage.vhd @@ -2,13 +2,15 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; +use work.common_pkg.all; + entity writeback_stage is generic ( -- active reset value RESET_VALUE : std_logic; -- active logic value - LOGIC_ACT : std_logic; + LOGIC_ACT : std_logic ); port( diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd index eb09e1e..94af88c 100644 --- a/cpu/src/writeback_stage_b.vhd +++ b/cpu/src/writeback_stage_b.vhd @@ -2,34 +2,38 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; +use work.common_pkg.all; use work.core_pkg.all; -architecture behav of writeback_stage is +use work.mem_pkg.all; +architecture behav of writeback_stage is -begin signal data_ram_read : word_t; signal wb_reg, wb_reg_nxt : writeback_rec; +begin + + data_ram : r_w_ram generic map ( - PHYS_DATA_ADDR_WIDTH, + DATA_ADDR_WIDTH, WORD_WIDTH ) port map ( clk, - wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2), - wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2), + wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2), + wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2), wb_reg_nxt.dmem_write_en, ram_data, data_ram_read ); -syn: process(sys_clk, reset) +syn: process(clk, reset) begin @@ -39,7 +43,7 @@ begin wb_reg_nxt.dmem_write_en <= '0'; wb_reg_nxt.hword <= '0'; wb_reg_nxt.byte_s <= '0'; - elsif rising_edge(sys_clk) then + elsif rising_edge(clk) then wb_reg <= wb_reg_nxt; end if; @@ -54,7 +58,7 @@ end process; -shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword_hl, wb_reg, result) +shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result) begin wb_reg_nxt.address <= address; @@ -82,6 +86,7 @@ begin when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8); when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16); when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24); + when others => null; end case; end if; end if; -- 2.25.1