From: Martin Perner <martin@perner.cc>
Date: Wed, 19 Jan 2011 18:24:33 +0000 (+0100)
Subject: removed 7seg from DT
X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=calu.git;a=commitdiff_plain;h=a37bfd1075f405931099ba5cc347b3954855675e

removed 7seg from DT
---

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 8f24a13..bd13a9c 100644
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -159,10 +159,10 @@ package core_pkg is
 			im_addr : out gp_register_t;
 			im_data : out gp_register_t;
 			
-			sseg0 : out std_logic_vector(0 to 6);
-			sseg1 : out std_logic_vector(0 to 6);
-			sseg2 : out std_logic_vector(0 to 6);
-			sseg3 : out std_logic_vector(0 to 6);
+			--sseg0 : out std_logic_vector(0 to 6);
+			--sseg1 : out std_logic_vector(0 to 6);
+			--sseg2 : out std_logic_vector(0 to 6);
+			--sseg3 : out std_logic_vector(0 to 6);
 
 			int_req : out interrupt_t
 
diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index f5354e3..a8d3bde 100644
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -18,12 +18,12 @@ entity core_top is
 		  -- uart
 			bus_tx : out std_logic;
 			bus_rx : in std_logic;
-			led2 : out std_logic;
+			led2 : out std_logic
 			
-			sseg0 : out std_logic_vector(0 to 6);
-			sseg1 : out std_logic_vector(0 to 6);
-			sseg2 : out std_logic_vector(0 to 6);
-			sseg3 : out std_logic_vector(0 to 6)
+			--sseg0 : out std_logic_vector(0 to 6);
+			--sseg1 : out std_logic_vector(0 to 6);
+			--sseg2 : out std_logic_vector(0 to 6);
+			--sseg3 : out std_logic_vector(0 to 6)
 		);
 
 end core_top;
@@ -180,7 +180,8 @@ begin
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
 				-- instruction memory program port :D
 				new_im_data, im_addr, im_data,
-				sseg0, sseg1, sseg2, sseg3, int_req);
+				--sseg0, sseg1, sseg2, sseg3,
+				 int_req);
 
 
 syn: process(sys_clk, sys_res, soft_res)
diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index ea82a1e..ff31450 100644
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -44,10 +44,10 @@ entity writeback_stage is
 			im_addr : out gp_register_t;
 			im_data : out gp_register_t;
 			
-			sseg0 : out std_logic_vector(0 to 6);
-			sseg1 : out std_logic_vector(0 to 6);
-			sseg2 : out std_logic_vector(0 to 6);
-			sseg3 : out std_logic_vector(0 to 6);
+			--sseg0 : out std_logic_vector(0 to 6);
+			--sseg1 : out std_logic_vector(0 to 6);
+			--sseg2 : out std_logic_vector(0 to 6);
+			--sseg3 : out std_logic_vector(0 to 6);
 
 			int_req : out interrupt_t
 
diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 6a3a4e6..569f2c6 100755
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -95,6 +95,8 @@ imp : extension_imp
 			new_im_data_out
 		);
 	
+	rem7seg: if "a" /= "a" generate
+
 	altera_7seg: if FPGATYPE /= "s3e" generate
 sseg : extension_7seg
 	generic map(
@@ -103,13 +105,15 @@ sseg : extension_7seg
 	port map(
 		clk,
 		reset,
-		ext_7seg,
-		sseg0,
-		sseg1,
-		sseg2,
-		sseg3
+		--ext_7seg,
+		ext_7seg
+		--sseg0,
+		--sseg1,
+		--sseg2,
+		--sseg3
 		);
 	end generate;
+	end generate;
 
 interrupt : extension_interrupt
 	generic map(
diff --git a/dt/.gitignore b/dt/.gitignore
index c949f28..2429abe 100644
--- a/dt/.gitignore
+++ b/dt/.gitignore
@@ -1,18 +1,12 @@
 db/
 incremental_db
 work/
-dt.asm.rpt
-dt.done
-dt.dpf
-dt.fit.rpt
-dt.fit.summary
-dt.flow.rpt
-dt.map.rpt
-dt.map.summary
-dt.pin
-dt.pof
-dt.rbf
-dt.sof
+*.done
+*.dpf
+*.pin
+*.pof
+*.rbf
+*.sof
 dt.*.rpt
 dt.*.summary
 output_file.pof
diff --git a/dt/dt.qpf b/dt/dt.qpf
index 86412f0..e7fbff1 100644
--- a/dt/dt.qpf
+++ b/dt/dt.qpf
@@ -18,13 +18,14 @@
 #
 # Quartus II
 # Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
-# Date created = 15:08:54  December 16, 2010
+# Date created = 12:37:50  January 18, 2011
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "10.0"
-DATE = "15:08:54  December 16, 2010"
+DATE = "12:37:50  January 18, 2011"
 
 # Revisions
 
+PROJECT_REVISION = "DSE"
 PROJECT_REVISION = "dt"